From fb781882f789841cd3f50e41a8a65086cafb29c5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Laptop Date: Mon, 3 Jun 2019 15:42:50 +0200 Subject: [PATCH 01/30] Included doxygen config. --- .gitignore | 1 + DRAMSys/docs/doxyCfg.cfg | 1228 +++++++++++++++++++ DRAMSys/library/src/controller/Controller.h | 2 +- DRAMSys/library/src/simulation/Arbiter.h | 89 +- 4 files changed, 1278 insertions(+), 42 deletions(-) create mode 100644 DRAMSys/docs/doxyCfg.cfg diff --git a/.gitignore b/.gitignore index 02d40fb3..c7425d6f 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,4 @@ DRAMSys/analyzer/scripts/__pycache__/ *.autosave *__pycache__* DRAMSys/gem5/boot_linux/linux-aarch32-ael.img +DRAMSys/docs/doxygen diff --git a/DRAMSys/docs/doxyCfg.cfg b/DRAMSys/docs/doxyCfg.cfg new file mode 100644 index 00000000..ea4940db --- /dev/null +++ b/DRAMSys/docs/doxyCfg.cfg @@ -0,0 +1,1228 @@ +# Doxyfile 1.4.4 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = DRAMSys + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = doxygen + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, +# Dutch, Finnish, French, German, Greek, Hungarian, Italian, Japanese, +# Japanese-en (Japanese with English messages), Korean, Korean-en, Norwegian, +# Polish, Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, +# Swedish, and Ukrainian. + +OUTPUT_LANGUAGE = English + +# This tag can be used to specify the encoding used in the generated output. +# The encoding is not always determined by the language that is chosen, +# but also whether or not the output is meant for Windows or non-Windows users. +# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES +# forces the Windows encoding (this is the default for the Windows binary), +# whereas setting the tag to NO uses a Unix-style encoding (the default for +# all platforms other than Windows). + +USE_WINDOWS_ENCODING = NO + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like the Qt-style comments (thus requiring an +# explicit @brief command for a brief description. + +JAVADOC_AUTOBRIEF = YES + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +DETAILS_AT_TOP = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources +# only. Doxygen will then generate output that is more tailored for Java. +# For instance, namespaces will be presented as packages, qualified scopes +# will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = YES + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = YES + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is YES. + +SHOW_DIRECTORIES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from the +# version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the progam writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be abled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = ../ + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx +# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix filesystem feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES (the default) +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES (the default) +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 4 + +# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be +# generated containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = NO + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = NO + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_PREDEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse +# the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option is superseded by the HAVE_DOT option below. This is only a +# fallback. It is recommended to install and use dot, since it yields more +# powerful graphs. + +CLASS_DIAGRAMS = YES + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will +# generate a call dependency graph for every global function or class method. +# Note that enabling this option will significantly increase the time of a run. +# So in most cases it will be better to enable call graphs for selected +# functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width +# (in pixels) of the graphs generated by dot. If a graph becomes larger than +# this value, doxygen will try to truncate the graph, so that it fits within +# the specified constraint. Beware that most browsers cannot cope with very +# large images. + +MAX_DOT_GRAPH_WIDTH = 1024 + +# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height +# (in pixels) of the graphs generated by dot. If a graph becomes larger than +# this value, doxygen will try to truncate the graph, so that it fits within +# the specified constraint. Beware that most browsers cannot cope with very +# large images. + +MAX_DOT_GRAPH_HEIGHT = 1024 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that a graph may be further truncated if the graph's +# image dimensions are not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH +# and MAX_DOT_GRAPH_HEIGHT). If 0 is used for the depth value (the default), +# the graph is not depth-constrained. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, which results in a white background. +# Warning: Depending on the platform used, enabling this option may lead to +# badly anti-aliased labels on the edges of a graph (i.e. they become hard to +# read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = NO + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- + +# The SEARCHENGINE tag specifies whether or not a search engine should be +# used. If set to NO the values of all tags below this one will be ignored. + +SEARCHENGINE = NO diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index c309c02d..c911f996 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -78,7 +78,7 @@ using namespace tlm; DECLARE_EXTENDED_PHASE(PendingRequest); -class Controller: public sc_module, public IController +class Controller : public sc_module, public IController { public: Controller(sc_module_name /*name*/) : diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 7f60913d..4881e664 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -54,7 +54,7 @@ using namespace std; using namespace tlm; -struct Arbiter: public sc_module { +struct Arbiter : public sc_module { public: tlm_utils::multi_passthrough_initiator_socket iSocket; tlm_utils::multi_passthrough_target_socket tSocket; @@ -66,7 +66,8 @@ public: // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i) { + for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i) + { channelIsFree.push_back(true); pendingRequests.push_back(queue()); } @@ -84,32 +85,16 @@ private: vector channelIsFree; - //used to account for the request_accept_delay in the dram controllers + // used to account for the request_accept_delay in the dram controllers // This is a queue of new transactions. The phase of a new request is BEGIN_REQ. vector> pendingRequests; - //used to account for the response_accept_delay in the initiators (traceplayer,core etc.) + // used to account for the response_accept_delay in the initiators (traceplayer, core etc.) // This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP. std::map> receivedResponses; - //used to map the transaction from devices to the arbiter's target socket ID. + // used to map the transaction from devices to the arbiter's target socket ID. std::map routeMap; - // Initiated by dram side - // This function is called when an arbiter's initiator socket receives a transaction from a memory controller - tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay) - { - // Check channel ID - if ((unsigned int)channelId != DramExtension::getExtension( - payload).getChannel().ID()) { - SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); - } - - printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + - bwDelay.to_string()); - payloadEventQueue.notify(payload, phase, bwDelay); - return TLM_ACCEPTED; - } // Initiated by initiator side // This function is called when an arbiter's target socket receives a transaction from a device @@ -118,7 +103,8 @@ private: { sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) - (sc_time_stamp() + fwDelay); - if (phase == BEGIN_REQ) { + if (phase == BEGIN_REQ) + { // adjust address offset: payload.set_address(payload.get_address() - Configuration::getInstance().AddressOffset); @@ -130,7 +116,9 @@ private: // It will extracted from the payload and used later. appendDramExtension(id, payload); payload.acquire(); - } else if (phase == END_RESP) { + } + else if (phase == END_RESP) + { notDelay += Configuration::getInstance().memSpec.clk; // Erase before the payload is released. routeMap.erase(&payload); @@ -143,6 +131,21 @@ private: return TLM_ACCEPTED; } + // Initiated by dram side + // This function is called when an arbiter's initiator socket receives a transaction from a memory controller + tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload, + tlm_phase &phase, sc_time &bwDelay) + { + // Check channel ID + if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID()) + SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); + + printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + + bwDelay.to_string()); + payloadEventQueue.notify(payload, phase, bwDelay); + return TLM_ACCEPTED; + } + virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) { // adjust address offset: @@ -164,7 +167,8 @@ private: assert(channelId < Configuration::getInstance().NumberOfMemChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) - if (phase == BEGIN_REQ) { + if (phase == BEGIN_REQ) + { if (channelIsFree[channelId]) { // This channel was available. Forward the new transaction to the memory controller. channelIsFree[channelId] = false; @@ -173,21 +177,7 @@ private: // This channel is busy. Enqueue the new transaction which phase is BEGIN_REQ. pendingRequests[channelId].push(&payload); } - } else if (phase == END_RESP) { - // Send the END_RESP message to the memory - sendToChannel(channelId, payload, phase, SC_ZERO_TIME); - // Drop one element of the queue of BEGIN_RESP from memory to this device - receivedResponses[initiatorSocket].pop(); - - // Check if there are queued transactoins with phase BEGIN_RESP from memory to this device - if (!receivedResponses[initiatorSocket].empty()) { - // The queue is not empty. - tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front(); - // Send ONE extra BEGIN_RESP to the device - sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME); - } } - // Phases initiated by the target side from arbiter's point of view (memory side) else if (phase == END_REQ) { channelIsFree[channelId] = true; @@ -207,7 +197,9 @@ private: // Mark the channel as busy again. channelIsFree[channelId] = false; } - } else if (phase == BEGIN_RESP) { + } + else if (phase == BEGIN_RESP) + { // Validate the initiatorSocket ID if ((int)initiatorSocket != routeMap[&payload]) { SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); @@ -221,10 +213,25 @@ private: // Enqueue the transaction in BEGIN_RESP phase until the initiator // device acknowledge it (phase changes to END_RESP). receivedResponses[initiatorSocket].push(&payload); - } else { + } + else if (phase == END_RESP) + { + // Send the END_RESP message to the memory + sendToChannel(channelId, payload, phase, SC_ZERO_TIME); + // Drop one element of the queue of BEGIN_RESP from memory to this device + receivedResponses[initiatorSocket].pop(); + + // Check if there are queued transactoins with phase BEGIN_RESP from memory to this device + if (!receivedResponses[initiatorSocket].empty()) { + // The queue is not empty. + tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front(); + // Send ONE extra BEGIN_RESP to the device + sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME); + } + } + else SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); - } } void sendToChannel(unsigned int channelId, tlm_generic_payload &payload, From b90784f54c9f4488d5e940ef2717e5910fb16b64 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 4 Jun 2019 15:51:35 +0200 Subject: [PATCH 02/30] Created cpp file for arbiter. Removed redundant routing table in arbiter. --- DRAMSys/library/library.pro | 3 +- DRAMSys/library/src/simulation/Arbiter.cpp | 250 ++++++++++++++++++ DRAMSys/library/src/simulation/Arbiter.h | 222 +--------------- DRAMSys/library/src/simulation/StlPlayer.h | 10 +- .../library/src/simulation/TracePlayer.cpp | 11 +- DRAMSys/library/src/simulation/TracePlayer.h | 7 +- DRAMSys/library/src/simulation/TraceSetup.cpp | 13 +- 7 files changed, 287 insertions(+), 229 deletions(-) create mode 100644 DRAMSys/library/src/simulation/Arbiter.cpp diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 113fe07d..a1c1b07a 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -143,7 +143,8 @@ SOURCES += \ src/controller/RecordableController.cpp \ src/common/AddressDecoder.cpp \ src/controller/scheduler/grp.cpp \ - src/common/congenAddressDecoder.cpp + src/common/congenAddressDecoder.cpp \ + src/simulation/Arbiter.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp new file mode 100644 index 00000000..f417eb1e --- /dev/null +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Robert Gernhardt + * Matthias Jung + * Eder F. Zulian + */ + +#include "Arbiter.h" + +using namespace std; +using namespace tlm; + +Arbiter::Arbiter(sc_module_name) : payloadEventQueue(this, &Arbiter::peqCallback) +{ + // The arbiter communicates with one or more memory unity through one or more sockets (one or more memory channels). + // Each of the arbiter's initiator sockets is bound to a memory controller's target socket. + // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. + iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); + + for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i) + { + channelIsFree.push_back(true); + pendingRequests.push_back(queue()); + } + + // One or more devices can accesss all the memory units through the arbiter. + // Devices' initiator sockets are bound to arbiter's target sockets. + // As soon the arbiter receives a request in any of its target sockets it should treat and forward it to the proper memory channel. + tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw); + + tSocket.register_transport_dbg(this, &Arbiter::transport_dbg); +} + +// Initiated by initiator side +// This function is called when an arbiter's target socket receives a transaction from a device +tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, + tlm_phase &phase, sc_time &fwDelay) +{ + sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) - + (sc_time_stamp() + fwDelay); + if (phase == BEGIN_REQ) + { + // adjust address offset: + payload.set_address(payload.get_address() - + Configuration::getInstance().AddressOffset); + + // In the begin request phase the socket ID is appended to the payload. + // It will extracted from the payload and used later. + appendDramExtension(id, payload); + payload.acquire(); + } + else if (phase == END_RESP) + { + notDelay += Configuration::getInstance().memSpec.clk; + payload.release(); + } + + printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + + notDelay.to_string()); + payloadEventQueue.notify(payload, phase, notDelay); + return TLM_ACCEPTED; +} + +// Initiated by dram side +// This function is called when an arbiter's initiator socket receives a transaction from a memory controller +tlm_sync_enum Arbiter::nb_transport_bw(int channelId, tlm_generic_payload &payload, + tlm_phase &phase, sc_time &bwDelay) +{ + // Check channel ID + if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID()) + SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); + + printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + + bwDelay.to_string()); + payloadEventQueue.notify(payload, phase, bwDelay); + return TLM_ACCEPTED; +} + +unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) +{ + // adjust address offset: + trans.set_address(trans.get_address() - + Configuration::getInstance().AddressOffset); + + DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress( + trans.get_address()); + return iSocket[decodedAddress.channel]->transport_dbg(trans); +} + +void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) +{ + unsigned int initiatorSocket = DramExtension::getExtension( + payload).getThread().ID(); + unsigned int channelId = DramExtension::getExtension(payload).getChannel().ID(); + + // Check the valid range of initiatorSocket ID and channel Id + assert(channelId < Configuration::getInstance().NumberOfMemChannels); + + // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) + if (phase == BEGIN_REQ) + { + if (channelIsFree[channelId]) { + // This channel was available. Forward the new transaction to the memory controller. + channelIsFree[channelId] = false; + sendToChannel(channelId, payload, phase, SC_ZERO_TIME); + } else { + // This channel is busy. Enqueue the new transaction which phase is BEGIN_REQ. + pendingRequests[channelId].push(&payload); + } + } + // Phases initiated by the target side from arbiter's point of view (memory side) + else if (phase == END_REQ) { + channelIsFree[channelId] = true; + + // The arbiter receives a transaction which phase is END_REQ from memory controller and forwards it to the requester device. + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); + + // This channel is now free! Dispatch a new transaction (phase is BEGIN_REQ) from the queue, if any. Send it to the memory controller. + if (!pendingRequests[channelId].empty()) { + tlm_generic_payload *payloadToSend = pendingRequests[channelId].front(); + pendingRequests[channelId].pop(); + // Send ONE of the enqueued new transactions (phase is BEGIN_REQ) through this channel. + sendToChannel(channelId, *payloadToSend, BEGIN_REQ, SC_ZERO_TIME); + // Mark the channel as busy again. + channelIsFree[channelId] = false; + } + } + else if (phase == BEGIN_RESP) + { + // The arbiter receives a transaction in BEGIN_RESP phase + // (that came from the memory side) and forwards it to the requester + // device + if (receivedResponses[initiatorSocket].empty()) { + sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); + } + // Enqueue the transaction in BEGIN_RESP phase until the initiator + // device acknowledge it (phase changes to END_RESP). + receivedResponses[initiatorSocket].push(&payload); + } + else if (phase == END_RESP) + { + // Send the END_RESP message to the memory + sendToChannel(channelId, payload, phase, SC_ZERO_TIME); + // Drop one element of the queue of BEGIN_RESP from memory to this device + receivedResponses[initiatorSocket].pop(); + + // Check if there are queued transactoins with phase BEGIN_RESP from memory to this device + if (!receivedResponses[initiatorSocket].empty()) { + // The queue is not empty. + tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front(); + // Send ONE extra BEGIN_RESP to the device + sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME); + } + } + else + SC_REPORT_FATAL(0, + "Payload event queue in arbiter was triggered with unknown phase"); +} + +void Arbiter::sendToChannel(unsigned int channelId, tlm_generic_payload &payload, + const tlm_phase &phase, const sc_time &delay) +{ + tlm_phase TPhase = phase; + sc_time TDelay = delay; + iSocket[channelId]->nb_transport_fw(payload, TPhase, TDelay); +} + +void Arbiter::sendToInitiator(unsigned int id, tlm_generic_payload &payload, + const tlm_phase &phase, const sc_time &delay) +{ + tlm_phase TPhase = phase; + sc_time TDelay = delay; + tSocket[id]->nb_transport_bw(payload, TPhase, TDelay); +} + +void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) +{ + // Append Generation Extension + GenerationExtension *genExtension = new GenerationExtension(sc_time_stamp()); + payload.set_auto_extension(genExtension); + + unsigned int burstlength = payload.get_streaming_width(); + DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress(payload.get_address()); + // Check the valid range of decodedAddress + if (addressIsValid(decodedAddress)) { + DramExtension *extension = new DramExtension(Thread(socketId), + Channel(decodedAddress.channel), Bank(decodedAddress.bank), + BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), + Column(decodedAddress.column), burstlength); + payload.set_auto_extension(extension); + } else { + SC_REPORT_FATAL("Arbiter", "Decoded Address is not inside the valid range"); + } +} + +bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) +{ + if (decodedAddress.channel >= AddressDecoder::getInstance().amount["channel"]) { + return false; + } + if (decodedAddress.bank >= AddressDecoder::getInstance().amount["bank"]) { + return false; + } + if (decodedAddress.bankgroup > + AddressDecoder::getInstance().amount["bankgroup"]) { + return false; + } + if (decodedAddress.column >= AddressDecoder::getInstance().amount["column"]) { + return false; + } + if (decodedAddress.row >= AddressDecoder::getInstance().amount["row"]) { + return false; + } + return true; +} + +void Arbiter::printDebugMessage(std::string message) +{ + DebugManager::getInstance().printDebugMessage(this->name(), message); +} diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 4881e664..1c5687b0 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -54,31 +54,14 @@ using namespace std; using namespace tlm; -struct Arbiter : public sc_module { +class Arbiter : public sc_module +{ public: tlm_utils::multi_passthrough_initiator_socket iSocket; tlm_utils::multi_passthrough_target_socket tSocket; - SC_CTOR(Arbiter) : payloadEventQueue(this, &Arbiter::peqCallback) - { - // The arbiter communicates with one or more memory unity through one or more sockets (one or more memory channels). - // Each of the arbiter's initiator sockets is bound to a memory controller's target socket. - // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. - iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - - for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i) - { - channelIsFree.push_back(true); - pendingRequests.push_back(queue()); - } - - // One or more devices can accesss all the memory units through the arbiter. - // Devices' initiator sockets are bound to arbiter's target sockets. - // As soon the arbiter receives a request in any of its target sockets it should treat and forward it to the proper memory channel. - tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw); - - tSocket.register_transport_dbg(this, &Arbiter::transport_dbg); - } + Arbiter(sc_module_name); + SC_HAS_PROCESS(Arbiter); private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; @@ -92,210 +75,31 @@ private: // This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP. std::map> receivedResponses; - // used to map the transaction from devices to the arbiter's target socket ID. - std::map routeMap; - - // Initiated by initiator side // This function is called when an arbiter's target socket receives a transaction from a device tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay) - { - sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) - - (sc_time_stamp() + fwDelay); - if (phase == BEGIN_REQ) - { - // adjust address offset: - payload.set_address(payload.get_address() - - Configuration::getInstance().AddressOffset); - - // Map the payload with socket id. - routeMap[&payload] = id; - - // In the begin request phase the socket ID is appended to the payload. - // It will extracted from the payload and used later. - appendDramExtension(id, payload); - payload.acquire(); - } - else if (phase == END_RESP) - { - notDelay += Configuration::getInstance().memSpec.clk; - // Erase before the payload is released. - routeMap.erase(&payload); - payload.release(); - } - - printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + - notDelay.to_string()); - payloadEventQueue.notify(payload, phase, notDelay); - return TLM_ACCEPTED; - } + tlm_phase &phase, sc_time &fwDelay); // Initiated by dram side // This function is called when an arbiter's initiator socket receives a transaction from a memory controller tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay) - { - // Check channel ID - if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID()) - SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); + tlm_phase &phase, sc_time &bwDelay); - printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + - bwDelay.to_string()); - payloadEventQueue.notify(payload, phase, bwDelay); - return TLM_ACCEPTED; - } + virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans); - virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) - { - // adjust address offset: - trans.set_address(trans.get_address() - - Configuration::getInstance().AddressOffset); - - DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress( - trans.get_address()); - return iSocket[decodedAddress.channel]->transport_dbg(trans); - } - - void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) - { - unsigned int initiatorSocket = DramExtension::getExtension( - payload).getThread().ID(); - unsigned int channelId = DramExtension::getExtension(payload).getChannel().ID(); - - // Check the valid range of initiatorSocket ID and channel Id - assert(channelId < Configuration::getInstance().NumberOfMemChannels); - - // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) - if (phase == BEGIN_REQ) - { - if (channelIsFree[channelId]) { - // This channel was available. Forward the new transaction to the memory controller. - channelIsFree[channelId] = false; - sendToChannel(channelId, payload, phase, SC_ZERO_TIME); - } else { - // This channel is busy. Enqueue the new transaction which phase is BEGIN_REQ. - pendingRequests[channelId].push(&payload); - } - } - // Phases initiated by the target side from arbiter's point of view (memory side) - else if (phase == END_REQ) { - channelIsFree[channelId] = true; - // Validate the initiatorSocket ID - if ((int)initiatorSocket != routeMap[&payload]) { - SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); - } - // The arbiter receives a transaction which phase is END_REQ from memory controller and forwards it to the requester device. - sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); - - // This channel is now free! Dispatch a new transaction (phase is BEGIN_REQ) from the queue, if any. Send it to the memory controller. - if (!pendingRequests[channelId].empty()) { - tlm_generic_payload *payloadToSend = pendingRequests[channelId].front(); - pendingRequests[channelId].pop(); - // Send ONE of the enqueued new transactions (phase is BEGIN_REQ) through this channel. - sendToChannel(channelId, *payloadToSend, BEGIN_REQ, SC_ZERO_TIME); - // Mark the channel as busy again. - channelIsFree[channelId] = false; - } - } - else if (phase == BEGIN_RESP) - { - // Validate the initiatorSocket ID - if ((int)initiatorSocket != routeMap[&payload]) { - SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); - } - // The arbiter receives a transaction in BEGIN_RESP phase - // (that came from the memory side) and forwards it to the requester - // device - if (receivedResponses[initiatorSocket].empty()) { - sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME); - } - // Enqueue the transaction in BEGIN_RESP phase until the initiator - // device acknowledge it (phase changes to END_RESP). - receivedResponses[initiatorSocket].push(&payload); - } - else if (phase == END_RESP) - { - // Send the END_RESP message to the memory - sendToChannel(channelId, payload, phase, SC_ZERO_TIME); - // Drop one element of the queue of BEGIN_RESP from memory to this device - receivedResponses[initiatorSocket].pop(); - - // Check if there are queued transactoins with phase BEGIN_RESP from memory to this device - if (!receivedResponses[initiatorSocket].empty()) { - // The queue is not empty. - tlm_generic_payload *payloadToSend = receivedResponses[initiatorSocket].front(); - // Send ONE extra BEGIN_RESP to the device - sendToInitiator(initiatorSocket, *payloadToSend, BEGIN_RESP, SC_ZERO_TIME); - } - } - else - SC_REPORT_FATAL(0, - "Payload event queue in arbiter was triggered with unknown phase"); - } + void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase); void sendToChannel(unsigned int channelId, tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay) - { - tlm_phase TPhase = phase; - sc_time TDelay = delay; - iSocket[channelId]->nb_transport_fw(payload, TPhase, TDelay); - } + const tlm_phase &phase, const sc_time &delay); void sendToInitiator(unsigned int id, tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay) - { - tlm_phase TPhase = phase; - sc_time TDelay = delay; - tSocket[id]->nb_transport_bw(payload, TPhase, TDelay); - } + const tlm_phase &phase, const sc_time &delay); - void appendDramExtension(int socketId, tlm_generic_payload &payload) - { - // Append Generation Extension - GenerationExtension *genExtension = new GenerationExtension(sc_time_stamp()); - payload.set_auto_extension(genExtension); + void appendDramExtension(int socketId, tlm_generic_payload &payload); - unsigned int burstlength = payload.get_streaming_width(); - DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress( - payload.get_address()); - // Check the valid range of decodedAddress - if (addressIsValid(decodedAddress)) { - DramExtension *extension = new DramExtension(Thread(socketId), - Channel(decodedAddress.channel), Bank(decodedAddress.bank), - BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), - Column(decodedAddress.column), burstlength); - payload.set_auto_extension(extension); - } else { - SC_REPORT_FATAL("Arbiter", "Decoded Address are not inside the valid range"); - } - } + bool addressIsValid(DecodedAddress &decodedAddress); - bool addressIsValid(DecodedAddress &decodedAddress) - { - if (decodedAddress.channel >= AddressDecoder::getInstance().amount["channel"]) { - return false; - } - if (decodedAddress.bank >= AddressDecoder::getInstance().amount["bank"]) { - return false; - } - if (decodedAddress.bankgroup > - AddressDecoder::getInstance().amount["bankgroup"]) { - return false; - } - if (decodedAddress.column >= AddressDecoder::getInstance().amount["column"]) { - return false; - } - if (decodedAddress.row >= AddressDecoder::getInstance().amount["row"]) { - return false; - } - return true; - } - - void printDebugMessage(std::string message) - { - DebugManager::getInstance().printDebugMessage(this->name(), message); - } + void printDebugMessage(std::string message); }; #endif /* ARBITER_H_ */ diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index 8e36b54b..ee5ac0a0 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -86,7 +86,6 @@ public: } else { numberOfTransactions++; } - // Allocate a generic payload for this request. gp *payload = this->allocatePayload(); @@ -170,16 +169,17 @@ public: payload->set_data_ptr(data); payload->set_command(cmd); - if (relative == false) { + if (relative == false) + { // Send the transaction directly or schedule it to be sent in the future. if (sendingTime <= sc_time_stamp()) this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME); else this->payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime - sc_time_stamp()); - } else { - payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime); } + else + payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime); } private: @@ -188,7 +188,7 @@ private: unsigned int burstlength; unsigned int dataLength; - sc_time playerClk; // May be different from from the memory clock! + sc_time playerClk; // May be different from the memory clock! }; #endif // STLPLAYER_H diff --git a/DRAMSys/library/src/simulation/TracePlayer.cpp b/DRAMSys/library/src/simulation/TracePlayer.cpp index e46840b3..793dd904 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.cpp +++ b/DRAMSys/library/src/simulation/TracePlayer.cpp @@ -80,7 +80,6 @@ tlm_sync_enum TracePlayer::nb_transport_bw(tlm_generic_payload &payload, void TracePlayer::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) { - if (phase == BEGIN_REQ) { payload.acquire(); sendToTarget(payload, phase, SC_ZERO_TIME); @@ -99,7 +98,8 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, transactionsReceived++; // If all answers were received: - if (finished == true && numberOfTransactions == transactionsReceived) { + if (finished == true && numberOfTransactions == transactionsReceived) + { this->terminate(); } } else if (phase == END_RESP) { @@ -108,6 +108,13 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, } } +void TracePlayer::sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase, const sc_time &delay) +{ + tlm_phase TPhase = phase; + sc_time TDelay = delay; + iSocket->nb_transport_fw(payload, TPhase, TDelay); +} + void TracePlayer::setNumberOfTransactions(unsigned int n) { numberOfTransactions = n; diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index d03f5ead..dd4cb8ae 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -77,12 +77,7 @@ private: sc_time &bwDelay); void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase); void sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase, - const sc_time &delay) - { - tlm_phase TPhase = phase; - sc_time TDelay = delay; - iSocket->nb_transport_fw(payload, TPhase, TDelay); - } + const sc_time &delay); MemoryManager memoryManager; unsigned int transactionsSent; unsigned int transactionsReceived; diff --git a/DRAMSys/library/src/simulation/TraceSetup.cpp b/DRAMSys/library/src/simulation/TraceSetup.cpp index c64eac3d..79a241d6 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.cpp +++ b/DRAMSys/library/src/simulation/TraceSetup.cpp @@ -56,9 +56,10 @@ traceSetup::traceSetup(std::string uri, simulation->FirstChildElement("tracesetup"); for (tinyxml2::XMLElement *device = - tracesetup->FirstChildElement("device"); - device != NULL; - device = device->NextSiblingElement("device")) { + tracesetup->FirstChildElement("device"); + device != NULL; + device = device->NextSiblingElement("device")) + { sc_time playerClk; unsigned int frequency = device->IntAttribute("clkMhz"); @@ -83,12 +84,12 @@ traceSetup::traceSetup(std::string uri, std::string moduleName = name; // replace all '.' to '_' - std::replace( moduleName.begin(), moduleName.end(), '.', '_'); + std::replace(moduleName.begin(), moduleName.end(), '.', '_'); TracePlayer *player; - if (strcmp(ext.c_str(), "stl") == 0) { + if (ext == "stl") { player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, this); - } else if (strcmp(ext.c_str(), "rstl") == 0) { + } else if (ext == "rstl") { player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, this); } else { std::string error = "Unsupported file extension in " + name; From 84bd62a781fdc7d1b3f4301ef94405246a330d10 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 5 Jun 2019 16:21:26 +0200 Subject: [PATCH 03/30] No changes, some TODOs for future work. --- .../resources/configs/simulator/ddr3.xml | 2 +- DRAMSys/library/src/controller/Controller.cpp | 51 ++++++++++++------- DRAMSys/library/src/controller/Controller.h | 6 +-- .../library/src/controller/scheduler/Fifo.cpp | 19 +++---- .../library/src/controller/scheduler/Fifo.h | 7 +-- .../src/controller/scheduler/FifoStrict.cpp | 8 +-- .../src/controller/scheduler/FifoStrict.h | 2 +- DRAMSys/library/src/simulation/Arbiter.cpp | 4 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- coding-style.md | 2 +- 10 files changed, 61 insertions(+), 42 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index 1613737f..f43e4b8c 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,6 +1,6 @@ - + diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index ebe31027..dfc021ba 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -232,12 +232,14 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_REQ) { notDelay += Configuration::getInstance().memSpec.clk; - //Bandwidth IDLE + // Bandwidth IDLE if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState) { endBandwidthIdleCollector(); } - } else if (phase == END_RESP) { - // Badnwith IDLE + } + else if (phase == END_RESP) { + // Bandwidth IDLE + // TODO: getTotalNumberOfPayloadsInSystem() == 1 && !idleState ?? if (getTotalNumberOfPayloadsInSystem() == 1) { startBandwidthIdleCollector(); } @@ -258,13 +260,15 @@ unsigned int Controller::transport_dbg(tlm::tlm_generic_payload &trans) void Controller::frontendPEQCallback(tlm_generic_payload &payload, const tlm_phase &phase) { - if (phase == BEGIN_REQ) { - printDebugMessage(string("Payload in system: ") + to_string( - getTotalNumberOfPayloadsInSystem())); + if (phase == BEGIN_REQ) + { + printDebugMessage(string("Payload in system: ") + + to_string(getTotalNumberOfPayloadsInSystem())); payload.acquire(); payloadEntersSystem(payload); if (getTotalNumberOfPayloadsInSystem() > - controllerCore->config.MaxNrOfTransactions) { + controllerCore->config.MaxNrOfTransactions) + { printDebugMessage("##Backpressure: Max number of transactions in system reached"); backpressure = &payload; return; @@ -273,12 +277,18 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, sendToFrontend(payload, END_REQ, SC_ZERO_TIME); scheduler->storeRequest(&payload); + // TODO: (current position in code) scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); - } else if (phase == PendingRequest) { + } + else if (phase == PendingRequest) + { // Schedule a pending request. scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); - } else if (phase == END_RESP) { - if (backpressure != NULL) { + } + else if (phase == END_RESP) + { + if (backpressure != NULL) + { printDebugMessage("##Backpressure released"); backpressure->set_response_status(tlm::TLM_OK_RESPONSE); sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME); @@ -292,11 +302,11 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, responseQueue.pop(); payload.release(); - if(!responseQueue.empty()) { + if(!responseQueue.empty()) sendToFrontend(*(responseQueue.front()), BEGIN_RESP, SC_ZERO_TIME); - } - - } else { + } + else + { SC_REPORT_FATAL(0, "Front-end PEQ in controller wrapper was triggered with unknown phase"); } @@ -305,12 +315,14 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, void Controller::payloadEntersSystem(tlm_generic_payload &payload) { Bank bank = DramExtension::getExtension(payload).getBank(); + // TODO: first increase numberOfPayloadsInSystem[bank], then printDebugMessage ?? printDebugMessage( "Payload enters system on bank " + to_string(bank.ID()) + ". Total number of payloads in Controller: " + to_string(getTotalNumberOfPayloadsInSystem())); numberOfPayloadsInSystem[bank]++; // Set Start Time for Simulation + // TODO: startTimeSet always false at this point?? if (startTimeSet == false) { printDebugMessage("Simulation Timer Start"); startTime = sc_time_stamp() - Configuration::getInstance().memSpec.clk; @@ -340,18 +352,21 @@ unsigned int Controller::getTotalNumberOfPayloadsInSystem() void Controller::scheduleNextFromScheduler(Bank bank) { - if (controllerCore->bankIsBusy(bank)) { + if (controllerCore->bankIsBusy(bank)) return; - } bool rescheduled = true; pair nextRequest = scheduler->getNextRequest(bank); if (nextRequest.second != NULL) { schedule(nextRequest.first, *nextRequest.second); - } else { + } + else + { + // TODO: getPendingRequest is only used by SMS scheduler gp *pendingRequest = scheduler->getPendingRequest(bank); - if (pendingRequest != NULL) { + if (pendingRequest != NULL) + { rescheduled = true; frontendPEQ.notify(*(pendingRequest), PendingRequest, Configuration::getInstance().memSpec.clk); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index c911f996..7e524a51 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -82,9 +82,9 @@ class Controller : public sc_module, public IController { public: Controller(sc_module_name /*name*/) : - frontendPEQ(this, &Controller::frontendPEQCallback), dramPEQ(this, - &Controller::dramPEQCallback), controllerCorePEQ(this, - &Controller::controllerCorePEQCallback), + frontendPEQ(this, &Controller::frontendPEQCallback), + dramPEQ(this, &Controller::dramPEQCallback), + controllerCorePEQ(this, &Controller::controllerCorePEQCallback), debugManager(DebugManager::getInstance()) { controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem); diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.cpp b/DRAMSys/library/src/controller/scheduler/Fifo.cpp index 6eb46aa8..305e2798 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fifo.cpp @@ -36,27 +36,28 @@ #include "Fifo.h" -using namespace std; - void Fifo::storeRequest(gp *payload) { - buffer[DramExtension::getExtension(payload).getBank()].emplace_back(payload); + Bank bank = DramExtension::getExtension(payload).getBank(); + buffer[bank].emplace_back(payload); } -pair Fifo::getNextRequest(Bank bank) +std::pair Fifo::getNextRequest(Bank bank) { - if (!buffer[bank].empty()) { + if (!buffer[bank].empty()) + { gp *payload = buffer[bank].front(); Command command = IScheduler::getNextCommand(*payload); if (command == Command::Read || command == Command::ReadA - || command == Command::Write || command == Command::WriteA) { + || command == Command::Write || command == Command::WriteA) + { buffer[bank].pop_front(); } - return pair(command, payload); + return std::pair(command, payload); } - - return pair(Command::NOP, NULL); + else + return std::pair(Command::NOP, NULL); } gp *Fifo::getPendingRequest(Bank /*bank*/) diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.h b/DRAMSys/library/src/controller/scheduler/Fifo.h index 912570d2..dfb5820c 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.h +++ b/DRAMSys/library/src/controller/scheduler/Fifo.h @@ -37,13 +37,14 @@ #ifndef FIFO_H_ #define FIFO_H_ -#include "../core/ControllerCore.h" -#include "../Command.h" -#include "IScheduler.h" #include #include #include +#include "../core/ControllerCore.h" +#include "../Command.h" +#include "IScheduler.h" + class Fifo : public IScheduler { public: diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp index 9b3f8ec3..3f36dd9e 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp @@ -92,7 +92,7 @@ std::pair FifoStrict::getNextRequest( } } - return pair(command, payload); + return std::pair(command, payload); } else { // The next request in the FIFO is NOT for the bank passed as parameter. @@ -116,18 +116,18 @@ std::pair FifoStrict::getNextRequest( // the next command for this request is read or write // NOP will be returned and no operation will be // performed. - return pair(Command::NOP, NULL); + return std::pair(Command::NOP, NULL); } else { // Commands other than read and write are issued normally. - return pair(command, payload); + return std::pair(command, payload); } } } } } - return pair(Command::NOP, NULL); + return std::pair(Command::NOP, NULL); } gp *FifoStrict::getPendingRequest(Bank /*bank*/) diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.h b/DRAMSys/library/src/controller/scheduler/FifoStrict.h index acd22086..4adf3990 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.h +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.h @@ -40,7 +40,7 @@ #define FIFOSTRICT_H #include -#include +//#include #include #include "../core/ControllerCore.h" diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index f417eb1e..0459445d 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -40,7 +40,7 @@ using namespace std; using namespace tlm; -Arbiter::Arbiter(sc_module_name) : payloadEventQueue(this, &Arbiter::peqCallback) +Arbiter::Arbiter(sc_module_name /*name*/) : payloadEventQueue(this, &Arbiter::peqCallback) { // The arbiter communicates with one or more memory unity through one or more sockets (one or more memory channels). // Each of the arbiter's initiator sockets is bound to a memory controller's target socket. @@ -66,6 +66,7 @@ Arbiter::Arbiter(sc_module_name) : payloadEventQueue(this, &Arbiter::peqCallback tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, tlm_phase &phase, sc_time &fwDelay) { + // TODO: clkAlign necessary? sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) - (sc_time_stamp() + fwDelay); if (phase == BEGIN_REQ) @@ -124,6 +125,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) unsigned int channelId = DramExtension::getExtension(payload).getChannel().ID(); // Check the valid range of initiatorSocket ID and channel Id + // TODO: initiatorSocket ID not checked assert(channelId < Configuration::getInstance().NumberOfMemChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 5b48fc92..30b2393e 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -175,7 +175,7 @@ void DRAMSys::logo() void DRAMSys::setupDebugManager(const string &traceName) { auto &dbg = DebugManager::getInstance(); - dbg.writeToConsole = true; + dbg.writeToConsole = false; dbg.writeToFile = true; if (dbg.writeToFile) dbg.openDebugFile(traceName + ".txt"); diff --git a/coding-style.md b/coding-style.md index 7647bd95..80291bc1 100644 --- a/coding-style.md +++ b/coding-style.md @@ -148,7 +148,7 @@ There is a plugin for VIM. More information can be found in ## Applying the Coding Style The script [make_pretty.sh](./utils/make_pretty.sh) applies the coding style -to the project excluding thrid party code. +to the project excluding third party code. ## References From 4454b82363695d235b5d625bd9808160fe394e7d Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 10 Jun 2019 00:52:26 +0200 Subject: [PATCH 04/30] No changes, some TODOs for future work. --- DRAMSys/library/src/common/dramExtension.h | 47 +++++++------------ DRAMSys/library/src/controller/Controller.cpp | 23 ++++++++- DRAMSys/library/src/controller/Controller.h | 16 ++----- .../core/scheduling/checker/ActBChecker.h | 5 +- .../core/scheduling/checker/PreBChecker.cpp | 2 +- .../src/controller/scheduler/FifoStrict.cpp | 4 +- 6 files changed, 48 insertions(+), 49 deletions(-) diff --git a/DRAMSys/library/src/common/dramExtension.h b/DRAMSys/library/src/common/dramExtension.h index 19176cc5..c990e912 100644 --- a/DRAMSys/library/src/common/dramExtension.h +++ b/DRAMSys/library/src/common/dramExtension.h @@ -45,15 +45,13 @@ class Thread { public: - explicit Thread(unsigned int id) : - id(id) - { - } + explicit Thread(unsigned int id) : id(id) {} unsigned int ID() const { return id; } + private: unsigned int id; }; @@ -61,14 +59,13 @@ private: class Channel { public: - explicit Channel(unsigned int id) : - id(id) - { - } + explicit Channel(unsigned int id) : id(id) {} + unsigned int ID() const { return id; } + private: unsigned int id; }; @@ -76,14 +73,13 @@ private: class BankGroup { public: - explicit BankGroup(unsigned int id) : - id(id) - { - } + explicit BankGroup(unsigned int id) : id(id) {} + unsigned int ID() const { return id; } + private: unsigned int id; }; @@ -91,10 +87,8 @@ private: class Bank { public: - Bank(unsigned int id) : - id(id) - { - } + Bank(unsigned int id) : id(id) {} + unsigned int ID() const { return id; @@ -110,7 +104,6 @@ public: return std::to_string(id); } - private: unsigned int id; }; @@ -120,14 +113,9 @@ class Row public: static const Row NO_ROW; - Row() : - id(0), isNoRow(true) - { - } - explicit Row(unsigned int id) : - id(id), isNoRow(false) - { - } + Row() : id(0), isNoRow(true) {} + + explicit Row(unsigned int id) : id(id), isNoRow(false) {} unsigned int ID() const { @@ -135,6 +123,7 @@ public: } const Row operator++(); + private: unsigned int id; bool isNoRow; @@ -145,21 +134,19 @@ private: class Column { public: - explicit Column(unsigned int id) : - id(id) - { - } + explicit Column(unsigned int id) : id(id) {} unsigned int ID() const { return id; } + private: unsigned int id; }; -class DramExtension: public tlm::tlm_extension +class DramExtension : public tlm::tlm_extension { public: DramExtension(); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index dfc021ba..844e5d09 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -39,6 +39,19 @@ #include "Controller.h" #include +Controller::Controller(sc_module_name /*name*/) : + frontendPEQ(this, &Controller::frontendPEQCallback), + dramPEQ(this, &Controller::dramPEQCallback), + controllerCorePEQ(this, &Controller::controllerCorePEQCallback), + debugManager(DebugManager::getInstance()) +{ + controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem); + buildScheduler(); + iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw); + tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw); + tSocket.register_transport_dbg(this, &Controller::transport_dbg); +} + void Controller::buildScheduler() { string selectedScheduler = Configuration::getInstance().Scheduler; @@ -274,6 +287,7 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, return; } payload.set_response_status(tlm::TLM_OK_RESPONSE); + // tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME) sendToFrontend(payload, END_REQ, SC_ZERO_TIME); scheduler->storeRequest(&payload); @@ -291,6 +305,7 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, { printDebugMessage("##Backpressure released"); backpressure->set_response_status(tlm::TLM_OK_RESPONSE); + // tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME) sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME); scheduler->storeRequest(backpressure); @@ -355,6 +370,7 @@ void Controller::scheduleNextFromScheduler(Bank bank) if (controllerCore->bankIsBusy(bank)) return; + // TODO: rescheduled always true? bool rescheduled = true; pair nextRequest = scheduler->getNextRequest(bank); @@ -363,8 +379,8 @@ void Controller::scheduleNextFromScheduler(Bank bank) } else { - // TODO: getPendingRequest is only used by SMS scheduler gp *pendingRequest = scheduler->getPendingRequest(bank); + // TODO: if path (pendingRequest != NULL) is only used by SMS scheduler if (pendingRequest != NULL) { rescheduled = true; @@ -373,8 +389,10 @@ void Controller::scheduleNextFromScheduler(Bank bank) } } + // TODO: only used with FifoStrict scheduler queue blocked; - while (!blockedRequests.empty()) { + while (!blockedRequests.empty()) + { bank = blockedRequests.front(); blockedRequests.pop(); @@ -387,6 +405,7 @@ void Controller::scheduleNextFromScheduler(Bank bank) if (pendingRequest != NULL) { //Pending request if (!rescheduled) { + // TODO: never reached, rescheduled is always true rescheduled = true; frontendPEQ.notify(*(pendingRequest), PendingRequest, Configuration::getInstance().memSpec.clk); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 7e524a51..97ec9e73 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -81,18 +81,7 @@ DECLARE_EXTENDED_PHASE(PendingRequest); class Controller : public sc_module, public IController { public: - Controller(sc_module_name /*name*/) : - frontendPEQ(this, &Controller::frontendPEQCallback), - dramPEQ(this, &Controller::dramPEQCallback), - controllerCorePEQ(this, &Controller::controllerCorePEQCallback), - debugManager(DebugManager::getInstance()) - { - controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem); - buildScheduler(); - iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw); - tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw); - tSocket.register_transport_dbg(this, &Controller::transport_dbg); - } + Controller(sc_module_name); virtual ~Controller() { @@ -112,8 +101,9 @@ public: virtual void send(Trigger trigger, sc_time time, tlm_generic_payload &payload) override; - tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; + tlm_utils::simple_initiator_socket iSocket; + unsigned int getTotalNumberOfPayloadsInSystem(); void scheduleNextFromScheduler(Bank bank) override; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h index 023db94f..0c83d71d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h @@ -33,11 +33,13 @@ */ #ifndef ACTB_CHECKER_H_ #define ACTB_CHECKER_H_ + #include #include "ICommandChecker.h" #include "../../configuration/Configuration.h" #include "../../../ControllerState.h" -class ActBChecker: public ICommandChecker + +class ActBChecker : public ICommandChecker { public: ActBChecker(const Configuration &config, @@ -53,4 +55,5 @@ private: bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const; bool satisfies_nActivateWindow(ScheduledCommand &command) const; }; + #endif /* ACTB_CHECKER_H_ */ diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index a8376a28..97c8a103 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -34,7 +34,7 @@ #include "PreBChecker.h" #include "../../TimingCalculation.h" -void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd)const +void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const { sc_assert(cmd.getCommand() == Command::PreB); ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank()); diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp index 3f36dd9e..00701ce0 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp @@ -61,14 +61,14 @@ std::pair FifoStrict::getNextRequest( // enqueued request until the appropriate sequence of commands is // sent to the DRAM. // - // Every time getNextRequest() it is called it calls + // Every time getNextRequest() is called it calls // getNextCommand() that returns the suitable command to be sent // to the DRAM. // // getNextCommand() returns the proper command based on the // internal status of the DRAM. // - // In the worst case getNextCommand() need to be called three + // In the worst case getNextCommand() needs to be called three // times for a given element in the requests queue: first for // precharge, second for activate and finally for read or write // (accordingly the nature of the request). In contrast, for the From 02803de97cdfc3ec6c592b89b3c3dc35b93118a5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 11 Jun 2019 23:10:45 +0200 Subject: [PATCH 05/30] Code refactoring. --- DRAMSys/library/src/controller/Controller.cpp | 52 ++++++++++++------- DRAMSys/library/src/controller/Controller.h | 4 +- .../src/controller/core/ControllerCore.cpp | 2 +- .../core/configuration/Configuration.h | 3 +- .../library/src/controller/scheduler/Fifo.cpp | 2 + .../library/src/controller/scheduler/Fifo.h | 4 +- .../src/controller/scheduler/IScheduler.cpp | 22 +++++--- 7 files changed, 56 insertions(+), 33 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 844e5d09..27055763 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -451,47 +451,59 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload, printDebugMessage("Received " + phaseNameToString(phase) + " on bank " + to_string(bank.ID()) + " from DRAM"); - if (phase == END_RD || phase == END_WR) { - if(responseQueue.empty()) { + if (phase == END_RD || phase == END_WR) + { + if(responseQueue.empty()) sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); - } + responseQueue.push(&payload); - } else if (phase == END_RDA || phase == END_WRA) { - if(responseQueue.empty()) { + } + else if (phase == END_RDA || phase == END_WRA) + { + if(responseQueue.empty()) sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); - } + responseQueue.push(&payload); scheduleNextFromScheduler(bank); - } else if (phase == END_REFA) { + } + else if (phase == END_REFA) + { printDebugMessage("Finished auto refresh on all banks "); bool sleepy = true; - for (Bank bank : controllerCore->getBanks()) { - if (numberOfPayloadsInSystem[bank] != 0) { + for (Bank bank : controllerCore->getBanks()) + { + if (numberOfPayloadsInSystem[bank] != 0) + { sleepy = false; scheduleNextFromScheduler(bank); } } - - if (sleepy == true) { + if (sleepy == true) controllerCore->powerDownManager->sleep(0, sc_time_stamp()); - } - } else if (phase == END_REFB) { + } + else if (phase == END_REFB) + { printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID())); - if (numberOfPayloadsInSystem[bank] == 0) { + if (numberOfPayloadsInSystem[bank] == 0) controllerCore->powerDownManager->sleep(bank, sc_time_stamp()); - } else { + else scheduleNextFromScheduler(bank); - } - scheduleNextFromScheduler(bank); - } else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) { + scheduleNextFromScheduler(bank); } - else if (phase == END_PRE_ALL) { + else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) + { + scheduleNextFromScheduler(bank); + } + else if (phase == END_PRE_ALL) + { // No need to trigger anything for a END_PRE_ALL. It is followed by a AUTO_REFRESH anyway (in our current // scheduler implementation) - } else { + } + else + { string str = string("DRAM PEQ in controller wrapper was triggered with unsupported phase ") + phaseNameToString(phase); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 97ec9e73..8df4f8b0 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -145,9 +145,9 @@ protected: //Scheduler* scheduler; IScheduler *scheduler; std::map numberOfPayloadsInSystem; - std::vector refreshCollisionRequets; + std::vector refreshCollisionRequets; tlm::tlm_generic_payload *backpressure = NULL; - std::queue responseQueue; + std::queue responseQueue; tlm_utils::peq_with_cb_and_phase frontendPEQ; tlm_utils::peq_with_cb_and_phase dramPEQ; diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 63069368..ba8d1ebe 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -169,7 +169,7 @@ bool ControllerCore::scheduleRequest(Command command, sc_time start = clkAlign(sc_time_stamp()); state->cleanUp(start); ScheduledCommand scheduledCommand = schedule(command, start, payload); - if (config.ControllerCoreRefDisable == true) { + if (config.ControllerCoreRefDisable) { state->change(scheduledCommand); controller.send(scheduledCommand, payload); return true; diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index c20e35f7..37b7f4ea 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -54,7 +54,8 @@ enum class EPowerDownMode {NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF}; enum class ECCControllerMode {Disabled, Hamming}; -struct Configuration { +struct Configuration +{ static std::string memspecUri; static std::string mcconfigUri; std::string pathToResources; diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.cpp b/DRAMSys/library/src/controller/scheduler/Fifo.cpp index 305e2798..71e098b6 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fifo.cpp @@ -57,7 +57,9 @@ std::pair Fifo::getNextRequest(Bank bank) return std::pair(command, payload); } else + { return std::pair(Command::NOP, NULL); + } } gp *Fifo::getPendingRequest(Bank /*bank*/) diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.h b/DRAMSys/library/src/controller/scheduler/Fifo.h index dfb5820c..14a9f34c 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.h +++ b/DRAMSys/library/src/controller/scheduler/Fifo.h @@ -52,8 +52,8 @@ public: virtual ~Fifo() {} void storeRequest(gp *payload) override; - std::pair getNextRequest( - Bank bank) override; + std::pair + getNextRequest(Bank bank) override; virtual gp *getPendingRequest(Bank bank) override; private: diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp index 09d53b47..2a9b6eff 100644 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp +++ b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp @@ -50,13 +50,18 @@ void IScheduler::printDebugMessage(std::string message) Command IScheduler::getNextCommand(gp &payload) { Bank bank = DramExtension::getBank(payload); - if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) { + if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) + { return Command::Activate; - } else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && + } + else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && controllerCore.getRowBufferStates().getRowInRowBuffer(bank) != - DramExtension::getRow(payload)) { + DramExtension::getRow(payload)) + { return Command::Precharge; - } else { + } + else + { return getReadWriteCommand(payload); } } @@ -68,13 +73,15 @@ Command IScheduler::getNextCommand(gp *payload) Command IScheduler::getReadWriteCommand(gp &payload) { - - if (payload.get_command() == tlm::TLM_READ_COMMAND) { + if (payload.get_command() == tlm::TLM_READ_COMMAND) + { if (Configuration::getInstance().OpenPagePolicy) return Command::Read; else return Command::ReadA; - } else { + } + else + { if (Configuration::getInstance().OpenPagePolicy) return Command::Write; else @@ -86,3 +93,4 @@ Command IScheduler::getReadWriteCommand(gp *payload) { return getReadWriteCommand(*payload); } + From e7704a74e6fa6bacb4f662953bef19572724aca6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 11 Jun 2019 23:11:39 +0200 Subject: [PATCH 06/30] Code refactoring. --- DRAMSys/library/library.pro | 2 + DRAMSys/library/src/simulation/Dram.cpp | 602 ++++++++++++++++++ DRAMSys/library/src/simulation/Dram.h | 524 +-------------- .../library/src/simulation/RecordableDram.cpp | 135 ++++ .../library/src/simulation/RecordableDram.h | 102 +-- 5 files changed, 772 insertions(+), 593 deletions(-) create mode 100644 DRAMSys/library/src/simulation/Dram.cpp create mode 100644 DRAMSys/library/src/simulation/RecordableDram.cpp diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index a1c1b07a..8063b653 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -144,6 +144,8 @@ SOURCES += \ src/common/AddressDecoder.cpp \ src/controller/scheduler/grp.cpp \ src/common/congenAddressDecoder.cpp \ + src/simulation/Dram.cpp \ + src/simulation/RecordableDram.cpp \ src/simulation/Arbiter.cpp HEADERS += \ diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp new file mode 100644 index 00000000..68b3acb0 --- /dev/null +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Robert Gernhardt + * Matthias Jung + * Peter Ehses + * Eder F. Zulian + * Felipe S. Prado + */ + +#include "Dram.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/DebugManager.h" +#include "../common/dramExtension.h" +#include "../controller/Controller.h" +#include "../controller/core/TimingCalculation.h" +#include "../controller/core/configuration/Configuration.h" +#include "../common/protocol.h" +#include "../common/Utils.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../error/errormodel.h" + +using namespace std; +using namespace tlm; +using namespace Data; + + +Dram::Dram(sc_module_name) : tSocket("socket") +{ + // Adjust number of bytes per burst dynamically to the selected ecc controller + bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC( + bytesPerBurst); + dramController = NULL; + + std::uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes(); + if (Configuration::getInstance().UseMalloc) + { + memory = (unsigned char *)malloc(memorySize); + if (!memory) + { + SC_REPORT_FATAL(this->name(), "Memory allocation failed"); + } + } + else + { + // allocate and model storage of one DRAM channel using memory map + memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + } + + tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); + tSocket.register_transport_dbg(this, &Dram::transport_dbg); + + if (powerAnalysis) + { + sc_time clk = Configuration::getInstance().memSpec.clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = + Configuration::getInstance().memSpec.BurstLength; + memArchSpec.dataRate = Configuration::getInstance().memSpec.DataRate; + memArchSpec.nbrOfRows = + Configuration::getInstance().memSpec.NumberOfRows; + memArchSpec.nbrOfBanks = + Configuration::getInstance().memSpec.NumberOfBanks; + memArchSpec.nbrOfColumns = + Configuration::getInstance().memSpec.NumberOfColumns; + memArchSpec.nbrOfRanks = + Configuration::getInstance().memSpec.NumberOfRanks; + memArchSpec.width = Configuration::getInstance().memSpec.bitWidth; + memArchSpec.nbrOfBankGroups = + Configuration::getInstance().memSpec.NumberOfBankGroups; + memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 + ? false : true); + memArchSpec.dll = Configuration::getInstance().memSpec.DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = Configuration::getInstance().memSpec.tAL / clk; + memTimingSpec.CCD = Configuration::getInstance().memSpec.tCCD_S / clk; + memTimingSpec.CCD_L = Configuration::getInstance().memSpec.tCCD_L / clk; + memTimingSpec.CCD_S = Configuration::getInstance().memSpec.tCCD_S / clk; + memTimingSpec.CKE = Configuration::getInstance().memSpec.tCKE / clk; + memTimingSpec.CKESR = Configuration::getInstance().memSpec.tCKESR / clk; + memTimingSpec.clkMhz = Configuration::getInstance().memSpec.clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec.clkMHz; + memTimingSpec.DQSCK = Configuration::getInstance().memSpec.tDQSCK / clk; + memTimingSpec.FAW = Configuration::getInstance().memSpec.tNAW / clk; + memTimingSpec.RAS = Configuration::getInstance().memSpec.tRAS / clk; + memTimingSpec.RC = Configuration::getInstance().memSpec.tRC / clk; + memTimingSpec.RCD = Configuration::getInstance().memSpec.tRCD / clk; + memTimingSpec.REFI = Configuration::getInstance().memSpec.tREFI / clk; + auto m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC2 / clk; + else + memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC / clk; + memTimingSpec.RL = Configuration::getInstance().memSpec.tRL / clk; + memTimingSpec.RP = Configuration::getInstance().memSpec.tRP / clk; + memTimingSpec.RRD = Configuration::getInstance().memSpec.tRRD_S / clk; + memTimingSpec.RRD_L = Configuration::getInstance().memSpec.tRRD_L / clk; + memTimingSpec.RRD_S = Configuration::getInstance().memSpec.tRRD_S / clk; + memTimingSpec.RTP = Configuration::getInstance().memSpec.tRTP / clk; + memTimingSpec.TAW = Configuration::getInstance().memSpec.tNAW / clk; + memTimingSpec.WL = Configuration::getInstance().memSpec.tWL / clk; + memTimingSpec.WR = Configuration::getInstance().memSpec.tWR / clk; + memTimingSpec.WTR = Configuration::getInstance().memSpec.tWTR_S / clk; + memTimingSpec.WTR_L = Configuration::getInstance().memSpec.tWTR_L / clk; + memTimingSpec.WTR_S = Configuration::getInstance().memSpec.tWTR_S / clk; + memTimingSpec.XP = Configuration::getInstance().memSpec.tXP / clk; + memTimingSpec.XPDLL = Configuration::getInstance().memSpec.tXPDLL / clk; + memTimingSpec.XS = Configuration::getInstance().memSpec.tXSR / clk; + memTimingSpec.XSDLL = Configuration::getInstance().memSpec.tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = Configuration::getInstance().memSpec.iDD0; + memPowerSpec.idd02 = Configuration::getInstance().memSpec.iDD02; + memPowerSpec.idd2p0 = Configuration::getInstance().memSpec.iDD2P0; + memPowerSpec.idd2p02 = Configuration::getInstance().memSpec.iDD2P02; + memPowerSpec.idd2p1 = Configuration::getInstance().memSpec.iDD2P1; + memPowerSpec.idd2p12 = Configuration::getInstance().memSpec.iDD2P12; + memPowerSpec.idd2n = Configuration::getInstance().memSpec.iDD2N; + memPowerSpec.idd2n2 = Configuration::getInstance().memSpec.iDD2N2; + memPowerSpec.idd3p0 = Configuration::getInstance().memSpec.iDD3P0; + memPowerSpec.idd3p02 = Configuration::getInstance().memSpec.iDD3P02; + memPowerSpec.idd3p1 = Configuration::getInstance().memSpec.iDD3P1; + memPowerSpec.idd3p12 = Configuration::getInstance().memSpec.iDD3P12; + memPowerSpec.idd3n = Configuration::getInstance().memSpec.iDD3N; + memPowerSpec.idd3n2 = Configuration::getInstance().memSpec.iDD3N2; + memPowerSpec.idd4r = Configuration::getInstance().memSpec.iDD4R; + memPowerSpec.idd4r2 = Configuration::getInstance().memSpec.iDD4R2; + memPowerSpec.idd4w = Configuration::getInstance().memSpec.iDD4W; + memPowerSpec.idd4w2 = Configuration::getInstance().memSpec.iDD4W2; + memPowerSpec.idd5 = Configuration::getInstance().memSpec.iDD5; + memPowerSpec.idd52 = Configuration::getInstance().memSpec.iDD52; + memPowerSpec.idd6 = Configuration::getInstance().memSpec.iDD6; + memPowerSpec.idd62 = Configuration::getInstance().memSpec.iDD62; + memPowerSpec.vdd = Configuration::getInstance().memSpec.vDD; + memPowerSpec.vdd2 = Configuration::getInstance().memSpec.vDD2; + + MemorySpecification memSpec; + memSpec.id = Configuration::getInstance().memSpec.MemoryId; + memSpec.memoryType = Configuration::getInstance().memSpec.MemoryType; + memSpec.memTimingSpec = memTimingSpec; + memSpec.memPowerSpec = memPowerSpec; + memSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(memSpec, 0); + } + + // Bandwidth Calculation: + numberOfTransactionsServed = 0; + firstAccess = SC_ZERO_TIME; + lastAccess = SC_ZERO_TIME; + + // For each bank in a channel a error Model is created: + if (StoreMode == StorageMode::ErrorModel) + { + for (unsigned i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks; + i++) + { + errorModel *em; + std::string errorModelStr = "errorModel_bank" + std::to_string(i); + if (powerAnalysis) + em = new errorModel(errorModelStr.c_str(), DRAMPower); + else + em = new errorModel(errorModelStr.c_str()); + ememory.push_back(em); + } + } +} + +Dram::~Dram() +{ + if (powerAnalysis) + { + if (!Configuration::getInstance().DatabaseRecording) + DRAMPower->calcEnergy(); + + // Print the final total energy and the average power for + // the simulation: + cout << name() << string(" Total Energy: ") + << fixed << std::setprecision( 2 ) + << DRAMPower->getEnergy().total_energy + * Configuration::getInstance().NumberOfDevicesOnDIMM + << string(" pJ") + << endl; + + cout << name() << string(" Average Power: ") + << fixed << std::setprecision( 2 ) + << DRAMPower->getPower().average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM + << string(" mW") << endl; + } + + // Bandwidth: + + sc_time activeTime = numberOfTransactionsServed + * Configuration::getInstance().memSpec.BurstLength + / Configuration::getInstance().memSpec.DataRate + * Configuration::getInstance().memSpec.clk; + + sc_time idleTime = dramController->getIdleTime(); + sc_time endTime = dramController->getEndTime(); + sc_time startTime = dramController->getStartTime(); + + double bandwidth = (activeTime / (endTime - startTime) * 100); + double bandwidth_IDLE = ((activeTime) / (endTime - startTime - idleTime) * 100); + + double maxBandwidth = ( + // clk in Mhz e.g. 800 [MHz]: + (1000000 / Configuration::getInstance().memSpec.clk.to_double()) + // DataRate e.g. 2 + * Configuration::getInstance().memSpec.DataRate + // BusWidth e.g. 8 or 64 + * Configuration::getInstance().memSpec.bitWidth + // Number of devices on a DIMM e.g. 8 + * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); + + cout << name() << string(" Total Time: ") + << (endTime - startTime).to_string() + << endl; + cout << name() << string(" AVG BW: ") + << std::fixed << std::setprecision(2) + << ((bandwidth / 100)*maxBandwidth) + << " Gibit/s (" << bandwidth << " %)" + << endl; + cout << name() << string(" AVG BW/IDLE: ") + << std::fixed << std::setprecision(2) + << ((bandwidth_IDLE / 100)*maxBandwidth) + << " Gibit/s (" << (bandwidth_IDLE) << " %)" + << endl; + cout << name() << string(" MAX BW: ") + << std::fixed << std::setprecision(2) + << maxBandwidth << " Gibit/s" + << endl; + // Clean up: + for (auto e : ememory) + delete e; + + if (Configuration::getInstance().UseMalloc) + free(memory); +} + +tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay) +{ + if (numberOfTransactionsServed == 0) + firstAccess = sc_time_stamp(); + else + lastAccess = sc_time_stamp(); + + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + + // This is only needed for power simulation: + unsigned long long cycle = 0; + if (powerAnalysis) + { + cycle = sc_time_stamp().value() / + Configuration::getInstance().memSpec.clk.value(); + } + + if (phase == BEGIN_PREB) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PREB, bank, cycle); + + sendToController(payload, END_PREB, delay + getExecutionTime(Command::PreB, + payload)); + } + else if (phase == BEGIN_PRE) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PRE, bank, cycle); + + sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, + payload)); + } + else if (phase == BEGIN_PRE_ALL) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PREA, bank, cycle); + + sendToController(payload, END_PRE_ALL, + delay + getExecutionTime(Command::PrechargeAll, payload)); + } + else if (phase == BEGIN_ACTB) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); + + sendToController(payload, END_ACTB, delay + getExecutionTime(Command::ActB, + payload)); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + if (StoreMode == StorageMode::ErrorModel) + ememory[bank]->activate(row); + } + else if (phase == BEGIN_ACT) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + + sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, + payload)); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + + if (StoreMode == StorageMode::ErrorModel) + ememory[bank]->activate(row); + } + else if (phase == BEGIN_WR) + { +#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5) + assert(payload.get_data_length() == bytesPerBurst); +#endif + + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::WR, bank, cycle); + + numberOfTransactionsServed++; + + // save data: + if (StoreMode == StorageMode::NoStorage) // Don't store data + {} + else if (StoreMode == StorageMode::Store) // Use Storage + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); + } + else // if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model + { + ememory[bank]->store(payload); + } + sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, + payload)); + } + else if (phase == BEGIN_RD) + { +#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5) + assert(payload.get_data_length() == bytesPerBurst); +#endif + + numberOfTransactionsServed++; + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::RD, bank, cycle); + + // load data: + if (StoreMode == StorageMode::Store) // use StorageMode + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); + } + else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel + { + ememory[bank]->load(payload); + } + sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, + payload)); + } + else if (phase == BEGIN_WRA) + { + numberOfTransactionsServed++; + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::WRA, bank, cycle); + + // save data: + if (StoreMode == StorageMode::NoStorage) // Don't store data + {} + else if (StoreMode == StorageMode::Store) // Use Storage + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); + } + else // if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model + { + ememory[bank]->store(payload); + } + sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, + payload)); + } + else if (phase == BEGIN_RDA) + { + numberOfTransactionsServed++; + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::RDA, bank, cycle); + + // Load data: + if (StoreMode == StorageMode::Store) // use StorageMode + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); + } + else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel + { + ememory[bank]->load(payload); + } + sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, + payload)); + } + else if (phase == BEGIN_REFA) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::REF, bank, cycle); + + sendToController(payload, END_REFA, + delay + getExecutionTime(Command::AutoRefresh, payload)); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + + if (StoreMode == StorageMode::ErrorModel) + ememory[bank]->refresh(row); + } + else if (phase == BEGIN_REFB) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::REFB, bank, cycle); + + sendToController(payload, END_REFB, + delay + getExecutionTime(Command::AutoRefresh, payload)); + } + // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length + else if (phase == BEGIN_PDNA) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + } + else if (phase == END_PDNA) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + } + else if (phase == BEGIN_PDNAB) + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == END_PDNAB) + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == BEGIN_PDNP) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + } + else if (phase == END_PDNP) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + } + else if (phase == BEGIN_PDNPB) + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == END_PDNPB) + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == BEGIN_SREF) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + } + else if (phase == END_SREF) + { + if (powerAnalysis) + DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + } + else if (phase == BEGIN_SREFB) + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == END_SREFB) + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else + { + if (powerAnalysis) + SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); + } + + return tlm::TLM_ACCEPTED; +} + +unsigned int Dram::transport_dbg(tlm_generic_payload &trans) +{ + printDebugMessage("transport_dgb"); + + // TODO: This part is not tested yet, neither with traceplayers nor with GEM5 coupling + if (StoreMode == StorageMode::NoStorage) + { + SC_REPORT_FATAL("DRAM", + "Debug Transport is used in combination with NoStorage"); + } + else + { + tlm_command cmd = trans.get_command(); + //sc_dt::uint64 adr = trans.get_address(); // TODO: - offset; + unsigned char *ptr = trans.get_data_ptr(); + unsigned int len = trans.get_data_length(); + //unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); + + //cout << "cmd " << (cmd ? "write" : "read") << " adr " << hex << adr << " len " << len << endl; + + if (cmd == TLM_READ_COMMAND) + { + if (StoreMode == StorageMode::Store) + { // Use Storage + unsigned char *phyAddr = memory + trans.get_address(); + memcpy(ptr, phyAddr, trans.get_data_length()); + } + else + { + //ememory[bank]->load(trans); + SC_REPORT_FATAL("DRAM", "Debug transport not supported with error model yet."); + } + } + else if (cmd == TLM_WRITE_COMMAND) + { + if (StoreMode == StorageMode::Store) + { // Use Storage + unsigned char *phyAddr = memory + trans.get_address(); + memcpy(phyAddr, ptr, trans.get_data_length()); + } + else + { + //ememory[bank]->store(trans); + SC_REPORT_FATAL("DRAM", "Debug transport not supported with error model yet."); + } + } + return len; + } + return 0; +} + +void Dram::sendToController(tlm_generic_payload &payload, const tlm_phase &phase, + const sc_time &delay) +{ + tlm_phase TPhase = phase; + sc_time TDelay = delay; + tSocket->nb_transport_bw(payload, TPhase, TDelay); +} + +void Dram::printDebugMessage(string message) +{ + DebugManager::getInstance().printDebugMessage(name(), message); +} + +void Dram::setDramController(Controller *contr) +{ + dramController = contr; +} diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 7c383498..20817be9 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -40,39 +40,24 @@ #ifndef DRAM_H_ #define DRAM_H_ -#include #include #include -#include #include -#include -#include -#include -#include -#include -#include "../common/DebugManager.h" -#include "../common/dramExtension.h" #include "../controller/Controller.h" -#include "../controller/core/TimingCalculation.h" #include "../controller/core/configuration/Configuration.h" -#include "../common/protocol.h" -#include "../common/Utils.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../error/errormodel.h" using namespace std; using namespace tlm; using namespace Data; -struct Dram : sc_module { +class Dram : public sc_module +{ +private: unsigned int bytesPerBurst = Configuration::getInstance().getBytesPerBurst(); - // TLM Related: - tlm_utils::simple_target_socket tSocket; - // Power Model related bool powerAnalysis = Configuration::getInstance().PowerAnalysis; - libDRAMPower *DRAMPower; // Bandwidth realted: unsigned long long int numberOfTransactionsServed; @@ -88,499 +73,28 @@ struct Dram : sc_module { Controller *dramController; - SC_CTOR(Dram) : tSocket("socket") - { - // Adjust number of bytes per burst dynamically to the selected ecc controller - bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC( - bytesPerBurst); - dramController = NULL; +protected: + libDRAMPower *DRAMPower; - std::uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes(); - if (Configuration::getInstance().UseMalloc) { - memory = (unsigned char *)malloc(memorySize); - if (!memory) { - SC_REPORT_FATAL(this->name(), "Memory allocation failed"); - } - } else { - // allocate and model storage of one DRAM channel using memory map - memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); - } + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay); - tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - tSocket.register_transport_dbg(this, &Dram::transport_dbg); - - if (powerAnalysis == true) { - sc_time clk = Configuration::getInstance().memSpec.clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = - Configuration::getInstance().memSpec.BurstLength; - memArchSpec.dataRate = Configuration::getInstance().memSpec.DataRate; - memArchSpec.nbrOfRows = - Configuration::getInstance().memSpec.NumberOfRows; - memArchSpec.nbrOfBanks = - Configuration::getInstance().memSpec.NumberOfBanks; - memArchSpec.nbrOfColumns = - Configuration::getInstance().memSpec.NumberOfColumns; - memArchSpec.nbrOfRanks = - Configuration::getInstance().memSpec.NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec.bitWidth; - memArchSpec.nbrOfBankGroups = - Configuration::getInstance().memSpec.NumberOfBankGroups; - memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 - ? false : true); - memArchSpec.dll = Configuration::getInstance().memSpec.DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = Configuration::getInstance().memSpec.tAL / clk; - memTimingSpec.CCD = Configuration::getInstance().memSpec.tCCD_S / clk; - memTimingSpec.CCD_L = Configuration::getInstance().memSpec.tCCD_L / clk; - memTimingSpec.CCD_S = Configuration::getInstance().memSpec.tCCD_S / clk; - memTimingSpec.CKE = Configuration::getInstance().memSpec.tCKE / clk; - memTimingSpec.CKESR = Configuration::getInstance().memSpec.tCKESR / clk; - memTimingSpec.clkMhz = Configuration::getInstance().memSpec.clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec.clkMHz; - memTimingSpec.DQSCK = Configuration::getInstance().memSpec.tDQSCK / clk; - memTimingSpec.FAW = Configuration::getInstance().memSpec.tNAW / clk; - memTimingSpec.RAS = Configuration::getInstance().memSpec.tRAS / clk; - memTimingSpec.RC = Configuration::getInstance().memSpec.tRC / clk; - memTimingSpec.RCD = Configuration::getInstance().memSpec.tRCD / clk; - memTimingSpec.REFI = Configuration::getInstance().memSpec.tREFI / clk; - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC2 / clk; - else - memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC / clk; - memTimingSpec.RL = Configuration::getInstance().memSpec.tRL / clk; - memTimingSpec.RP = Configuration::getInstance().memSpec.tRP / clk; - memTimingSpec.RRD = Configuration::getInstance().memSpec.tRRD_S / clk; - memTimingSpec.RRD_L = Configuration::getInstance().memSpec.tRRD_L / clk; - memTimingSpec.RRD_S = Configuration::getInstance().memSpec.tRRD_S / clk; - memTimingSpec.RTP = Configuration::getInstance().memSpec.tRTP / clk; - memTimingSpec.TAW = Configuration::getInstance().memSpec.tNAW / clk; - memTimingSpec.WL = Configuration::getInstance().memSpec.tWL / clk; - memTimingSpec.WR = Configuration::getInstance().memSpec.tWR / clk; - memTimingSpec.WTR = Configuration::getInstance().memSpec.tWTR_S / clk; - memTimingSpec.WTR_L = Configuration::getInstance().memSpec.tWTR_L / clk; - memTimingSpec.WTR_S = Configuration::getInstance().memSpec.tWTR_S / clk; - memTimingSpec.XP = Configuration::getInstance().memSpec.tXP / clk; - memTimingSpec.XPDLL = Configuration::getInstance().memSpec.tXPDLL / clk; - memTimingSpec.XS = Configuration::getInstance().memSpec.tXSR / clk; - memTimingSpec.XSDLL = Configuration::getInstance().memSpec.tXSRDLL / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = Configuration::getInstance().memSpec.iDD0; - memPowerSpec.idd02 = Configuration::getInstance().memSpec.iDD02; - memPowerSpec.idd2p0 = Configuration::getInstance().memSpec.iDD2P0; - memPowerSpec.idd2p02 = Configuration::getInstance().memSpec.iDD2P02; - memPowerSpec.idd2p1 = Configuration::getInstance().memSpec.iDD2P1; - memPowerSpec.idd2p12 = Configuration::getInstance().memSpec.iDD2P12; - memPowerSpec.idd2n = Configuration::getInstance().memSpec.iDD2N; - memPowerSpec.idd2n2 = Configuration::getInstance().memSpec.iDD2N2; - memPowerSpec.idd3p0 = Configuration::getInstance().memSpec.iDD3P0; - memPowerSpec.idd3p02 = Configuration::getInstance().memSpec.iDD3P02; - memPowerSpec.idd3p1 = Configuration::getInstance().memSpec.iDD3P1; - memPowerSpec.idd3p12 = Configuration::getInstance().memSpec.iDD3P12; - memPowerSpec.idd3n = Configuration::getInstance().memSpec.iDD3N; - memPowerSpec.idd3n2 = Configuration::getInstance().memSpec.iDD3N2; - memPowerSpec.idd4r = Configuration::getInstance().memSpec.iDD4R; - memPowerSpec.idd4r2 = Configuration::getInstance().memSpec.iDD4R2; - memPowerSpec.idd4w = Configuration::getInstance().memSpec.iDD4W; - memPowerSpec.idd4w2 = Configuration::getInstance().memSpec.iDD4W2; - memPowerSpec.idd5 = Configuration::getInstance().memSpec.iDD5; - memPowerSpec.idd52 = Configuration::getInstance().memSpec.iDD52; - memPowerSpec.idd6 = Configuration::getInstance().memSpec.iDD6; - memPowerSpec.idd62 = Configuration::getInstance().memSpec.iDD62; - memPowerSpec.vdd = Configuration::getInstance().memSpec.vDD; - memPowerSpec.vdd2 = Configuration::getInstance().memSpec.vDD2; - - MemorySpecification memSpec; - memSpec.id = Configuration::getInstance().memSpec.MemoryId; - memSpec.memoryType = Configuration::getInstance().memSpec.MemoryType; - memSpec.memTimingSpec = memTimingSpec; - memSpec.memPowerSpec = memPowerSpec; - memSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower( memSpec, 0 ); - } - - // Bandwidth Calculation: - numberOfTransactionsServed = 0; - firstAccess = SC_ZERO_TIME; - lastAccess = SC_ZERO_TIME; - - // For each bank in a channel a error Model is created: - if (StoreMode == StorageMode::ErrorModel) { - for (unsigned i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks; - i++) { - errorModel *em; - std::string errorModelStr = "errorModel_bank" + std::to_string(i); - if (powerAnalysis == true) { - em = new errorModel(errorModelStr.c_str(), DRAMPower); - } else { - em = new errorModel(errorModelStr.c_str()); - } - ememory.push_back(em); - } - } - } - - virtual void end_of_simulation() - { - } - - ~Dram() - { - if (powerAnalysis == true) { - if (!Configuration::getInstance().DatabaseRecording) - DRAMPower->calcEnergy(); - - // Print the final total energy and the average power for - // the simulation: - cout << name() << string(" Total Energy: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" pJ") - << endl; - - cout << name() << string(" Average Power: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getPower().average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" mW") << endl; - } - - // Bandwidth: - - sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec.BurstLength - / Configuration::getInstance().memSpec.DataRate - * Configuration::getInstance().memSpec.clk; - - sc_time idleTime = dramController->getIdleTime(); - sc_time endTime = dramController->getEndTime(); - sc_time startTime = dramController->getStartTime(); - - double bandwidth = (activeTime / (endTime - startTime) * 100); - double bandwidth_IDLE = ((activeTime) / (endTime - startTime - idleTime) * 100); - - double maxBandwidth = ( - // clk in Mhz e.g. 800 [MHz]: - (1000000 / Configuration::getInstance().memSpec.clk.to_double()) - // DataRate e.g. 2 - * Configuration::getInstance().memSpec.DataRate - // BusWidth e.g. 8 or 64 - * Configuration::getInstance().memSpec.bitWidth - // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); - - cout << name() << string(" Total Time: ") - << (endTime - startTime).to_string() - << endl; - cout << name() << string(" AVG BW: ") - << std::fixed << std::setprecision(2) - << ((bandwidth / 100)*maxBandwidth) - << " Gibit/s (" << bandwidth << " %)" - << endl; - cout << name() << string(" AVG BW/IDLE: ") - << std::fixed << std::setprecision(2) - << ((bandwidth_IDLE / 100)*maxBandwidth) - << " Gibit/s (" << (bandwidth_IDLE) << " %)" - << endl; - cout << name() << string(" MAX BW: ") - << std::fixed << std::setprecision(2) - << maxBandwidth << " Gibit/s" - << endl; - // Clean up: - for (auto e : ememory) { - delete e; - } - - if (Configuration::getInstance().UseMalloc) { - free(memory); - } - } - - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) - { - if (numberOfTransactionsServed == 0) { - firstAccess = sc_time_stamp(); - } else { - lastAccess = sc_time_stamp(); - } - - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); - - // This is only needed for power simulation: - unsigned long long cycle = 0; - if (powerAnalysis == true) { - cycle = sc_time_stamp().value() / - Configuration::getInstance().memSpec.clk.value(); - } - if (phase == BEGIN_PREB) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - } - sendToController(payload, END_PREB, delay + getExecutionTime(Command::PreB, - payload)); - } else if (phase == BEGIN_PRE) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - } - sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, - payload)); - } else if (phase == BEGIN_PRE_ALL) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - } - sendToController(payload, END_PRE_ALL, - delay + getExecutionTime(Command::PrechargeAll, payload)); - } else if (phase == BEGIN_ACTB) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - } - sendToController(payload, END_ACTB, delay + getExecutionTime(Command::ActB, - payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - if (StoreMode == StorageMode::ErrorModel) { - ememory[bank]->activate(row); - } - } else if (phase == BEGIN_ACT) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - } - sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, - payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - - if (StoreMode == StorageMode::ErrorModel) { - ememory[bank]->activate(row); - } - } else if (phase == BEGIN_WR) { -#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5) - assert(payload.get_data_length() == bytesPerBurst); -#endif - - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); - } - numberOfTransactionsServed++; - - //save data: - if (StoreMode == StorageMode::NoStorage) { - // Don't store data - } else if (StoreMode == StorageMode::Store) { // Use Storage - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } else { // == 2 Use Storage with Error Model - ememory[bank]->store(payload); - } - sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, - payload)); - } else if (phase == BEGIN_RD) { -#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5) - assert(payload.get_data_length() == bytesPerBurst); -#endif - - numberOfTransactionsServed++; - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); - } - - // Load data: - if (StoreMode == StorageMode::Store) { //use StorageMode - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } else if (StoreMode == - StorageMode::ErrorModel) { // use StorageMode with errormodel - ememory[bank]->load(payload); - } - - sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, - payload)); - } else if (phase == BEGIN_WRA) { - numberOfTransactionsServed++; - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); - } - - //save data: - if (StoreMode == StorageMode::NoStorage) { - // Don't store data - } else if (StoreMode == StorageMode::Store) { // Use Storage - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } else { // == 2 Use Storage with Error Model - ememory[bank]->store(payload); - } - sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, - payload)); - } else if (phase == BEGIN_RDA) { - numberOfTransactionsServed++; - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); - } - - // Load data: - if (StoreMode == StorageMode::Store) { //use StorageMode - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } else if (StoreMode == - StorageMode::ErrorModel) { // use StorageMode with errormodel - ememory[bank]->load(payload); - } - - sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, - payload)); - } else if (phase == BEGIN_REFA) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - } - sendToController(payload, END_REFA, - delay + getExecutionTime(Command::AutoRefresh, payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - - if (StoreMode == StorageMode::ErrorModel) { - ememory[bank]->refresh(row); - } - } - - else if (phase == BEGIN_REFB) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::REFB, bank, cycle); - } - sendToController(payload, END_REFB, - delay + getExecutionTime(Command::AutoRefresh, payload)); - } - - //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length - else if (phase == BEGIN_PDNA) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); - } - } else if (phase == END_PDNA) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); - } - } else if (phase == BEGIN_PDNAB) { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - } else if (phase == END_PDNAB) { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - } else if (phase == BEGIN_PDNP) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); - } - } else if (phase == END_PDNP) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); - } - } else if (phase == BEGIN_PDNPB) { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - } else if (phase == END_PDNPB) { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - } else if (phase == BEGIN_SREF) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); - } - } else if (phase == END_SREF) { - if (powerAnalysis == true) { - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); - } - } else if (phase == BEGIN_SREFB) { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - } else if (phase == END_SREFB) { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - } else { - if (powerAnalysis == true) { - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); - } - } - - return tlm::TLM_ACCEPTED; - } - - virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans) - { - printDebugMessage("transport_dgb"); - - // TODO: This part is not tested yet, neither with traceplayers neither with GEM5 coupling - if (StoreMode == StorageMode::NoStorage) { - SC_REPORT_FATAL("DRAM", - "Debug Transport is used in combination with NoStorage"); - } else { - tlm::tlm_command cmd = trans.get_command(); - //sc_dt::uint64 adr = trans.get_address(); // TODO: - offset; - unsigned char *ptr = trans.get_data_ptr(); - unsigned int len = trans.get_data_length(); - //unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); - - //cout << "cmd " << (cmd ? "write" : "read") << " adr " << hex << adr << " len " << len << endl; - - if ( cmd == tlm::TLM_READ_COMMAND ) { - if (StoreMode == StorageMode::Store) { // Use Storage - unsigned char *phyAddr = memory + trans.get_address(); - memcpy(ptr, phyAddr, trans.get_data_length()); - } else { - //ememory[bank]->load(trans); - SC_REPORT_FATAL("DRAM", "Debug transport not supported with error model yet."); - } - } else if ( cmd == tlm::TLM_WRITE_COMMAND ) { - - if (StoreMode == StorageMode::Store) { // Use Storage - unsigned char *phyAddr = memory + trans.get_address(); - memcpy(phyAddr, ptr, trans.get_data_length()); - } else { - //ememory[bank]->store(trans); - SC_REPORT_FATAL("DRAM", "Debug transport not supported with error model yet."); - } - - } - return len; - } - return 0; - } + virtual unsigned int transport_dbg(tlm_generic_payload &trans); void sendToController(tlm_generic_payload &payload, const tlm_phase &phase, - const sc_time &delay) - { - tlm_phase TPhase = phase; - sc_time TDelay = delay; - tSocket->nb_transport_bw(payload, TPhase, TDelay); - } + const sc_time &delay); - void printDebugMessage(string message) - { - DebugManager::getInstance().printDebugMessage(name(), message); - } + void printDebugMessage(string message); - void setDramController(Controller *contr) - { - dramController = contr; - } +public: + tlm_utils::simple_target_socket tSocket; + + Dram(sc_module_name); + SC_HAS_PROCESS(Dram); + + ~Dram(); + + void setDramController(Controller *contr); }; #endif /* DRAM_H_ */ diff --git a/DRAMSys/library/src/simulation/RecordableDram.cpp b/DRAMSys/library/src/simulation/RecordableDram.cpp new file mode 100644 index 00000000..7ba789ef --- /dev/null +++ b/DRAMSys/library/src/simulation/RecordableDram.cpp @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2018, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Felipe S. Prado + * Matthias Jung + */ + +#include "RecordableDram.h" + +using namespace tlm; + +RecordableDram::RecordableDram(sc_module_name name, TlmRecorder *tlmRecorder) + : Dram(name), tlmRecorder(tlmRecorder) +{ + // Create a thread that is triggered every $powerWindowSize + // to generate a Power over Time plot in the Trace analyzer: + if (Configuration::getInstance().PowerAnalysis + && Configuration::getInstance().EnableWindowing) + SC_THREAD(powerWindow); +} + +RecordableDram::~RecordableDram() +{ + if (Configuration::getInstance().PowerAnalysis) + { + // Obtain the residual energy which was not covered by + // previous windows + DRAMPower->calcEnergy(); + recordPower(); + } + tlmRecorder->closeConnection(); +} + + +tlm_sync_enum RecordableDram::nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay) +{ + // Recording time used by the traceAnalyzer + sc_time recTime = sc_time_stamp() + delay; + + // These are terminating phases recorded by the DRAM. The execution + // time of the related command must be taken into consideration. + if (phase == END_PDNA || phase == END_PDNAB) { + recTime += getExecutionTime(Command::PDNAX, payload); + } else if (phase == END_PDNP || phase == END_PDNPB) { + recTime += getExecutionTime(Command::PDNPX, payload); + } else if (phase == END_SREF || phase == END_SREFB) { + recTime += getExecutionTime(Command::SREFX, payload); + } + + unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); + unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); + unsigned int bg = DramExtension::getExtension(payload).getBankGroup().ID(); + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); + + printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( + bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + + to_string(col) + " at " + recTime.to_string()); + + tlmRecorder->recordPhase(payload, phase, recTime); + + return Dram::nb_transport_fw(payload, phase, delay); +} + +// This Thread is only triggered when Power Simulation is enabled. +// It estimates the current average power which will be stored in the trace database for visualization purposes. +void RecordableDram::powerWindow() +{ + unsigned long long clk_cycles = 0; + + do { + // At the very beginning (zero clock cycles) the energy is 0, so we wait first + wait(powerWindowSize); + + clk_cycles = sc_time_stamp().value() / + Configuration::getInstance().memSpec.clk.value(); + + DRAMPower->calcWindowEnergy(clk_cycles); + + // During operation the energy should never be zero since the device is always consuming + assert(!is_equal(DRAMPower->getEnergy().window_energy, 0.0)); + + // Store the time (in seconds) and the current average power (in mW) into the database + recordPower(); + + // Here considering that DRAMPower provides the energy in pJ and the power in mW + printDebugMessage(string("\tWindow Energy: \t") + to_string( + DRAMPower->getEnergy().window_energy * + Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); + printDebugMessage(string("\tWindow Average Power: \t") + to_string( + DRAMPower->getPower().window_average_power * + Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); + + } while (true); +} + +void RecordableDram::recordPower() +{ + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + DRAMPower->getPower().window_average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM); +} + diff --git a/DRAMSys/library/src/simulation/RecordableDram.h b/DRAMSys/library/src/simulation/RecordableDram.h index 00a2d073..669eb3cc 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.h +++ b/DRAMSys/library/src/simulation/RecordableDram.h @@ -40,66 +40,25 @@ #include "Dram.h" #include "../common/TlmRecorder.h" -struct RecordableDram : public Dram { +using namespace tlm; + +class RecordableDram : public Dram +{ +public: + RecordableDram(sc_module_name, TlmRecorder *tlmRecorder); SC_HAS_PROCESS(RecordableDram); - RecordableDram(sc_module_name name, TlmRecorder *tlmRecorder): - Dram(name), tlmRecorder(tlmRecorder) - { - // Create a thread that is triggered every $powerWindowSize - // to generate a Power over Time plot in the Trace analyzer: - if (Configuration::getInstance().PowerAnalysis - && Configuration::getInstance().EnableWindowing) - SC_THREAD(powerWindow); - } - ~RecordableDram() - { - if (Configuration::getInstance().PowerAnalysis) { - // Obtain the residual energy which was not covered by - // previous windows - DRAMPower->calcEnergy(); - recordPower(); - } - tlmRecorder->closeConnection(); - } + ~RecordableDram(); +protected: + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay); + +private: TlmRecorder *tlmRecorder; sc_time powerWindowSize = Configuration::getInstance().memSpec.clk * Configuration::getInstance().WindowSize; - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) - { - // Recording time used by the traceAnalyzer - sc_time recTime = sc_time_stamp() + delay; - - // These are terminating phases recorded by the DRAM. The execution - // time of the related command must be taken into consideration. - if (phase == END_PDNA || phase == END_PDNAB) { - recTime += getExecutionTime(Command::PDNAX, payload); - } else if (phase == END_PDNP || phase == END_PDNPB) { - recTime += getExecutionTime(Command::PDNPX, payload); - } else if (phase == END_SREF || phase == END_SREFB) { - recTime += getExecutionTime(Command::SREFX, payload); - } - - unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); - unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); - unsigned int bg = DramExtension::getExtension(payload).getBankGroup().ID(); - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); - - printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + - to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( - bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " at " + recTime.to_string()); - - tlmRecorder->recordPhase(payload, phase, recTime); - - return Dram::nb_transport_fw(payload, phase, delay); - } - // When working with floats, we have to decide ourselves what is an // acceptable definition for "equal". Here the number is compared with a // suitable error margin (0.00001). @@ -110,42 +69,9 @@ struct RecordableDram : public Dram { // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for visualization purposes. - void powerWindow() - { - unsigned long long clk_cycles = 0; + void powerWindow(); - do { - // At the very beginning (zero clock cycles) the energy is 0, so we wait first - wait(powerWindowSize); - - clk_cycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec.clk.value(); - - DRAMPower->calcWindowEnergy(clk_cycles); - - // During operation the energy should never be zero since the device is always consuming - assert(!is_equal(DRAMPower->getEnergy().window_energy, 0.0)); - - // Store the time (in seconds) and the current average power (in mW) into the database - recordPower(); - - // Here considering that DRAMPower provides the energy in pJ and the power in mW - printDebugMessage(string("\tWindow Energy: \t") + to_string( - DRAMPower->getEnergy().window_energy * - Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); - printDebugMessage(string("\tWindow Average Power: \t") + to_string( - DRAMPower->getPower().window_average_power * - Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); - - } while (true); - } - - void recordPower() - { - tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM); - } + void recordPower(); }; #endif /* RECORDABLEDRAM_H_ */ From 62c5ec720ff677e6feb80292da8af4999430006b Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 11 Jun 2019 23:14:07 +0200 Subject: [PATCH 07/30] Code refactoring. --- DRAMSys/library/src/controller/scheduler/Fifo.cpp | 2 +- DRAMSys/library/src/controller/scheduler/FifoStrict.cpp | 6 +++--- DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp | 2 +- .../library/src/controller/scheduler/Fr_Fcfs_grouper.cpp | 4 ++-- .../src/controller/scheduler/Fr_Fcfs_read_priority.cpp | 4 ++-- DRAMSys/library/src/controller/scheduler/SMS.cpp | 2 +- DRAMSys/library/src/controller/scheduler/grp.cpp | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.cpp b/DRAMSys/library/src/controller/scheduler/Fifo.cpp index 71e098b6..cc2ddb11 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fifo.cpp @@ -47,7 +47,7 @@ std::pair Fifo::getNextRequest(Bank bank) if (!buffer[bank].empty()) { gp *payload = buffer[bank].front(); - Command command = IScheduler::getNextCommand(*payload); + Command command = IScheduler::getNextCommand(payload); if (command == Command::Read || command == Command::ReadA || command == Command::Write || command == Command::WriteA) { diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp index 00701ce0..4b890433 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp @@ -75,7 +75,7 @@ std::pair FifoStrict::getNextRequest( // case of an already open row (due to a previous request) the // command itself could be directly issued. // - Command command = IScheduler::getNextCommand(*payload); + Command command = IScheduler::getNextCommand(payload); if (commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { buffer.pop_front(); @@ -84,7 +84,7 @@ std::pair FifoStrict::getNextRequest( if (!buffer.empty()) { tlm::tlm_generic_payload *p = buffer.front().second; - Command cmd = IScheduler::getNextCommand(*p); + Command cmd = IScheduler::getNextCommand(p); if (commandIsIn(cmd, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { Bank b = DramExtension::getBank(p); controller.blockedRequests.push(b); @@ -110,7 +110,7 @@ std::pair FifoStrict::getNextRequest( // Reads and writes will not be issued since this // scheduler executes all read and writes in a strict // order. - Command command = getNextCommand(*payload); + Command command = getNextCommand(payload); if (commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { // Reads and writes must be executed in order. Then if // the next command for this request is read or write diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp b/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp index 05a4e745..7fe82b7c 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp @@ -81,7 +81,7 @@ std::pair FR_FCFS::getNextRequest(Bank bank) if (it != buffer[bank].end()) { gp *payload = *it; buffer[bank].erase(it); - return pair(getReadWriteCommand(*payload), payload); + return pair(getReadWriteCommand(payload), payload); } // If there is no row hit, the FR_FCFS takes always the oldest transaction diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp b/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp index 40a8258e..9fa2030f 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp @@ -74,7 +74,7 @@ std::pair FR_FCFS_GRP::getNextRequest(Bank bank) if (hazardDetection(bank, it) == false) { buffer[bank].erase(it); printDebugMessage("Read Hit found"); - return pair(getReadWriteCommand(*read), + return pair(getReadWriteCommand(read), read); } else { // If there was a hazard, switch the mode and try again: @@ -112,7 +112,7 @@ std::pair FR_FCFS_GRP::getNextRequest(Bank bank) .getRowInRowBuffer(bank)) { buffer[bank].erase(it); printDebugMessage("Write Hit found"); - return pair(getReadWriteCommand(*write), + return pair(getReadWriteCommand(write), write); } } diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp b/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp index 57c2f60f..117583c6 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp @@ -62,7 +62,7 @@ std::pair FR_FCFS_RP::getNextRequest(Bank bank) if (hazardDetection(bank, it) == false) { buffer[bank].erase(it); printDebugMessage("Read Hit found"); - return pair(getReadWriteCommand(*read), read); + return pair(getReadWriteCommand(read), read); } } } @@ -78,7 +78,7 @@ std::pair FR_FCFS_RP::getNextRequest(Bank bank) == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { buffer[bank].erase(it); printDebugMessage("Write Hit found"); - return pair(getReadWriteCommand(*write), write); + return pair(getReadWriteCommand(write), write); } } } diff --git a/DRAMSys/library/src/controller/scheduler/SMS.cpp b/DRAMSys/library/src/controller/scheduler/SMS.cpp index 0f407775..42530571 100644 --- a/DRAMSys/library/src/controller/scheduler/SMS.cpp +++ b/DRAMSys/library/src/controller/scheduler/SMS.cpp @@ -30,7 +30,7 @@ std::pair SMS::getNextRequest(Bank bank) return pair(Command::NOP, NULL); } else { gp *payload = bankBuffers[bank].front(); - Command command = IScheduler::getNextCommand(*payload); + Command command = IScheduler::getNextCommand(payload); if (command == Command::Read || command == Command::ReadA || command == Command::Write || command == Command::WriteA) { diff --git a/DRAMSys/library/src/controller/scheduler/grp.cpp b/DRAMSys/library/src/controller/scheduler/grp.cpp index 652405aa..afb06fac 100644 --- a/DRAMSys/library/src/controller/scheduler/grp.cpp +++ b/DRAMSys/library/src/controller/scheduler/grp.cpp @@ -74,7 +74,7 @@ std::pair GRP::getNextRequest(Bank bank) if (hazardDetection(bank, it) == false) { buffer[bank].erase(it); printDebugMessage("Read Hit found"); - return pair(getReadWriteCommand(*read), + return pair(getReadWriteCommand(read), read); } else { // If there was a hazard, switch the mode and try again: @@ -106,7 +106,7 @@ std::pair GRP::getNextRequest(Bank bank) .getRowInRowBuffer(bank)) { buffer[bank].erase(it); printDebugMessage("Write Hit found"); - return pair(getReadWriteCommand(*write), + return pair(getReadWriteCommand(write), write); } else { printDebugMessage("Write miss found"); From 5ac2701d2c809bfabe1a4123bd4e3e0eb55ea14e Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 00:52:28 +0200 Subject: [PATCH 08/30] Fix commit for renaming issue. --- .../scheduler/{grp.cpp => Grp_rename.cpp} | 18 +++++++++--------- .../scheduler/{grp.h => Grp_rename.h} | 19 +++++++------------ 2 files changed, 16 insertions(+), 21 deletions(-) rename DRAMSys/library/src/controller/scheduler/{grp.cpp => Grp_rename.cpp} (92%) rename DRAMSys/library/src/controller/scheduler/{grp.h => Grp_rename.h} (89%) diff --git a/DRAMSys/library/src/controller/scheduler/grp.cpp b/DRAMSys/library/src/controller/scheduler/Grp_rename.cpp similarity index 92% rename from DRAMSys/library/src/controller/scheduler/grp.cpp rename to DRAMSys/library/src/controller/scheduler/Grp_rename.cpp index afb06fac..aa6c49cf 100644 --- a/DRAMSys/library/src/controller/scheduler/grp.cpp +++ b/DRAMSys/library/src/controller/scheduler/Grp_rename.cpp @@ -33,14 +33,14 @@ * Matthias Jung */ -#include "grp.h" +#include "Grp.h" -// GRP just reorders w.r.t. read write grouping, however is not aware of the -// row buffer. For a row buffer aware grouper refer to FR_FCFS_GRP. +// Grp (Grouper) just reorders w.r.t. read write grouping, however is not aware of the +// row buffer. For a row buffer aware grouper refer to FrFcfsGrp. // TODO: what is missed is a check if the buffers are full. This will only work // if we have buffers with a fixed size (Prado's future patch). -std::pair GRP::getNextRequest(Bank bank) +std::pair Grp::getNextRequest(Bank bank) { // If the bank is empty we do nothing: if (buffer[bank].empty()) { @@ -131,12 +131,12 @@ std::pair GRP::getNextRequest(Bank bank) readMode = !readMode; return getNextRequest(bank); - reportFatal("GRP", "Never should go here ..."); + reportFatal("Grp", "Never should go here ..."); } // There is a hazard if a read is found which will be scheduled before a write // to the same column and the same row of the same bank: -bool GRP::hazardDetection(Bank bank, std::deque::iterator ext) +bool Grp::hazardDetection(Bank bank, std::deque::iterator ext) { gp *read = *ext; @@ -157,7 +157,7 @@ bool GRP::hazardDetection(Bank bank, std::deque::iterator ext) } // Estimate the number of writes/reads in all bank buffers: -unsigned int GRP::getNumberOfRequest(tlm::tlm_command cmd) +unsigned int Grp::getNumberOfRequest(tlm::tlm_command cmd) { unsigned int numberOfRequests = 0; for (unsigned int i = 0; @@ -174,7 +174,7 @@ unsigned int GRP::getNumberOfRequest(tlm::tlm_command cmd) return numberOfRequests; } -void GRP::printDebugMessage(std::string message) +void Grp::printDebugMessage(std::string message) { - DebugManager::getInstance().printDebugMessage("FR_FCFS_GRP", message); + DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); } diff --git a/DRAMSys/library/src/controller/scheduler/grp.h b/DRAMSys/library/src/controller/scheduler/Grp_rename.h similarity index 89% rename from DRAMSys/library/src/controller/scheduler/grp.h rename to DRAMSys/library/src/controller/scheduler/Grp_rename.h index 2ffc46e0..13ccea71 100644 --- a/DRAMSys/library/src/controller/scheduler/grp.h +++ b/DRAMSys/library/src/controller/scheduler/Grp_rename.h @@ -33,29 +33,24 @@ * Matthias Jung */ -#ifndef GROUPER_H -#define GROUPER_H +#ifndef GRP_H +#define GRP_H -#include "Fr_Fcfs.h" +#include "FrFcfs.h" #include "../Controller.h" class Controller; -class GRP : public FR_FCFS +class Grp : public FrFcfs { public: - GRP(ControllerCore &controllerCore, Controller *c) : - FR_FCFS(controllerCore), - ctrl(c), - readMode(true) - { - } + Grp(ControllerCore &controllerCore, Controller *c) + : FrFcfs(controllerCore), ctrl(c), readMode(true) {} std::pair getNextRequest(Bank bank) override; private: - Controller *ctrl; bool hazardDetection(Bank bank, std::deque::iterator ext); unsigned int getNumberOfRequest(tlm::tlm_command cmd); @@ -63,4 +58,4 @@ private: bool readMode; }; -#endif // GROUPER_H +#endif // GRP_H From 193893c23b362e06d33277265c6c6655bf6d075b Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 00:54:02 +0200 Subject: [PATCH 09/30] Renaming of schedulers. --- DRAMSys/library/library.pro | 22 +++++++------------ DRAMSys/library/src/controller/Controller.cpp | 8 +++---- DRAMSys/library/src/controller/Controller.h | 6 ++--- .../scheduler/{Fr_Fcfs.cpp => FrFcfs.cpp} | 14 ++++++------ .../scheduler/{Fr_Fcfs.h => FrFcfs.h} | 18 +++++++-------- .../{Fr_Fcfs_grouper.cpp => FrFcfsGrp.cpp} | 19 ++++++++-------- .../{Fr_Fcfs_grouper.h => FrFcfsGrp.h} | 19 ++++++---------- ...Fr_Fcfs_read_priority.cpp => FrFcfsRp.cpp} | 17 +++++++------- .../{Fr_Fcfs_read_priority.h => FrFcfsRp.h} | 14 +++++------- .../scheduler/{Grp_rename.cpp => Grp.cpp} | 0 .../scheduler/{Grp_rename.h => Grp.h} | 0 11 files changed, 62 insertions(+), 75 deletions(-) rename DRAMSys/library/src/controller/scheduler/{Fr_Fcfs.cpp => FrFcfs.cpp} (91%) rename DRAMSys/library/src/controller/scheduler/{Fr_Fcfs.h => FrFcfs.h} (87%) rename DRAMSys/library/src/controller/scheduler/{Fr_Fcfs_grouper.cpp => FrFcfsGrp.cpp} (92%) rename DRAMSys/library/src/controller/scheduler/{Fr_Fcfs_grouper.h => FrFcfsGrp.h} (87%) rename DRAMSys/library/src/controller/scheduler/{Fr_Fcfs_read_priority.cpp => FrFcfsRp.cpp} (90%) rename DRAMSys/library/src/controller/scheduler/{Fr_Fcfs_read_priority.h => FrFcfsRp.h} (89%) rename DRAMSys/library/src/controller/scheduler/{Grp_rename.cpp => Grp.cpp} (100%) rename DRAMSys/library/src/controller/scheduler/{Grp_rename.h => Grp.h} (100%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 8063b653..e4e8eedb 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -95,9 +95,7 @@ SOURCES += \ src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ src/controller/core/powerdown/PowerDownManagerBankwise.cpp \ src/controller/core/powerdown/PowerDownManager.cpp \ - src/controller/scheduler/ThreadLoad.cpp \ - src/controller/scheduler/PARBS.cpp \ - src/controller/scheduler/Fr_Fcfs.cpp \ + src/controller/scheduler/FrFcfs.cpp \ src/controller/scheduler/Fifo.cpp \ src/controller/scheduler/SMS.cpp \ src/controller/core/refresh/RefreshManagerBankwise.cpp \ @@ -118,7 +116,6 @@ SOURCES += \ src/controller/core/ControllerCore.cpp \ src/simulation/MemoryManager.cpp \ src/simulation/TemperatureController.cpp \ - src/controller/scheduler/readwritegrouper.cpp \ src/controller/core/configuration/ConfigurationLoader.cpp \ src/controller/core/powerdown/NoPowerDown.cpp \ src/controller/Command.cpp \ @@ -138,11 +135,11 @@ SOURCES += \ src/error/ECC/Word.cpp \ src/error/eccbaseclass.cpp \ src/error/ecchamming.cpp \ - src/controller/scheduler/Fr_Fcfs_read_priority.cpp \ - src/controller/scheduler/Fr_Fcfs_grouper.cpp \ + src/controller/scheduler/FrFcfsRp.cpp \ + src/controller/scheduler/FrFcfsGrp.cpp \ + src/controller/scheduler/Grp.cpp \ src/controller/RecordableController.cpp \ src/common/AddressDecoder.cpp \ - src/controller/scheduler/grp.cpp \ src/common/congenAddressDecoder.cpp \ src/simulation/Dram.cpp \ src/simulation/RecordableDram.cpp \ @@ -161,9 +158,7 @@ HEADERS += \ src/controller/core/powerdown/PowerDownManagerTimeout.h \ src/controller/core/powerdown/PowerDownManagerBankwise.h \ src/controller/core/powerdown/PowerDownManager.h \ - src/controller/scheduler/ThreadLoad.h \ - src/controller/scheduler/PARBS.h \ - src/controller/scheduler/Fr_Fcfs.h \ + src/controller/scheduler/FrFcfs.h \ src/controller/scheduler/Fifo.h \ src/controller/scheduler/SMS.h \ src/controller/Controller.h \ @@ -191,7 +186,6 @@ HEADERS += \ src/simulation/Dram.h \ src/simulation/Arbiter.h \ src/common/libDRAMPower.h \ - src/controller/scheduler/readwritegrouper.h \ src/simulation/ReorderBuffer.h \ src/controller/core/configuration/MemSpec.h \ src/controller/core/configuration/thermalSimConfig.h \ @@ -219,14 +213,14 @@ HEADERS += \ src/error/ECC/Word.h \ src/error/eccbaseclass.h \ src/error/ecchamming.h \ - src/controller/scheduler/Fr_Fcfs_read_priority.h \ - src/controller/scheduler/Fr_Fcfs_grouper.h \ + src/controller/scheduler/FrFcfsRp.h \ + src/controller/scheduler/FrFcfsGrp.h \ + src/controller/scheduler/Grp.h \ src/simulation/IArbiter.h \ src/simulation/SimpleArbiter.h \ src/controller/RecordableController.h \ src/simulation/RecordableDram.h \ src/common/AddressDecoder.h \ - src/controller/scheduler/grp.h \ src/common/congenAddressDecoder.h #src/common/third_party/json/include/nlohmann/json.hpp \ diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 27055763..242bde35 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -61,13 +61,13 @@ void Controller::buildScheduler() } else if (selectedScheduler == "FIFO_STRICT") { scheduler = new FifoStrict(*this, *controllerCore); } else if (selectedScheduler == "FR_FCFS") { - scheduler = new FR_FCFS(*controllerCore); + scheduler = new FrFcfs(*controllerCore); } else if (selectedScheduler == "FR_FCFS_RP") { - scheduler = new FR_FCFS_RP(*controllerCore); + scheduler = new FrFcfsRp(*controllerCore); } else if (selectedScheduler == "FR_FCFS_GRP") { - scheduler = new FR_FCFS_GRP(*controllerCore, this); + scheduler = new FrFcfsGrp(*controllerCore, this); } else if (selectedScheduler == "GRP") { - scheduler = new GRP(*controllerCore, this); + scheduler = new Grp(*controllerCore, this); } else if (selectedScheduler == "SMS") { scheduler = new SMS("SMS", *controllerCore, Configuration::getInstance().SJFProbability); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 8df4f8b0..f26e2fb8 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -67,9 +67,9 @@ #include "scheduler/Fifo.h" #include "scheduler/grp.h" #include "scheduler/FifoStrict.h" -#include "scheduler/Fr_Fcfs.h" -#include "scheduler/Fr_Fcfs_read_priority.h" -#include "scheduler/Fr_Fcfs_grouper.h" +#include "scheduler/FrFcfs.h" +#include "scheduler/FrFcfsRp.h" +#include "scheduler/FrFcfsGrp.h" #include "scheduler/SMS.h" #include "scheduler/IScheduler.h" diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp similarity index 91% rename from DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp rename to DRAMSys/library/src/controller/scheduler/FrFcfs.cpp index 7fe82b7c..c51b9192 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp @@ -35,17 +35,17 @@ * Matthias Jung */ -#include "Fr_Fcfs.h" +#include "FrFcfs.h" #include "../../common/dramExtension.h" #include "../core/configuration/Configuration.h" #include using namespace std; -// The FR_FCFS is descibed in a 2000 paper from Rixner et al.: +// The FrFcfs (First Ready First Come First Served) is descibed in a 2000 paper from Rixner et al.: // Memory Access Scheduling // -// The FR_FCFS scheduler features for each bank in the DRAM a specific +// The FrFcfs scheduler features for each bank in the DRAM a specific // scheduling buffer for example: // // Bank0: OOOOOOOO @@ -58,7 +58,7 @@ using namespace std; // Bank6: OOOOO0XX // Bank7: XXXXXXXX -void FR_FCFS::storeRequest(gp *payload) +void FrFcfs::storeRequest(gp *payload) { // FIXME: Question: what if the buffer is full? IMHO the schedule function // should provide a true or false when the placement into the buffer worked @@ -67,7 +67,7 @@ void FR_FCFS::storeRequest(gp *payload) .emplace_back(payload); } -std::pair FR_FCFS::getNextRequest(Bank bank) +std::pair FrFcfs::getNextRequest(Bank bank) { // If the bank is empty like Bank0 in the example we do nothing if (buffer[bank].empty()) { @@ -97,7 +97,7 @@ std::pair FR_FCFS::getNextRequest(Bank bank) // deque container. The past-the-end element is the theoretical element that // would follow the last element in the deque container. It does not point to // any element, and thus shall not be dereferenced. -deque::iterator FR_FCFS::FindRowHit(Bank bank) +deque::iterator FrFcfs::FindRowHit(Bank bank) { deque &queue = buffer[bank]; @@ -117,7 +117,7 @@ deque::iterator FR_FCFS::FindRowHit(Bank bank) return queue.end(); } -gp *FR_FCFS::getPendingRequest(Bank /*bank*/) +gp *FrFcfs::getPendingRequest(Bank /*bank*/) { return NULL; } diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.h b/DRAMSys/library/src/controller/scheduler/FrFcfs.h similarity index 87% rename from DRAMSys/library/src/controller/scheduler/Fr_Fcfs.h rename to DRAMSys/library/src/controller/scheduler/FrFcfs.h index 983c664a..ea8d250e 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs.h +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.h @@ -35,8 +35,8 @@ * Matthias Jung */ -#ifndef FR_FCFS_H_ -#define FR_FCFS_H_ +#ifndef FRFCFS_H_ +#define FRFCFS_H_ #include "IScheduler.h" #include "../core/ControllerCore.h" @@ -44,16 +44,15 @@ #include #include - -class FR_FCFS : public IScheduler +class FrFcfs : public IScheduler { public: - FR_FCFS(ControllerCore &controllerCore) : IScheduler(controllerCore) {} - virtual ~FR_FCFS() {} + FrFcfs(ControllerCore &controllerCore) : IScheduler(controllerCore) {} + virtual ~FrFcfs() {} void storeRequest(gp *payload) override; - std::pair getNextRequest( - Bank bank) override; + std::pair + getNextRequest(Bank bank) override; virtual gp *getPendingRequest(Bank bank) override; protected: @@ -64,5 +63,4 @@ private: }; - -#endif +#endif // FRFCFS_H_ diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp similarity index 92% rename from DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp rename to DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp index 9fa2030f..ef5d1bc1 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp @@ -33,14 +33,15 @@ * Matthias Jung */ -#include "Fr_Fcfs_grouper.h" +#include "FrFcfsGrp.h" -// The FR_FCFS_Read_Priority works exactly like the FR_FCFS_RP. -// However writes are grouped! For detailed documentation look into the FR_FCFS. +// The FrFcfsGrp (First Ready First Come First Served Grouper) works exactly +// like the FrFcfsRp (First Ready First Come First Served Read Priority). +// However writes are grouped! For detailed documentation look into the FrFcfs. // TODO: what is missed is a check if the buffers are full. This will only work // if we have buffers with a fixed size (Prado's future patch). -std::pair FR_FCFS_GRP::getNextRequest(Bank bank) +std::pair FrFcfsGrp::getNextRequest(Bank bank) { // If the bank is empty we do nothing: if (buffer[bank].empty()) { @@ -144,12 +145,12 @@ std::pair FR_FCFS_GRP::getNextRequest(Bank bank) readMode = !readMode; return getNextRequest(bank); - reportFatal("FR_FCFS_GRP", "Never should go here ..."); + reportFatal("FrFcfsGrp", "Never should go here ..."); } // There is a hazard if a read is found which will be scheduled before a write // to the same column and the same row of the same bank: -bool FR_FCFS_GRP::hazardDetection(Bank bank, std::deque::iterator ext) +bool FrFcfsGrp::hazardDetection(Bank bank, std::deque::iterator ext) { gp *read = *ext; @@ -170,7 +171,7 @@ bool FR_FCFS_GRP::hazardDetection(Bank bank, std::deque::iterator ext) } // Estimate the number of writes/reads in all bank buffers: -unsigned int FR_FCFS_GRP::getNumberOfRequest(tlm::tlm_command cmd) +unsigned int FrFcfsGrp::getNumberOfRequest(tlm::tlm_command cmd) { unsigned int numberOfRequests = 0; for (unsigned int i = 0; @@ -187,7 +188,7 @@ unsigned int FR_FCFS_GRP::getNumberOfRequest(tlm::tlm_command cmd) return numberOfRequests; } -void FR_FCFS_GRP::printDebugMessage(std::string message) +void FrFcfsGrp::printDebugMessage(std::string message) { - DebugManager::getInstance().printDebugMessage("FR_FCFS_GRP", message); + DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); } diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.h b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h similarity index 87% rename from DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.h rename to DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h index 6ae8ff08..ffcf0b5a 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_grouper.h +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h @@ -33,29 +33,24 @@ * Matthias Jung */ -#ifndef FR_FCFS_GROUPER_H -#define FR_FCFS_GROUPER_H +#ifndef FRFCFSGRP_H +#define FRFCFSGRP_H -#include "Fr_Fcfs.h" +#include "FrFcfs.h" #include "../Controller.h" class Controller; -class FR_FCFS_GRP : public FR_FCFS +class FrFcfsGrp : public FrFcfs { public: - FR_FCFS_GRP(ControllerCore &controllerCore, Controller *c) : - FR_FCFS(controllerCore), - ctrl(c), - readMode(true) - { - } + FrFcfsGrp(ControllerCore &controllerCore, Controller *c) + : FrFcfs(controllerCore), ctrl(c), readMode(true) {} std::pair getNextRequest(Bank bank) override; private: - Controller *ctrl; bool hazardDetection(Bank bank, std::deque::iterator ext); unsigned int getNumberOfRequest(tlm::tlm_command cmd); @@ -63,4 +58,4 @@ private: bool readMode; }; -#endif // FR_FCFS_GROUPER_H +#endif // FRFCFSGRP_H diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp similarity index 90% rename from DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp rename to DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp index 117583c6..250510c0 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp @@ -33,12 +33,13 @@ * Matthias Jung */ -#include "Fr_Fcfs_read_priority.h" +#include "FrFcfsRp.h" -// The FR_FCFS_Read_Priority works exactly like the FR_FCFS but reads are -// prioratized over writes. For detailed documentation look into the FR_FCFS. +// The FrFcfsRp (First Ready First Come First Served Read Priority) works +// exactly like the FrFcfs but reads are prioratized over writes. +// For detailed documentation look into the FrFcfs. -std::pair FR_FCFS_RP::getNextRequest(Bank bank) +std::pair FrFcfsRp::getNextRequest(Bank bank) { // If the bank is empty like Bank0 in the example we do nothing: if (buffer[bank].empty()) { @@ -107,13 +108,13 @@ std::pair FR_FCFS_RP::getNextRequest(Bank bank) } } - reportFatal("FR_FCFS_RP", "Never should go here ..."); + reportFatal("FrFcfsRp", "Never should go here ..."); return pair(Command::NOP, NULL); } // There is a hazard if a read is found which will be scheduled before a write // to the same column and the same row of the same bank: -bool FR_FCFS_RP::hazardDetection(Bank bank, std::deque::iterator ext) +bool FrFcfsRp::hazardDetection(Bank bank, std::deque::iterator ext) { gp *read = *ext; @@ -133,7 +134,7 @@ bool FR_FCFS_RP::hazardDetection(Bank bank, std::deque::iterator ext) return false; } -void FR_FCFS_RP::printDebugMessage(std::string message) +void FrFcfsRp::printDebugMessage(std::string message) { - DebugManager::getInstance().printDebugMessage("FR_FCFS_RP", message); + DebugManager::getInstance().printDebugMessage("FrFcfsRp", message); } diff --git a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.h b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.h similarity index 89% rename from DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.h rename to DRAMSys/library/src/controller/scheduler/FrFcfsRp.h index fac0af85..c1c10ca4 100644 --- a/DRAMSys/library/src/controller/scheduler/Fr_Fcfs_read_priority.h +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.h @@ -33,23 +33,21 @@ * Matthias Jung */ -#ifndef FR_FCFS_READ_PRIORITY_H -#define FR_FCFS_READ_PRIORITY_H +#ifndef FRFCFSRP_H +#define FRFCFSRP_H -#include "Fr_Fcfs.h" +#include "FrFcfs.h" -class FR_FCFS_RP : public FR_FCFS +class FrFcfsRp : public FrFcfs { public: - FR_FCFS_RP(ControllerCore &controllerCore) : FR_FCFS(controllerCore) {} - + FrFcfsRp(ControllerCore &controllerCore) : FrFcfs(controllerCore) {} std::pair getNextRequest(Bank bank) override; private: - bool hazardDetection(Bank bank, std::deque::iterator ext); void printDebugMessage(std::string message); }; -#endif // FR_FCFS_READ_PRIORITY_H +#endif // FRFCFSRP_H diff --git a/DRAMSys/library/src/controller/scheduler/Grp_rename.cpp b/DRAMSys/library/src/controller/scheduler/Grp.cpp similarity index 100% rename from DRAMSys/library/src/controller/scheduler/Grp_rename.cpp rename to DRAMSys/library/src/controller/scheduler/Grp.cpp diff --git a/DRAMSys/library/src/controller/scheduler/Grp_rename.h b/DRAMSys/library/src/controller/scheduler/Grp.h similarity index 100% rename from DRAMSys/library/src/controller/scheduler/Grp_rename.h rename to DRAMSys/library/src/controller/scheduler/Grp.h From 6bc5f6ead3fe0909a4333a01e9db96ca76b75d63 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 00:54:55 +0200 Subject: [PATCH 10/30] Removed unused files in folder scheduler. --- .../src/controller/scheduler/PARBS.cpp | 149 -------------- .../library/src/controller/scheduler/PARBS.h | 77 ------- .../src/controller/scheduler/ThreadLoad.cpp | 108 ---------- .../src/controller/scheduler/ThreadLoad.h | 81 -------- .../controller/scheduler/readwritegrouper.cpp | 191 ------------------ .../controller/scheduler/readwritegrouper.h | 78 ------- 6 files changed, 684 deletions(-) delete mode 100644 DRAMSys/library/src/controller/scheduler/PARBS.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/PARBS.h delete mode 100644 DRAMSys/library/src/controller/scheduler/ThreadLoad.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/ThreadLoad.h delete mode 100644 DRAMSys/library/src/controller/scheduler/readwritegrouper.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/readwritegrouper.h diff --git a/DRAMSys/library/src/controller/scheduler/PARBS.cpp b/DRAMSys/library/src/controller/scheduler/PARBS.cpp deleted file mode 100644 index fcc65896..00000000 --- a/DRAMSys/library/src/controller/scheduler/PARBS.cpp +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - - -//// * PARBS.cpp -//// * -//// * Created on: Apr 9, 2014 -//// * Author: robert -//// */ - -//#include "PARBS.h" -//#include "../core/configuration/Configuration.h" -//#include "../../common/dramExtension.h" -//#include "map" -//#include "ThreadLoad.h" -//#include - -//namespace scheduler { - -//using namespace std; - -//PAR_BS::PAR_BS(ControllerCore& controllerCore, bool useExternalBankstates, unsigned int capsize) : -// controllerCore(controllerCore), useExternalBankstates(useExternalBankstates), capsize(capsize) -//{ -// if (useExternalBankstates) -// { -// batch = new FR_FCFS(controllerCore, true, false); -// buffer = new FR_FCFS(controllerCore, true, false); -// } -// else -// { -// batch = new FR_FCFS(controllerCore, true, false); -// buffer = new FR_FCFS(controllerCore, true, false); -// } -//} - -//PAR_BS::~PAR_BS() -//{ - -//} - -//bool PAR_BS::hasPayloads() -//{ -// return batch->hasPayloads() || buffer->hasPayloads(); -//} - -//void PAR_BS::schedule(gp* payload) -//{ -// printDebugMessage("hello!"); -// buffer->schedule(payload); -//} - -//gp* PAR_BS::getNextPayload() -//{ -// if (!batch->hasPayloads()) -// { -// stringstream s; -// s << "In batch: " << batch->getNumberOfQueuedPayloads() << "\t" << "in buffer: " << buffer->getNumberOfQueuedPayloads() << endl; -// formBatch(); -// s<< "Formed new batch" << endl; -// s << "In batch: " << batch->getNumberOfQueuedPayloads() << "\t" << "in buffer: " << buffer->getNumberOfQueuedPayloads() << endl; -// printDebugMessage(s.str()); -// sc_assert(batch->hasPayloads()); -// } - -// gp* result = batch->getNextPayload(); -// if(result == NULL) -// result = buffer->getNextPayload(); -// return result; -//} - -//void PAR_BS::removePayload(gp* payload) -//{ -// buffer->removePayload(payload); -// batch->removePayload(payload); - -// if (!useExternalBankstates) -// { -// DramExtension& extension = DramExtension::getExtension(payload); -// internalBankstates.openRowInRowBuffer(extension.getBank(), extension.getRow()); -// } - -//} - -//void PAR_BS::formBatch() -//{ -// map loads; - -// for (Bank bank : controllerCore.getBanks()) -// { -// for (unsigned int i = 0; i < capsize; i++) -// { -// gp* payload = buffer->popOldest(bank); -// if(payload == NULL) -// break; -// loads[DramExtension::getExtension(payload).getThread()].addTransaction(payload); -// } -// } - -// vector sortedLoads; -// for (auto& threadLoadPair : loads) -// { -// sortedLoads.push_back(&threadLoadPair.second); -// } - -// sort(sortedLoads.begin(), sortedLoads.end(), LoadPointerComparer()); - -// for (auto& load : sortedLoads) -// { -// batch->schedule(load->getTransactions()); -// } - -//} - -//} diff --git a/DRAMSys/library/src/controller/scheduler/PARBS.h b/DRAMSys/library/src/controller/scheduler/PARBS.h deleted file mode 100644 index 59e3f1e1..00000000 --- a/DRAMSys/library/src/controller/scheduler/PARBS.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - - -//// * PARBS.h -//// * -//// * Created on: Apr 9, 2014 -//// * Author: robert -//// * - -//#ifndef PARBS_H_ -//#define PARBS_H_ -//#include "Scheduler.h" -//#include "../core/ControllerCore.h" -//#include "Fr_Fcfs.h" - -//namespace scheduler { - -//class PAR_BS : public Scheduler -//{ -//public: -// PAR_BS(ControllerCore& controllerCore, bool useExternalBankstates, unsigned int capsize); -// virtual ~PAR_BS(); - -// virtual bool hasPayloads() override; -// virtual void schedule(gp* payload) override; -// virtual gp* getNextPayload() override; -// virtual void removePayload(gp* payload) override; - -//private: -// void formBatch(); - -// ControllerCore& controllerCore; -// bool useExternalBankstates; -// RowBufferState internalBankstates; -// FR_FCFS *batch; -// FR_FCFS *buffer; -// unsigned int capsize; -//}; - -//} /* scheduler core */ - -//#endif diff --git a/DRAMSys/library/src/controller/scheduler/ThreadLoad.cpp b/DRAMSys/library/src/controller/scheduler/ThreadLoad.cpp deleted file mode 100644 index 1938c1d3..00000000 --- a/DRAMSys/library/src/controller/scheduler/ThreadLoad.cpp +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - - -// * ThreadLoad.cpp -// * -// * Created on: Apr 9, 2014 -// * Author: robert -// */ - -//#include "ThreadLoad.h" - -//namespace scheduler { - -//using namespace std; - -//ThreadLoad::ThreadLoad() -//{ -// // TODO Auto-generated constructor stub - -//} - -//ThreadLoad::~ThreadLoad() -//{ -// // TODO Auto-generated destructor stub -//} - -//unsigned int ThreadLoad::getMaxBankLoad() const -//{ -// unsigned int maxLoad = 0; -// for (auto& bankVectorPair : load) -// { -// if (bankVectorPair.second.size() > maxLoad) -// maxLoad = bankVectorPair.second.size(); -// } -// return maxLoad; -//} - -//unsigned int ThreadLoad::getTotalLoad() const -//{ -// unsigned int totalLoad = 0; -// for (auto& bankVectorPair : load) -// { -// totalLoad += bankVectorPair.second.size(); -// } -// return totalLoad; -//} - -//void ThreadLoad::addTransaction(gp* payload) -//{ -// load[DramExtension::getExtension(payload).getBank()].push_back(payload); -//} - -//bool operator<(const ThreadLoad& lhs, const ThreadLoad& rhs) -//{ -// if (lhs.getMaxBankLoad() < rhs.getMaxBankLoad()) -// return true; -// else if (lhs.getMaxBankLoad() == rhs.getMaxBankLoad()) -// return lhs.getTotalLoad() < rhs.getTotalLoad(); -// else -// return false; -//} - -//vector ThreadLoad::getTransactions() -//{ -// vector result; -// for (auto& bankVectorPair : load) -// { -// result.insert(result.end(), bankVectorPair.second.begin(), bankVectorPair.second.end()); -// } -// return result; -//} - -//} /* namespace scheduler diff --git a/DRAMSys/library/src/controller/scheduler/ThreadLoad.h b/DRAMSys/library/src/controller/scheduler/ThreadLoad.h deleted file mode 100644 index f4152a05..00000000 --- a/DRAMSys/library/src/controller/scheduler/ThreadLoad.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - - -//// * ThreadLoad.h -//// * -//// * Created on: Apr 9, 2014 -//// * Author: robert -//// */ - -//#ifndef THREADLOAD_H_ -//#define THREADLOAD_H_ -//#include -//#include -//#include "../../common/dramExtension.h" - -//namespace scheduler { - -//typedef tlm::tlm_generic_payload gp; - -//class ThreadLoad -//{ -//public: -// ThreadLoad();d -// virtual ~ThreadLoad(); - -// unsigned int getMaxBankLoad() const; -// unsigned int getTotalLoad() const; - -// void addTransaction(gp* payload); -// std::vector getTransactions(); - -//private: -// std::map> load; -//}; - -//bool operator< (const ThreadLoad &lhs, const ThreadLoad &rhs); - -//struct LoadPointerComparer { -// bool operator()(const ThreadLoad* l, const ThreadLoad* r) { -// return *l < *r; -// } -//}; - -//} /* namespace scheduler */ - -//#endif /* THREADLOAD_H_ diff --git a/DRAMSys/library/src/controller/scheduler/readwritegrouper.cpp b/DRAMSys/library/src/controller/scheduler/readwritegrouper.cpp deleted file mode 100644 index e290fddd..00000000 --- a/DRAMSys/library/src/controller/scheduler/readwritegrouper.cpp +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -//#include "readwritegrouper.h" -//#include "../../common/DebugManager.h" - -//namespace scheduler{ - -//using namespace tlm; -//using namespace std; - -//ReadWriteGrouper::ReadWriteGrouper(ControllerCore& controllerCore): controllerCore(controllerCore) -//{ -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -//} - -//ReadWriteGrouper::~ReadWriteGrouper() -//{ - -//} - -//void ReadWriteGrouper::schedule(gp *payload) -//{ -// tlm_command command = payload->get_command(); - -// if(batches.size() > 2) -// { -// if(command == TLM_READ_COMMAND) -// { -// //printDebugMessage("Scheduling read"); - -// if(schedulingReadCausesHazardWithQueuedWrite(payload)) -// { -// printDebugMessage("Scheduling read causes hazard with queued write"); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// } - -// getLatestReadBatch().schedule(payload); -// } -// else if(command == TLM_WRITE_COMMAND) -// { -// //printDebugMessage("Scheduling write"); -// getLatestWriteBatch().schedule(payload); -// } -// } -// else if(batches.size() == 2) -// { -// if(command == TLM_READ_COMMAND) -// { -// //printDebugMessage("Scheduling read"); - -// if(getLatestReadBatch().hasPayloads() && schedulingReadCausesHazardWithQueuedWrite(payload)) -// { -// printDebugMessage("Scheduling read causes hazard with queued write"); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// } -// else if(!getLatestReadBatch().hasPayloads() && getLatestWriteBatch().hasPayloads()) -// { -// printDebugMessage("Scheduling read, but there are writes to be processed first"); -// batches.erase(batches.begin()); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// batches.push_back(shared_ptr(new FR_FCFS(controllerCore,true,false))); -// } -// getLatestReadBatch().schedule(payload); - -// } -// else if(command == TLM_WRITE_COMMAND) -// { -// //printDebugMessage("Scheduling write"); -// getLatestWriteBatch().schedule(payload); -// } -// } -// else -// { -// sc_assert(false); -// } -//} - -//gp *ReadWriteGrouper::getNextPayload() -//{ -// if(batches.size() > 2) -// { -// return batches.front()->getNextPayload(); -// } -// else if(batches.size() == 2) -// { -// if(getLatestReadBatch().hasPayloads()) -// return getLatestReadBatch().getNextPayload(); -// else if(getLatestWriteBatch().hasPayloads()) -// return getLatestWriteBatch().getNextPayload(); -// else -// return NULL; -// } -// else -// { -// sc_assert(false); -// return NULL; -// } -//} - - -//void ReadWriteGrouper::removePayload(gp *payload) -//{ -// if(batches.size() > 2) -// { -// batches.front()->removePayload(payload); -// if(!batches.front()->hasPayloads()) -// batches.erase(batches.begin()); -// } -// else if(batches.size() == 2) -// { -// if(payload->is_read()) -// getLatestReadBatch().removePayload(payload); -// else -// getLatestWriteBatch().removePayload(payload); -// } -// else -// { -// sc_assert(false); -// } -//} - - -//bool ReadWriteGrouper::hasPayloads() -//{ -// if(batches.size() > 2) -// return true; -// else if(batches.size() == 2) -// return (getLatestReadBatch().hasPayloads() || getLatestWriteBatch().hasPayloads()); -// else -// { -// sc_assert(false); -// return NULL; -// } -//} - - -//bool ReadWriteGrouper::schedulingReadCausesHazardWithQueuedWrite(gp *payload) -//{ -// sc_assert(payload->is_read()); -// return getLatestWriteBatch().containsPayloadTragetingSameAddress(payload); -//} - -//FR_FCFS &ReadWriteGrouper::getLatestWriteBatch() -//{ -// return *batches[batches.size()-1]; -//} - -//FR_FCFS &ReadWriteGrouper::getLatestReadBatch() -//{ -// return *batches[batches.size()-2]; -//} - -//} diff --git a/DRAMSys/library/src/controller/scheduler/readwritegrouper.h b/DRAMSys/library/src/controller/scheduler/readwritegrouper.h deleted file mode 100644 index 760b17fc..00000000 --- a/DRAMSys/library/src/controller/scheduler/readwritegrouper.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -//#ifndef READWRITEGROUPER_H -//#define READWRITEGROUPER_H -//#include "Scheduler.h" -//#include "Fr_Fcfs.h" -//#include "../core/ControllerCore.h" -//#include -//#include - - -//namespace scheduler{ - -//class ReadWriteGrouper : public Scheduler -//{ -//public: -// ReadWriteGrouper(ControllerCore& controllerCore); -// ~ReadWriteGrouper(); -// virtual void schedule(gp* payload) override; -// virtual bool hasPayloads() override; -// virtual gp* getNextPayload() override; -// virtual void removePayload(gp* payload) override; - -//private: -// // contains batches of requests -// // last element always contains writes -// // next-to-last element always contains reads -// // there are always at least two batches -// // if there are more than two batches, batches[0] is never empty and -// // getNextPayload and removePayload are forwarded to batches[0] -// std::vector> batches; -// ControllerCore& controllerCore; - -// bool schedulingReadCausesHazardWithQueuedWrite(gp* payload); -// FR_FCFS& getLatestWriteBatch(); -// FR_FCFS& getLatestReadBatch(); - -//}; - - -//} - -//#endif // READWRITEGROUPER_H From cea3b26bd0d015dfc4f48bc4096fc04976877cd5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 01:49:27 +0200 Subject: [PATCH 11/30] Bugfix (incomplete renaming). --- DRAMSys/library/src/controller/Controller.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index f26e2fb8..3b604c63 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -65,7 +65,7 @@ #include "core/scheduling/Trigger.h" #include "core/TimingCalculation.h" #include "scheduler/Fifo.h" -#include "scheduler/grp.h" +#include "scheduler/Grp.h" #include "scheduler/FifoStrict.h" #include "scheduler/FrFcfs.h" #include "scheduler/FrFcfsRp.h" From 20797f61f517e42193dcf98ac9ea97c0b5b76d18 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 16:21:00 +0200 Subject: [PATCH 12/30] Renaming files (Commit 1 of 2) --- DRAMSys/library/library.pro | 10 +++++----- DRAMSys/library/src/common/AddressDecoder.cpp | 6 +++--- DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- DRAMSys/library/src/common/TlmRecorder.h | 2 +- ...Decoder.cpp => rename_CongenAddressDecoder.cpp} | 2 +- ...ressDecoder.h => rename_CongenAddressDecoder.h} | 0 ...essdecoder.cpp => rename_XmlAddressDecoder.cpp} | 14 +++++++------- ...Addressdecoder.h => rename_XmlAddressDecoder.h} | 4 ++-- .../core/configuration/Configuration.cpp | 2 +- DRAMSys/library/src/error/eccbaseclass.h | 2 +- DRAMSys/library/src/error/errormodel.h | 2 +- DRAMSys/library/src/simulation/Arbiter.h | 2 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 6 +++--- DRAMSys/library/src/simulation/IArbiter.h | 12 ++++++------ DRAMSys/library/src/simulation/SimpleArbiter.h | 2 +- DRAMSys/library/src/simulation/StlPlayer.h | 2 +- DRAMSys/library/src/simulation/TracePlayer.h | 2 +- 17 files changed, 36 insertions(+), 36 deletions(-) rename DRAMSys/library/src/common/{congenAddressDecoder.cpp => rename_CongenAddressDecoder.cpp} (99%) rename DRAMSys/library/src/common/{congenAddressDecoder.h => rename_CongenAddressDecoder.h} (100%) rename DRAMSys/library/src/common/{xmlAddressdecoder.cpp => rename_XmlAddressDecoder.cpp} (92%) rename DRAMSys/library/src/common/{xmlAddressdecoder.h => rename_XmlAddressDecoder.h} (98%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index e4e8eedb..6ea08e13 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -86,7 +86,6 @@ QMAKE_CXXFLAGS += -isystem $${systemc_home}/include SOURCES += \ src/common/third_party/tinyxml2/tinyxml2.cpp \ - src/common/xmlAddressdecoder.cpp \ src/common/Utils.cpp \ src/common/TlmRecorder.cpp \ src/common/dramExtension.cpp \ @@ -140,14 +139,14 @@ SOURCES += \ src/controller/scheduler/Grp.cpp \ src/controller/RecordableController.cpp \ src/common/AddressDecoder.cpp \ - src/common/congenAddressDecoder.cpp \ src/simulation/Dram.cpp \ src/simulation/RecordableDram.cpp \ - src/simulation/Arbiter.cpp + src/simulation/Arbiter.cpp \ + src/common/rename_CongenAddressDecoder.cpp \ + src/common/rename_XmlAddressDecoder.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ - src/common/xmlAddressdecoder.h \ src/common/Utils.h \ src/common/TlmRecorder.h \ src/common/tlm2_base_protocol_checker.h \ @@ -221,7 +220,8 @@ HEADERS += \ src/controller/RecordableController.h \ src/simulation/RecordableDram.h \ src/common/AddressDecoder.h \ - src/common/congenAddressDecoder.h + src/common/rename_CongenAddressDecoder.h \ + src/common/rename_XmlAddressDecoder.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index f5eb23ce..ee6b4b38 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -34,8 +34,8 @@ */ #include "AddressDecoder.h" -#include "xmlAddressdecoder.h" -#include "congenAddressDecoder.h" +#include "rename_XmlAddressDecoder.h" +#include "rename_CongenAddressDecoder.h" AddressDecoder *AddressDecoder::m_pInstance = nullptr; @@ -50,7 +50,7 @@ void AddressDecoder::createInstance(Type t) assert(m_pInstance == nullptr); switch (t) { case Type::XML: - m_pInstance = new xmlAddressDecoder; + m_pInstance = new XmlAddressDecoder; break; case Type::CONGEN: m_pInstance = new CongenAddressDecoder; diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index db59e640..3709a487 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -42,7 +42,7 @@ #include "TlmRecorder.h" #include "protocol.h" #include "dramExtension.h" -#include "xmlAddressdecoder.h" +#include "rename_XmlAddressDecoder.h" #include "../controller/core/configuration/Configuration.h" #include "../controller/Controller.h" diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 31deb14d..150e0c3b 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -49,7 +49,7 @@ #include #include #include -#include "xmlAddressdecoder.h" +#include "rename_XmlAddressDecoder.h" #include "DebugManager.h" #include "Utils.h" diff --git a/DRAMSys/library/src/common/congenAddressDecoder.cpp b/DRAMSys/library/src/common/rename_CongenAddressDecoder.cpp similarity index 99% rename from DRAMSys/library/src/common/congenAddressDecoder.cpp rename to DRAMSys/library/src/common/rename_CongenAddressDecoder.cpp index 5a366741..071967f8 100644 --- a/DRAMSys/library/src/common/congenAddressDecoder.cpp +++ b/DRAMSys/library/src/common/rename_CongenAddressDecoder.cpp @@ -33,7 +33,7 @@ * Johannes Feldmann */ -#include "congenAddressDecoder.h" +#include "rename_CongenAddressDecoder.h" #include "Utils.h" #include diff --git a/DRAMSys/library/src/common/congenAddressDecoder.h b/DRAMSys/library/src/common/rename_CongenAddressDecoder.h similarity index 100% rename from DRAMSys/library/src/common/congenAddressDecoder.h rename to DRAMSys/library/src/common/rename_CongenAddressDecoder.h diff --git a/DRAMSys/library/src/common/xmlAddressdecoder.cpp b/DRAMSys/library/src/common/rename_XmlAddressDecoder.cpp similarity index 92% rename from DRAMSys/library/src/common/xmlAddressdecoder.cpp rename to DRAMSys/library/src/common/rename_XmlAddressDecoder.cpp index 11f4549c..403ac560 100644 --- a/DRAMSys/library/src/common/xmlAddressdecoder.cpp +++ b/DRAMSys/library/src/common/rename_XmlAddressDecoder.cpp @@ -35,7 +35,7 @@ * Matthias Jung */ -#include "xmlAddressdecoder.h" +#include "rename_XmlAddressDecoder.h" #include #include "Utils.h" #include "bitset" @@ -44,12 +44,12 @@ using namespace std; using namespace tinyxml2; -xmlAddressDecoder::xmlAddressDecoder() +XmlAddressDecoder::XmlAddressDecoder() { addressmapping = NULL; } -void xmlAddressDecoder::setConfiguration(std::string addressConfigURI) +void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) { tinyxml2::XMLDocument doc; loadXML(addressConfigURI, doc); @@ -76,7 +76,7 @@ void xmlAddressDecoder::setConfiguration(std::string addressConfigURI) } -DecodedAddress xmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) +DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) { DecodedAddress result; result.channel = (addr & masks["channel"]) >> shifts["channel"]; @@ -92,7 +92,7 @@ DecodedAddress xmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) return result; } -sc_dt::uint64 xmlAddressDecoder::encodeAddress(DecodedAddress n) +sc_dt::uint64 XmlAddressDecoder::encodeAddress(DecodedAddress n) { return n.channel << shifts["channel"] | n.rank << shifts["rank"] | @@ -103,7 +103,7 @@ sc_dt::uint64 xmlAddressDecoder::encodeAddress(DecodedAddress n) n.bytes << shifts["bytes"]; } -bool xmlAddressDecoder::testConfigFile(std::string url) +bool XmlAddressDecoder::testConfigFile(std::string url) { // Simple test if the root node has the correct name. // This is suitable for now, but can be extended in future. @@ -115,7 +115,7 @@ bool xmlAddressDecoder::testConfigFile(std::string url) return (strcmp(addressMap->Name(), "addressmapping") == 0); } -void xmlAddressDecoder::print() +void XmlAddressDecoder::print() { cout << headline << endl; cout << "Address Mapping:" << endl << endl; diff --git a/DRAMSys/library/src/common/xmlAddressdecoder.h b/DRAMSys/library/src/common/rename_XmlAddressDecoder.h similarity index 98% rename from DRAMSys/library/src/common/xmlAddressdecoder.h rename to DRAMSys/library/src/common/rename_XmlAddressDecoder.h index de1e574c..6f87bcd5 100644 --- a/DRAMSys/library/src/common/xmlAddressdecoder.h +++ b/DRAMSys/library/src/common/rename_XmlAddressDecoder.h @@ -44,7 +44,7 @@ #include "third_party/tinyxml2/tinyxml2.h" #include "AddressDecoder.h" -class xmlAddressDecoder +class XmlAddressDecoder : private AddressDecoder { // Friendship needed so that the AddressDecoder can access the @@ -58,7 +58,7 @@ private: tinyxml2::XMLElement *addressmapping; public: - xmlAddressDecoder(); + XmlAddressDecoder(); virtual DecodedAddress decodeAddress(sc_dt::uint64 addr); virtual sc_dt::uint64 encodeAddress(DecodedAddress n); diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index 50f5d563..fa69feae 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -40,7 +40,7 @@ #include "Configuration.h" #include "ConfigurationLoader.h" -#include "../../../common/xmlAddressdecoder.h" +#include "../../../common/rename_XmlAddressDecoder.h" using namespace std; diff --git a/DRAMSys/library/src/error/eccbaseclass.h b/DRAMSys/library/src/error/eccbaseclass.h index 544eb420..4219d8c3 100644 --- a/DRAMSys/library/src/error/eccbaseclass.h +++ b/DRAMSys/library/src/error/eccbaseclass.h @@ -8,7 +8,7 @@ #include "ECC/ECC.h" -#include "../common/xmlAddressdecoder.h" +#include "../common/rename_XmlAddressDecoder.h" #include "../common/DebugManager.h" using namespace std; diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index c1f21c6e..5f942b14 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -40,7 +40,7 @@ #include #include #include "../controller/core/configuration/Configuration.h" -#include "../common/xmlAddressdecoder.h" +#include "../common/rename_XmlAddressDecoder.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" class errorModel : public sc_module diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 1c5687b0..feeedec3 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -46,7 +46,7 @@ #include #include #include -#include "../common/xmlAddressdecoder.h" +#include "../common/rename_XmlAddressDecoder.h" #include "../common/dramExtension.h" #include "../controller/core/TimingCalculation.h" #include "../controller/core/configuration/ConfigurationLoader.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 30b2393e..dc798194 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -46,8 +46,8 @@ #include "Setup.h" #include "../common/TlmRecorder.h" #include "../common/DebugManager.h" -#include "../common/xmlAddressdecoder.h" -#include "../common/congenAddressDecoder.h" +#include "../common/rename_XmlAddressDecoder.h" +#include "../common/rename_CongenAddressDecoder.h" #include "../controller/core/ControllerCore.h" #include "../controller/core/configuration/ConfigurationLoader.h" #include "../common/Utils.h" @@ -86,7 +86,7 @@ DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name, // ConfigurationLoader because some information from the xmlAddressDecoder // is needed to assure the coherence of the configuration. - if (xmlAddressDecoder::testConfigFile(pathToResources + "configs/amconfigs/" + + if (XmlAddressDecoder::testConfigFile(pathToResources + "configs/amconfigs/" + amconfig)) { AddressDecoder::createInstance(AddressDecoder::Type::XML); AddressDecoder::getInstance().setConfiguration(pathToResources diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 3c3460cc..88c1231b 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -101,7 +101,7 @@ protected: payload.set_auto_extension(genExtension); unsigned int burstlength = payload.get_streaming_width(); - DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress( + DecodedAddress decodedAddress = XmlAddressDecoder::getInstance().decodeAddress( payload.get_address()); // Check the valid range of decodedAddress if (addressIsValid(decodedAddress)) { @@ -118,21 +118,21 @@ protected: bool addressIsValid(DecodedAddress &decodedAddress) { if (decodedAddress.channel >= - xmlAddressDecoder::getInstance().amount["channel"]) { + XmlAddressDecoder::getInstance().amount["channel"]) { return false; } - if (decodedAddress.bank >= xmlAddressDecoder::getInstance().amount["bank"]) { + if (decodedAddress.bank >= XmlAddressDecoder::getInstance().amount["bank"]) { return false; } if (decodedAddress.bankgroup > - xmlAddressDecoder::getInstance().amount["bankgroup"]) { + XmlAddressDecoder::getInstance().amount["bankgroup"]) { return false; } if (decodedAddress.column >= - xmlAddressDecoder::getInstance().amount["column"]) { + XmlAddressDecoder::getInstance().amount["column"]) { return false; } - if (decodedAddress.row >= xmlAddressDecoder::getInstance().amount["row"]) { + if (decodedAddress.row >= XmlAddressDecoder::getInstance().amount["row"]) { return false; } return true; diff --git a/DRAMSys/library/src/simulation/SimpleArbiter.h b/DRAMSys/library/src/simulation/SimpleArbiter.h index ec1994ae..ed2f01b5 100644 --- a/DRAMSys/library/src/simulation/SimpleArbiter.h +++ b/DRAMSys/library/src/simulation/SimpleArbiter.h @@ -38,7 +38,7 @@ #define SIMPLEARBITER_H #include "IArbiter.h" -#include "../common/xmlAddressdecoder.h" +#include "../common/rename_XmlAddressDecoder.h" #include "../common/dramExtension.h" #include "../controller/core/TimingCalculation.h" diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index ee5ac0a0..9b7de8a9 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -40,7 +40,7 @@ #ifndef STLPLAYER_H #define STLPLAYER_H -#include "../common/xmlAddressdecoder.h" +#include "../common/rename_XmlAddressDecoder.h" #include "TracePlayer.h" using namespace std; diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index dd4cb8ae..f73516b3 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -49,7 +49,7 @@ #include "MemoryManager.h" #include "../controller/core/configuration/Configuration.h" #include "../common/DebugManager.h" -#include "../common/xmlAddressdecoder.h" +#include "../common/rename_XmlAddressDecoder.h" #include "../controller/core/TimingCalculation.h" #include "TracePlayerListener.h" From 761bd8946f2d55375cb181fc52c11121a27f9ca5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 16:22:45 +0200 Subject: [PATCH 13/30] Renaming files (Commit 2 of 2) --- DRAMSys/library/library.pro | 8 ++++---- DRAMSys/library/src/common/AddressDecoder.cpp | 4 ++-- ..._CongenAddressDecoder.cpp => CongenAddressDecoder.cpp} | 2 +- ...name_CongenAddressDecoder.h => CongenAddressDecoder.h} | 0 DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- DRAMSys/library/src/common/TlmRecorder.h | 2 +- ...rename_XmlAddressDecoder.cpp => XmlAddressDecoder.cpp} | 2 +- .../{rename_XmlAddressDecoder.h => XmlAddressDecoder.h} | 0 .../src/controller/core/configuration/Configuration.cpp | 2 +- DRAMSys/library/src/error/eccbaseclass.h | 2 +- DRAMSys/library/src/error/errormodel.h | 2 +- DRAMSys/library/src/simulation/Arbiter.h | 2 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 4 ++-- DRAMSys/library/src/simulation/SimpleArbiter.h | 2 +- DRAMSys/library/src/simulation/StlPlayer.h | 2 +- DRAMSys/library/src/simulation/TracePlayer.h | 2 +- 16 files changed, 19 insertions(+), 19 deletions(-) rename DRAMSys/library/src/common/{rename_CongenAddressDecoder.cpp => CongenAddressDecoder.cpp} (99%) rename DRAMSys/library/src/common/{rename_CongenAddressDecoder.h => CongenAddressDecoder.h} (100%) rename DRAMSys/library/src/common/{rename_XmlAddressDecoder.cpp => XmlAddressDecoder.cpp} (99%) rename DRAMSys/library/src/common/{rename_XmlAddressDecoder.h => XmlAddressDecoder.h} (100%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 6ea08e13..b1ab01a0 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -142,8 +142,8 @@ SOURCES += \ src/simulation/Dram.cpp \ src/simulation/RecordableDram.cpp \ src/simulation/Arbiter.cpp \ - src/common/rename_CongenAddressDecoder.cpp \ - src/common/rename_XmlAddressDecoder.cpp + src/common/CongenAddressDecoder.cpp \ + src/common/XmlAddressDecoder.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -220,8 +220,8 @@ HEADERS += \ src/controller/RecordableController.h \ src/simulation/RecordableDram.h \ src/common/AddressDecoder.h \ - src/common/rename_CongenAddressDecoder.h \ - src/common/rename_XmlAddressDecoder.h + src/common/CongenAddressDecoder.h \ + src/common/XmlAddressDecoder.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index ee6b4b38..b0a3b98f 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -34,8 +34,8 @@ */ #include "AddressDecoder.h" -#include "rename_XmlAddressDecoder.h" -#include "rename_CongenAddressDecoder.h" +#include "XmlAddressDecoder.h" +#include "CongenAddressDecoder.h" AddressDecoder *AddressDecoder::m_pInstance = nullptr; diff --git a/DRAMSys/library/src/common/rename_CongenAddressDecoder.cpp b/DRAMSys/library/src/common/CongenAddressDecoder.cpp similarity index 99% rename from DRAMSys/library/src/common/rename_CongenAddressDecoder.cpp rename to DRAMSys/library/src/common/CongenAddressDecoder.cpp index 071967f8..6d71e39b 100644 --- a/DRAMSys/library/src/common/rename_CongenAddressDecoder.cpp +++ b/DRAMSys/library/src/common/CongenAddressDecoder.cpp @@ -33,7 +33,7 @@ * Johannes Feldmann */ -#include "rename_CongenAddressDecoder.h" +#include "CongenAddressDecoder.h" #include "Utils.h" #include diff --git a/DRAMSys/library/src/common/rename_CongenAddressDecoder.h b/DRAMSys/library/src/common/CongenAddressDecoder.h similarity index 100% rename from DRAMSys/library/src/common/rename_CongenAddressDecoder.h rename to DRAMSys/library/src/common/CongenAddressDecoder.h diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 3709a487..f32ec20f 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -42,7 +42,7 @@ #include "TlmRecorder.h" #include "protocol.h" #include "dramExtension.h" -#include "rename_XmlAddressDecoder.h" +#include "XmlAddressDecoder.h" #include "../controller/core/configuration/Configuration.h" #include "../controller/Controller.h" diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 150e0c3b..f6b97c91 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -49,7 +49,7 @@ #include #include #include -#include "rename_XmlAddressDecoder.h" +#include "XmlAddressDecoder.h" #include "DebugManager.h" #include "Utils.h" diff --git a/DRAMSys/library/src/common/rename_XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp similarity index 99% rename from DRAMSys/library/src/common/rename_XmlAddressDecoder.cpp rename to DRAMSys/library/src/common/XmlAddressDecoder.cpp index 403ac560..1f487f65 100644 --- a/DRAMSys/library/src/common/rename_XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -35,7 +35,7 @@ * Matthias Jung */ -#include "rename_XmlAddressDecoder.h" +#include "XmlAddressDecoder.h" #include #include "Utils.h" #include "bitset" diff --git a/DRAMSys/library/src/common/rename_XmlAddressDecoder.h b/DRAMSys/library/src/common/XmlAddressDecoder.h similarity index 100% rename from DRAMSys/library/src/common/rename_XmlAddressDecoder.h rename to DRAMSys/library/src/common/XmlAddressDecoder.h diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index fa69feae..52904001 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -40,7 +40,7 @@ #include "Configuration.h" #include "ConfigurationLoader.h" -#include "../../../common/rename_XmlAddressDecoder.h" +#include "../../../common/XmlAddressDecoder.h" using namespace std; diff --git a/DRAMSys/library/src/error/eccbaseclass.h b/DRAMSys/library/src/error/eccbaseclass.h index 4219d8c3..720be2d7 100644 --- a/DRAMSys/library/src/error/eccbaseclass.h +++ b/DRAMSys/library/src/error/eccbaseclass.h @@ -8,7 +8,7 @@ #include "ECC/ECC.h" -#include "../common/rename_XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" #include "../common/DebugManager.h" using namespace std; diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index 5f942b14..e562401c 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -40,7 +40,7 @@ #include #include #include "../controller/core/configuration/Configuration.h" -#include "../common/rename_XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" class errorModel : public sc_module diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index feeedec3..86d1d1c9 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -46,7 +46,7 @@ #include #include #include -#include "../common/rename_XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" #include "../common/dramExtension.h" #include "../controller/core/TimingCalculation.h" #include "../controller/core/configuration/ConfigurationLoader.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index dc798194..1e3e5d1b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -46,8 +46,8 @@ #include "Setup.h" #include "../common/TlmRecorder.h" #include "../common/DebugManager.h" -#include "../common/rename_XmlAddressDecoder.h" -#include "../common/rename_CongenAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" +#include "../common/CongenAddressDecoder.h" #include "../controller/core/ControllerCore.h" #include "../controller/core/configuration/ConfigurationLoader.h" #include "../common/Utils.h" diff --git a/DRAMSys/library/src/simulation/SimpleArbiter.h b/DRAMSys/library/src/simulation/SimpleArbiter.h index ed2f01b5..bc2f7b9e 100644 --- a/DRAMSys/library/src/simulation/SimpleArbiter.h +++ b/DRAMSys/library/src/simulation/SimpleArbiter.h @@ -38,7 +38,7 @@ #define SIMPLEARBITER_H #include "IArbiter.h" -#include "../common/rename_XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" #include "../common/dramExtension.h" #include "../controller/core/TimingCalculation.h" diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index 9b7de8a9..b8b0e9a8 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -40,7 +40,7 @@ #ifndef STLPLAYER_H #define STLPLAYER_H -#include "../common/rename_XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" #include "TracePlayer.h" using namespace std; diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index f73516b3..5adbd09e 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -49,7 +49,7 @@ #include "MemoryManager.h" #include "../controller/core/configuration/Configuration.h" #include "../common/DebugManager.h" -#include "../common/rename_XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" #include "../controller/core/TimingCalculation.h" #include "TracePlayerListener.h" From cd67d638d43f4388c0facbaea48af84244e7156c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 19:28:31 +0200 Subject: [PATCH 14/30] Renaming files (Commit 1 of 2) --- DRAMSys/library/library.pro | 16 ++++++++-------- .../library/src/common/CongenAddressDecoder.cpp | 2 +- DRAMSys/library/src/common/DebugManager.h | 8 ++++---- DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- DRAMSys/library/src/common/TlmRecorder.h | 8 ++++---- DRAMSys/library/src/common/XmlAddressDecoder.cpp | 2 +- DRAMSys/library/src/common/XmlAddressDecoder.h | 8 ++++---- .../{dramExtension.cpp => dramExtensions.cpp} | 4 ++-- .../common/{dramExtension.h => dramExtensions.h} | 6 +++--- DRAMSys/library/src/common/protocol.h | 6 +++--- .../src/common/{Utils.cpp => rename_utils.cpp} | 4 ++-- .../src/common/{Utils.h => rename_utils.h} | 8 ++++---- DRAMSys/library/src/controller/Command.h | 6 +++--- DRAMSys/library/src/controller/Controller.h | 12 ++++++------ .../library/src/controller/ControllerState.cpp | 2 +- DRAMSys/library/src/controller/ControllerState.h | 6 +++--- DRAMSys/library/src/controller/IController.h | 2 +- .../library/src/controller/RowBufferStates.cpp | 2 +- DRAMSys/library/src/controller/RowBufferStates.h | 8 ++++---- .../src/controller/core/ControllerCore.cpp | 6 +++--- .../library/src/controller/core/ControllerCore.h | 6 +++--- DRAMSys/library/src/controller/core/Slots.cpp | 2 +- DRAMSys/library/src/controller/core/Slots.h | 8 ++++---- .../core/configuration/Configuration.h | 8 ++++---- .../core/configuration/ConfigurationLoader.cpp | 2 +- .../core/configuration/ConfigurationLoader.h | 8 ++++---- .../src/controller/core/configuration/MemSpec.h | 2 +- .../core/configuration/thermalSimConfig.h | 2 +- .../core/powerdown/IPowerDownManager.h | 8 ++++---- .../src/controller/core/powerdown/NoPowerDown.h | 2 +- .../core/powerdown/PowerDownManager.cpp | 4 ++-- .../controller/core/powerdown/PowerDownManager.h | 6 +++--- .../core/powerdown/PowerDownManagerBankwise.cpp | 4 ++-- .../core/powerdown/PowerDownManagerBankwise.h | 8 ++++---- .../core/powerdown/PowerDownManagerTimeout.cpp | 4 ++-- .../core/powerdown/PowerDownManagerTimeout.h | 8 ++++---- .../PowerDownManagerTimeoutBankwise.cpp | 4 ++-- .../powerdown/PowerDownManagerTimeoutBankwise.h | 8 ++++---- .../controller/core/refresh/IRefreshManager.h | 6 +++--- .../library/src/controller/core/refresh/RGR.cpp | 4 ++-- .../library/src/controller/core/refresh/RGR.h | 12 ++++++++---- .../controller/core/refresh/RefreshManager.cpp | 4 ++-- .../src/controller/core/refresh/RefreshManager.h | 6 +++--- .../core/refresh/RefreshManagerBankwise.cpp | 4 ++-- .../core/refresh/RefreshManagerBankwise.h | 6 +++--- .../core/scheduling/ScheduledCommand.cpp | 4 ++-- .../core/scheduling/ScheduledCommand.h | 10 +++++----- .../src/controller/core/scheduling/Trigger.h | 6 +++--- .../core/scheduling/checker/ActBChecker.cpp | 4 ++-- .../core/scheduling/checker/ActBChecker.h | 7 ++++--- .../core/scheduling/checker/ActivateChecker.cpp | 4 ++-- .../core/scheduling/checker/ActivateChecker.h | 6 +++--- .../core/scheduling/checker/ICommandChecker.h | 6 +++--- .../core/scheduling/checker/PowerDownChecker.cpp | 2 +- .../core/scheduling/checker/PowerDownChecker.h | 6 +++--- .../core/scheduling/checker/PreBChecker.cpp | 2 +- .../core/scheduling/checker/PreBChecker.h | 10 +++++++--- .../scheduling/checker/PrechargeAllChecker.cpp | 2 +- .../scheduling/checker/PrechargeAllChecker.h | 7 +++---- .../core/scheduling/checker/PrechargeChecker.cpp | 2 +- .../core/scheduling/checker/PrechargeChecker.h | 7 +++---- .../core/scheduling/checker/ReadChecker.cpp | 4 ++-- .../core/scheduling/checker/ReadChecker.h | 6 +++--- .../core/scheduling/checker/RefreshChecker.cpp | 2 +- .../core/scheduling/checker/RefreshChecker.h | 7 +++---- .../core/scheduling/checker/WriteChecker.cpp | 4 ++-- .../core/scheduling/checker/WriteChecker.h | 7 +++---- ...ingCalculation.cpp => timingCalculations.cpp} | 4 ++-- ...{TimingCalculation.h => timingCalculations.h} | 8 ++++---- DRAMSys/library/src/controller/scheduler/Fifo.h | 6 +++--- .../src/controller/scheduler/FifoStrict.h | 2 +- .../library/src/controller/scheduler/FrFcfs.cpp | 2 +- .../library/src/controller/scheduler/FrFcfs.h | 6 +++--- .../src/controller/scheduler/IScheduler.h | 2 +- DRAMSys/library/src/controller/scheduler/SMS.h | 2 +- DRAMSys/library/src/simulation/Arbiter.h | 10 +++++----- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/DRAMSys.h | 6 +++--- DRAMSys/library/src/simulation/Dram.cpp | 6 +++--- DRAMSys/library/src/simulation/Dram.h | 6 +++--- .../library/src/simulation/ExampleInitiator.h | 8 ++++---- DRAMSys/library/src/simulation/IArbiter.h | 6 +++--- DRAMSys/library/src/simulation/MemoryManager.h | 6 +++--- DRAMSys/library/src/simulation/RecordableDram.h | 6 +++--- DRAMSys/library/src/simulation/Setup.h | 2 +- DRAMSys/library/src/simulation/SimpleArbiter.h | 4 ++-- .../src/simulation/TemperatureController.h | 8 ++++---- DRAMSys/library/src/simulation/TraceGenerator.h | 2 +- DRAMSys/library/src/simulation/TracePlayer.h | 8 ++++---- DRAMSys/library/src/simulation/TraceSetup.h | 2 +- 90 files changed, 244 insertions(+), 239 deletions(-) rename DRAMSys/library/src/common/{dramExtension.cpp => dramExtensions.cpp} (99%) rename DRAMSys/library/src/common/{dramExtension.h => dramExtensions.h} (98%) rename DRAMSys/library/src/common/{Utils.cpp => rename_utils.cpp} (99%) rename DRAMSys/library/src/common/{Utils.h => rename_utils.h} (97%) rename DRAMSys/library/src/controller/core/{TimingCalculation.cpp => timingCalculations.cpp} (98%) rename DRAMSys/library/src/controller/core/{TimingCalculation.h => timingCalculations.h} (94%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index b1ab01a0..2c4050f5 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -86,9 +86,7 @@ QMAKE_CXXFLAGS += -isystem $${systemc_home}/include SOURCES += \ src/common/third_party/tinyxml2/tinyxml2.cpp \ - src/common/Utils.cpp \ src/common/TlmRecorder.cpp \ - src/common/dramExtension.cpp \ src/common/DebugManager.cpp \ src/controller/core/configuration/Configuration.cpp \ src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ @@ -110,7 +108,6 @@ SOURCES += \ src/controller/core/scheduling/checker/PreBChecker.cpp \ src/controller/core/scheduling/checker/ActBChecker.cpp \ src/controller/core/scheduling/ScheduledCommand.cpp \ - src/controller/core/TimingCalculation.cpp \ src/controller/core/Slots.cpp \ src/controller/core/ControllerCore.cpp \ src/simulation/MemoryManager.cpp \ @@ -143,15 +140,16 @@ SOURCES += \ src/simulation/RecordableDram.cpp \ src/simulation/Arbiter.cpp \ src/common/CongenAddressDecoder.cpp \ - src/common/XmlAddressDecoder.cpp + src/common/XmlAddressDecoder.cpp \ + src/common/rename_utils.cpp \ + src/controller/core/timingCalculations.cpp \ + src/common/dramExtensions.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ - src/common/Utils.h \ src/common/TlmRecorder.h \ src/common/tlm2_base_protocol_checker.h \ src/common/protocol.h \ - src/common/dramExtension.h \ src/common/DebugManager.h \ src/controller/core/configuration/Configuration.h \ src/controller/core/powerdown/PowerDownManagerTimeout.h \ @@ -177,7 +175,6 @@ HEADERS += \ src/controller/core/scheduling/checker/ActBChecker.h \ src/controller/core/scheduling/Trigger.h \ src/controller/core/scheduling/ScheduledCommand.h \ - src/controller/core/TimingCalculation.h \ src/controller/core/Slots.h \ src/controller/core/ControllerCore.h \ src/simulation/TracePlayer.h \ @@ -221,7 +218,10 @@ HEADERS += \ src/simulation/RecordableDram.h \ src/common/AddressDecoder.h \ src/common/CongenAddressDecoder.h \ - src/common/XmlAddressDecoder.h + src/common/XmlAddressDecoder.h \ + src/common/rename_utils.h \ + src/controller/core/timingCalculations.h \ + src/common/dramExtensions.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.cpp b/DRAMSys/library/src/common/CongenAddressDecoder.cpp index 6d71e39b..8ca2ce74 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.cpp +++ b/DRAMSys/library/src/common/CongenAddressDecoder.cpp @@ -34,7 +34,7 @@ */ #include "CongenAddressDecoder.h" -#include "Utils.h" +#include "rename_utils.h" #include diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index be40527b..f3810dee 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -34,13 +34,13 @@ * Matthias Jung */ -#ifndef DEBUGMANAGER_H_ -#define DEBUGMANAGER_H_ +#ifndef DEBUGMANAGER_H +#define DEBUGMANAGER_H #include #include #include -#include "Utils.h" +#include "rename_utils.h" class DebugManager { @@ -63,4 +63,4 @@ private: ofstream debugFile; }; -#endif /* DEBUGMANAGER_H_ */ +#endif // DEBUGMANAGER_H diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index f32ec20f..c365c060 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -41,7 +41,7 @@ #include "TlmRecorder.h" #include "protocol.h" -#include "dramExtension.h" +#include "dramExtensions.h" #include "XmlAddressDecoder.h" #include "../controller/core/configuration/Configuration.h" #include "../controller/Controller.h" diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index f6b97c91..8b8ef016 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -36,8 +36,8 @@ * Eder F. Zulian */ -#ifndef TLMPHASERECORDER_H -#define TLMPHASERECORDER_H +#ifndef TLMRECORDER_H +#define TLMRECORDER_H #include #include @@ -51,7 +51,7 @@ #include #include "XmlAddressDecoder.h" #include "DebugManager.h" -#include "Utils.h" +#include "rename_utils.h" using namespace std; @@ -150,5 +150,5 @@ private: insertDebugMessageString, updateDataStrobeString, insertPowerString; }; -#endif +#endif // TLMRECORDER_H diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 1f487f65..caa49062 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -37,7 +37,7 @@ #include "XmlAddressDecoder.h" #include -#include "Utils.h" +#include "rename_utils.h" #include "bitset" #include "../controller/core/configuration/Configuration.h" diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.h b/DRAMSys/library/src/common/XmlAddressDecoder.h index 6f87bcd5..488eb4a7 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.h +++ b/DRAMSys/library/src/common/XmlAddressDecoder.h @@ -35,12 +35,12 @@ * Matthias Jung */ -#ifndef _XMLADDRESSDECODER_H -#define _XMLADDRESSDECODER_H +#ifndef XMLADDRESSDECODER_H +#define XMLADDRESSDECODER_H #include -#include "Utils.h" +#include "rename_utils.h" #include "third_party/tinyxml2/tinyxml2.h" #include "AddressDecoder.h" @@ -71,4 +71,4 @@ public: virtual void print(); }; -#endif +#endif // XMLADDRESSDECODER_H diff --git a/DRAMSys/library/src/common/dramExtension.cpp b/DRAMSys/library/src/common/dramExtensions.cpp similarity index 99% rename from DRAMSys/library/src/common/dramExtension.cpp rename to DRAMSys/library/src/common/dramExtensions.cpp index bfb7b7c4..51ee8578 100644 --- a/DRAMSys/library/src/common/dramExtension.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -35,10 +35,10 @@ * Matthias Jung */ -#include "dramExtension.h" +#include "dramExtensions.h" #include "../controller/core/configuration/Configuration.h" #include "map" -#include "Utils.h" +#include "rename_utils.h" using namespace tlm; diff --git a/DRAMSys/library/src/common/dramExtension.h b/DRAMSys/library/src/common/dramExtensions.h similarity index 98% rename from DRAMSys/library/src/common/dramExtension.h rename to DRAMSys/library/src/common/dramExtensions.h index c990e912..2f62ab94 100644 --- a/DRAMSys/library/src/common/dramExtension.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef DRAMEXTENSION_H_ -#define DRAMEXTENSION_H_ +#ifndef DRAMEXTENSIONS_H +#define DRAMEXTENSIONS_H #include #include @@ -238,4 +238,4 @@ bool operator!=(const Row &lhs, const Row &rhs); bool operator==(const Column &lhs, const Column &rhs); bool operator!=(const Column &lhs, const Column &rhs); -#endif /* DRAMEXTENSION_H_ */ +#endif // DRAMEXTENSIONS_H diff --git a/DRAMSys/library/src/common/protocol.h b/DRAMSys/library/src/common/protocol.h index 00b03c36..06af9c30 100644 --- a/DRAMSys/library/src/common/protocol.h +++ b/DRAMSys/library/src/common/protocol.h @@ -35,8 +35,8 @@ * Matthias Jung */ -#ifndef EXTENDED_PHASE_DRAM -#define EXTENDED_PHASE_DRAM +#ifndef PROTOCOL_H +#define PROTOCOL_H // DRAM Control Phases DECLARE_EXTENDED_PHASE(BEGIN_PREB); @@ -100,5 +100,5 @@ DECLARE_EXTENDED_PHASE(REF_TRIGGER); DECLARE_EXTENDED_PHASE(PDN_TRIGGER); -#endif +#endif // PROTOCOL_H diff --git a/DRAMSys/library/src/common/Utils.cpp b/DRAMSys/library/src/common/rename_utils.cpp similarity index 99% rename from DRAMSys/library/src/common/Utils.cpp rename to DRAMSys/library/src/common/rename_utils.cpp index 6634201b..9e0c19a8 100644 --- a/DRAMSys/library/src/common/Utils.cpp +++ b/DRAMSys/library/src/common/rename_utils.cpp @@ -35,11 +35,11 @@ * Matthias Jung */ -#include "Utils.h" +#include "rename_utils.h" #include #include #include -#include "dramExtension.h" +#include "dramExtensions.h" #include "../controller/Controller.h" using namespace std; diff --git a/DRAMSys/library/src/common/Utils.h b/DRAMSys/library/src/common/rename_utils.h similarity index 97% rename from DRAMSys/library/src/common/Utils.h rename to DRAMSys/library/src/common/rename_utils.h index ac7a71a1..79bf1c5b 100644 --- a/DRAMSys/library/src/common/Utils.h +++ b/DRAMSys/library/src/common/rename_utils.h @@ -35,8 +35,8 @@ * Eder F. Zulian */ -#ifndef UTILS_COMMON_UTILS_H_ -#define UTILS_COMMON_UTILS_H_ +#ifndef UTILS_H +#define UTILS_H #include #include @@ -44,7 +44,7 @@ #include #include #include -#include "dramExtension.h" +#include "dramExtensions.h" #include "third_party/tinyxml2/tinyxml2.h" #define DEF_SINGLETON( NAME ) \ @@ -148,5 +148,5 @@ double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name); void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank); -#endif /* UTILS_COMMON_H_ */ +#endif // UTILS_H diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index da66fef4..c2b87464 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -33,8 +33,8 @@ * Janik Schlemminger * Matthias Jung */ -#ifndef COMMAND_H_ -#define COMMAND_H_ +#ifndef COMMAND_H +#define COMMAND_H #include #include @@ -64,4 +64,4 @@ std::string commandToString(Command command); const std::vector &getAllCommands(); bool commandIsIn(Command command, std::vector commands); -#endif /* COMMAND_H_ */ +#endif // COMMAND_H diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 3b604c63..0a743632 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -35,8 +35,8 @@ * Eder F. Zulian */ -#ifndef CONTROLLERWRAPPER_H_ -#define CONTROLLERWRAPPER_H_ +#ifndef CONTROLLER_H +#define CONTROLLER_H #include #include @@ -49,11 +49,11 @@ #include #include -#include "../common/dramExtension.h" +#include "../common/dramExtensions.h" #include "../common/DebugManager.h" #include "../common/protocol.h" #include "../common/TlmRecorder.h" -#include "../common/Utils.h" +#include "../common/rename_utils.h" #include "core/configuration/Configuration.h" #include "core/configuration/MemSpec.h" #include "Command.h" @@ -63,7 +63,7 @@ #include "core/powerdown/IPowerDownManager.h" #include "core/scheduling/ScheduledCommand.h" #include "core/scheduling/Trigger.h" -#include "core/TimingCalculation.h" +#include "core/timingCalculations.h" #include "scheduler/Fifo.h" #include "scheduler/Grp.h" #include "scheduler/FifoStrict.h" @@ -171,5 +171,5 @@ protected: static const unsigned int controllerThreadId = INT_MAX; }; -#endif /* CONTROLLERWRAPPER_H_ */ +#endif // CONTROLLER_H diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index efff0548..a94905f8 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -37,7 +37,7 @@ #include "ControllerState.h" #include -#include "core/TimingCalculation.h" +#include "core/timingCalculations.h" using namespace std; diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index fff61882..77b99799 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef CONTROLLER_STATE_H_ -#define CONTROLLER_STATE_H_ +#ifndef CONTROLLERSTATE_H +#define CONTROLLERSTATE_H #include #include "RowBufferStates.h" @@ -84,5 +84,5 @@ private: void printDebugMessage(std::string message); }; -#endif /* CONTROLLER_STATE_H_ */ +#endif // CONTROLLERSTATE_H diff --git a/DRAMSys/library/src/controller/IController.h b/DRAMSys/library/src/controller/IController.h index ded2de7b..4504c4c3 100644 --- a/DRAMSys/library/src/controller/IController.h +++ b/DRAMSys/library/src/controller/IController.h @@ -42,7 +42,7 @@ #include #include "core/scheduling/ScheduledCommand.h" #include "core/scheduling/Trigger.h" -#include "../common/dramExtension.h" +#include "../common/dramExtensions.h" // Utiliy class to pass around the Controller class to the controller Core and various schedulers, without having to propagate the template defintions diff --git a/DRAMSys/library/src/controller/RowBufferStates.cpp b/DRAMSys/library/src/controller/RowBufferStates.cpp index 2948203a..4c57d257 100644 --- a/DRAMSys/library/src/controller/RowBufferStates.cpp +++ b/DRAMSys/library/src/controller/RowBufferStates.cpp @@ -37,7 +37,7 @@ #include "RowBufferStates.h" #include "core/ControllerCore.h" #include "../common/DebugManager.h" -#include "../common/Utils.h" +#include "../common/rename_utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/RowBufferStates.h b/DRAMSys/library/src/controller/RowBufferStates.h index 63de434e..f2670dec 100644 --- a/DRAMSys/library/src/controller/RowBufferStates.h +++ b/DRAMSys/library/src/controller/RowBufferStates.h @@ -34,11 +34,11 @@ * Matthias Jung */ -#ifndef ROWBUFFERSTATES_H_ -#define ROWBUFFERSTATES_H_ +#ifndef ROWBUFFERSTATES_H +#define ROWBUFFERSTATES_H #include -#include "../common/dramExtension.h" +#include "../common/dramExtensions.h" class RowBufferState { @@ -60,5 +60,5 @@ private: void printDebugMessage(std::string message); }; -#endif /* BANKSTATES_H_ */ +#endif // ROWBUFFERSTATES_H diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index ba8d1ebe..92dfe1a1 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -49,9 +49,9 @@ #include "refresh/RefreshManagerBankwise.h" #include "refresh/RefreshManager.h" #include "refresh/RGR.h" -#include "../../common/dramExtension.h" -#include "../../common/Utils.h" -#include "TimingCalculation.h" +#include "../../common/dramExtensions.h" +#include "../../common/rename_utils.h" +#include "timingCalculations.h" #include "powerdown/PowerDownManager.h" #include "powerdown/PowerDownManagerTimeout.h" diff --git a/DRAMSys/library/src/controller/core/ControllerCore.h b/DRAMSys/library/src/controller/core/ControllerCore.h index 7b00f1ea..f0b7dc99 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.h +++ b/DRAMSys/library/src/controller/core/ControllerCore.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef CONTROLLER_H_ -#define CONTROLLER_H_ +#ifndef CONTROLLERCORE_H +#define CONTROLLERCORE_H #include #include @@ -88,5 +88,5 @@ private: void printDebugMessage(string message); }; -#endif /* CONTROLLER_H_ */ +#endif // CONTROLLERCORE_H diff --git a/DRAMSys/library/src/controller/core/Slots.cpp b/DRAMSys/library/src/controller/core/Slots.cpp index 20126eab..d74ce9e9 100644 --- a/DRAMSys/library/src/controller/core/Slots.cpp +++ b/DRAMSys/library/src/controller/core/Slots.cpp @@ -35,7 +35,7 @@ */ #include "Slots.h" -#include "TimingCalculation.h" +#include "timingCalculations.h" Slots::Slots(sc_time clk) : diff --git a/DRAMSys/library/src/controller/core/Slots.h b/DRAMSys/library/src/controller/core/Slots.h index 5a821a4b..61663568 100644 --- a/DRAMSys/library/src/controller/core/Slots.h +++ b/DRAMSys/library/src/controller/core/Slots.h @@ -34,13 +34,13 @@ * Matthias Jung */ -#ifndef SLOTS_H_ -#define SLOTS_H_ +#ifndef SLOTS_H +#define SLOTS_H + #include #include #include "scheduling/ScheduledCommand.h" - class Slots { public: @@ -60,4 +60,4 @@ private: }; -#endif /* SLOTS_H_ */ +#endif // SLOTS_H diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index 37b7f4ea..6472a4c5 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -36,15 +36,15 @@ * Felipe S. Prado */ -#ifndef CONFIGURATION_H_ -#define CONFIGURATION_H_ +#ifndef CONFIGURATION_H +#define CONFIGURATION_H #include #include #include #include "MemSpec.h" #include "thermalSimConfig.h" -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" #include "../../../error/eccbaseclass.h" @@ -164,5 +164,5 @@ private: unsigned int powerDownTimeoutInClk = 3; }; -#endif /* CONFIGURATION_H_ */ +#endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 31f478b7..a8fb37c8 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -36,7 +36,7 @@ #include "ConfigurationLoader.h" #include "MemSpec.h" -#include "../TimingCalculation.h" +#include "../timingCalculations.h" using namespace tinyxml2; using namespace std; diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h index 8334cb4e..fe701b59 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h @@ -34,12 +34,12 @@ * Matthias Jung */ -#ifndef CONFIGURATIONLOADER_H_ -#define CONFIGURATIONLOADER_H_ +#ifndef CONFIGURATIONLOADER_H +#define CONFIGURATIONLOADER_H #include #include "../../../common/third_party/tinyxml2/tinyxml2.h" -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" #include "Configuration.h" class ConfigurationLoader @@ -74,4 +74,4 @@ private: }; -#endif /* CONFIGURATIONLOADER_H_ */ +#endif // CONFIGURATIONLOADER_H diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 434cb508..79b10329 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -39,7 +39,7 @@ #include #include -#include "../../../common/dramExtension.h" +#include "../../../common/dramExtensions.h" struct RefreshTiming { diff --git a/DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h b/DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h index 6d202dbc..8d13a77d 100644 --- a/DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h +++ b/DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h @@ -43,7 +43,7 @@ #include "../../../common/DebugManager.h" #include "../../../common/third_party/tinyxml2/tinyxml2.h" -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" struct TemperatureSimConfig { diff --git a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h index 1de77427..9ff8bd39 100644 --- a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h +++ b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h @@ -34,11 +34,11 @@ * Matthias Jung */ -#ifndef IPOWERDOWNMANAGER_H_ -#define IPOWERDOWNMANAGER_H_ +#ifndef IPOWERDOWNMANAGER_H +#define IPOWERDOWNMANAGER_H #include -#include "../../../common/dramExtension.h" +#include "../../../common/dramExtensions.h" #include "../../Command.h" @@ -126,4 +126,4 @@ inline std::string powerDownStateToString(PowerDownState powerDownState) } -#endif /* IPOWERDOWNMANAGER_H_ */ +#endif // IPOWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h index 13b9db16..e68d344a 100644 --- a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h +++ b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h @@ -40,7 +40,7 @@ #include "PowerDownManager.h" #include -#include "../../../common/dramExtension.h" +#include "../../../common/dramExtensions.h" #include "../scheduling/ScheduledCommand.h" diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp index 93cab1a6..9d3a5258 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp @@ -39,10 +39,10 @@ #include #include "PowerDownManager.h" #include "../ControllerCore.h" -#include "../TimingCalculation.h" +#include "../timingCalculations.h" #include "../../../common/DebugManager.h" #include -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" using namespace tlm; using namespace std; diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h index a8a77e20..ee90629e 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef POWERDOWNMANAGER_H_ -#define POWERDOWNMANAGER_H_ +#ifndef POWERDOWNMANAGER_H +#define POWERDOWNMANAGER_H #include "PowerDownManagerBankwise.h" @@ -68,4 +68,4 @@ protected: }; -#endif /* POWERDOWNMANAGER_H_ */ +#endif // POWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp index 57490c88..344b1700 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp @@ -36,9 +36,9 @@ #include "PowerDownManager.h" #include "../ControllerCore.h" -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" #include "../../../common/DebugManager.h" -#include "../TimingCalculation.h" +#include "../timingCalculations.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h index 5f532b00..69382538 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h @@ -34,15 +34,15 @@ * Matthias Jung */ -#ifndef POWERDOWNMANAGERBANKWISE_H_ -#define POWERDOWNMANAGERBANKWISE_H_ +#ifndef POWERDOWNMANAGERBANKWISE_H +#define POWERDOWNMANAGERBANKWISE_H #include #include #include #include #include "../../Command.h" -#include "../../../common/dramExtension.h" +#include "../../../common/dramExtensions.h" #include "../scheduling/ScheduledCommand.h" #include "IPowerDownManager.h" @@ -82,5 +82,5 @@ protected: void printDebugMessage(std::string message); }; -#endif /* POWERDOWNMANAGERBANKWISE_H_ */ +#endif // POWERDOWNMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp index c694d13f..88a97766 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp @@ -38,9 +38,9 @@ #include "PowerDownManagerTimeout.h" #include "../ControllerCore.h" -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" #include "../../../common/DebugManager.h" -#include "../TimingCalculation.h" +#include "../timingCalculations.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h index 538df00c..d56675f5 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h @@ -36,12 +36,12 @@ * Felipe S. Prado */ -#ifndef POWERDOWNMANAGERTIMEOUT_H_ -#define POWERDOWNMANAGERTIMEOUT_H_ +#ifndef POWERDOWNMANAGERTIMEOUT_H +#define POWERDOWNMANAGERTIMEOUT_H #include "PowerDownManager.h" #include -#include "../../../common/dramExtension.h" +#include "../../../common/dramExtensions.h" #include "../scheduling/ScheduledCommand.h" #include @@ -60,4 +60,4 @@ public: -#endif /* POWERDOWNMANAGERTIMEOUT_H_ */ +#endif // POWERDOWNMANAGERTIMEOUT_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp index 56a8b9b3..2e4a2a1a 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp @@ -38,9 +38,9 @@ #include "PowerDownManagerTimeoutBankwise.h" #include "../ControllerCore.h" -#include "../../../common/Utils.h" +#include "../../../common/rename_utils.h" #include "../../../common/DebugManager.h" -#include "../TimingCalculation.h" +#include "../timingCalculations.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h index 3c1fb76b..e4a43bed 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h @@ -36,12 +36,12 @@ * Felipe S. Prado */ -#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H_ -#define POWERDOWNMANAGERTIMEOUTBANKWISE_H_ +#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H +#define POWERDOWNMANAGERTIMEOUTBANKWISE_H #include "PowerDownManager.h" #include -#include "../../../common/dramExtension.h" +#include "../../../common/dramExtensions.h" #include "../scheduling/ScheduledCommand.h" #include @@ -60,4 +60,4 @@ public: -#endif /* POWERDOWNMANAGERTIMEOUTBANKWISE_H_ */ +#endif // POWERDOWNMANAGERTIMEOUTBANKWISE_H diff --git a/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h b/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h index 1668ef61..9b2f581b 100644 --- a/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h +++ b/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h @@ -35,8 +35,8 @@ * Matthias Jung */ -#ifndef IREFRESHMANAGER_H_ -#define IREFRESHMANAGER_H_ +#ifndef IREFRESHMANAGER_H +#define IREFRESHMANAGER_H #include #include "../scheduling/ScheduledCommand.h" @@ -62,5 +62,5 @@ public: virtual bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) = 0; }; -#endif /* IREFRESHMANAGER_H_ */ +#endif // IREFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index 37b552e4..ff4c72e5 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -36,8 +36,8 @@ #include "RGR.h" #include "../ControllerCore.h" -#include "../TimingCalculation.h" -#include "../../../common/Utils.h" +#include "../timingCalculations.h" +#include "../../../common/rename_utils.h" #define TRUE 1 #define FALSE !(TRUE) diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.h b/DRAMSys/library/src/controller/core/refresh/RGR.h index 96ad8cdb..bfe8e444 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.h +++ b/DRAMSys/library/src/controller/core/refresh/RGR.h @@ -32,12 +32,15 @@ * Author: Éder F. Zulian */ -#ifndef RGR_MANAGER_H_ -#define RGR_MANAGER_H_ -#include "../../../common/dramExtension.h" +#ifndef RGR_H +#define RGR_H + +#include "../../../common/dramExtensions.h" #include "../configuration/MemSpec.h" #include "IRefreshManager.h" + class ControllerCore; + class RGR : public IRefreshManager, public sc_module { public: @@ -73,5 +76,6 @@ private: void planNextRefresh(Bank b, sc_time t, bool align); void printDebugMessage(std::string message); }; -#endif /* RGR_MANAGER_H_ */ + +#endif // RGR_H diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index b07ed332..ad1cea5b 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -39,8 +39,8 @@ #include "RefreshManager.h" #include "../ControllerCore.h" -#include "../TimingCalculation.h" -#include "../../../common/Utils.h" +#include "../timingCalculations.h" +#include "../../../common/rename_utils.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h index c5fb5905..c89fa12b 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h @@ -35,8 +35,8 @@ * Éder F. Zulian */ -#ifndef REFRESHMANAGER_H_ -#define REFRESHMANAGER_H_ +#ifndef REFRESHMANAGER_H +#define REFRESHMANAGER_H #include "IRefreshManager.h" #include "../configuration/MemSpec.h" @@ -78,5 +78,5 @@ private: void printDebugMessage(std::string message); }; -#endif /* REFRESHMANAGER_H_ */ +#endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index 533b7859..ab878ff0 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -37,8 +37,8 @@ #include "RefreshManagerBankwise.h" #include "../ControllerCore.h" -#include "../TimingCalculation.h" -#include "../../../common/Utils.h" +#include "../timingCalculations.h" +#include "../../../common/rename_utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h index 6b8558a1..1c84d83e 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h @@ -35,8 +35,8 @@ * Éder F. Zulian */ -#ifndef BANKWISEREFRESHMANAGER_H_ -#define BANKWISEREFRESHMANAGER_H_ +#ifndef BANKWISEREFRESHMANAGER_H +#define BANKWISEREFRESHMANAGER_H //#include "../../../common/dramExtension.h" #include "IRefreshManager.h" @@ -79,5 +79,5 @@ private: void printDebugMessage(std::string message); }; -#endif /* BANKWISEREFRESHMANAGER_H_ */ +#endif // BANKWISEREFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index 3b367eda..718e25f3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -35,8 +35,8 @@ */ #include "ScheduledCommand.h" -#include "../TimingCalculation.h" -#include "../../../common/Utils.h" +#include "../timingCalculations.h" +#include "../../../common/rename_utils.h" #include "../configuration/Configuration.h" bool ScheduledCommand::isNoCommand() const diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h index c2a5a2fc..aa2f1121 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h @@ -34,14 +34,14 @@ * Matthias Jung */ -#ifndef SCHEDULEDCOMMAND_H_ -#define SCHEDULEDCOMMAND_H_ +#ifndef SCHEDULEDCOMMAND_H +#define SCHEDULEDCOMMAND_H #include #include #include "../../Command.h" -#include "../../../common/dramExtension.h" -#include "../../../common/Utils.h" +#include "../../../common/dramExtensions.h" +#include "../../../common/rename_utils.h" class ScheduledCommand { @@ -98,5 +98,5 @@ private: DramExtension extension; }; -#endif /* SCHEDULEDCOMMAND_H_ */ +#endif // SCHEDULEDCOMMAND_H diff --git a/DRAMSys/library/src/controller/core/scheduling/Trigger.h b/DRAMSys/library/src/controller/core/scheduling/Trigger.h index b0026be8..3900bdbe 100644 --- a/DRAMSys/library/src/controller/core/scheduling/Trigger.h +++ b/DRAMSys/library/src/controller/core/scheduling/Trigger.h @@ -34,11 +34,11 @@ * Matthias Jung */ -#ifndef TRIGGER_H_ -#define TRIGGER_H_ +#ifndef TRIGGER_H +#define TRIGGER_H enum Trigger {REFTrigger, PDNTrigger}; -#endif /* TRIGGER_H_ */ +#endif // TRIGGER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index fff23cde..2313d6cb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -36,10 +36,10 @@ #include #include #include "ActBChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" #include "../../../../common/DebugManager.h" #include "../../../Command.h" -#include "../../../../common/Utils.h" +#include "../../../../common/rename_utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h index 0c83d71d..f1a04859 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h @@ -31,8 +31,9 @@ * * Author: Éder F. Zulian */ -#ifndef ACTB_CHECKER_H_ -#define ACTB_CHECKER_H_ + +#ifndef ACTBCHECKER_H +#define ACTBCHECKER_H #include #include "ICommandChecker.h" @@ -56,4 +57,4 @@ private: bool satisfies_nActivateWindow(ScheduledCommand &command) const; }; -#endif /* ACTB_CHECKER_H_ */ +#endif // ACTBCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 2e29c114..51a10ea7 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -38,10 +38,10 @@ #include #include #include "ActivateChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" #include "../../../../common/DebugManager.h" #include "../../../Command.h" -#include "../../../../common/Utils.h" +#include "../../../../common/rename_utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h index ed62f98d..1312505d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef ACTIVATESCHEDULER_H_ -#define ACTIVATESCHEDULER_H_ +#ifndef ACTIVATECHECKER_H +#define ACTIVATECHECKER_H #include #include "ICommandChecker.h" @@ -61,4 +61,4 @@ private: bool satisfies_nActivateWindow(ScheduledCommand &command) const; }; -#endif /* ACTIVATESCHEDULER_H_ */ +#endif // ACTIVATECHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h index 833077cb..3f38f93b 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef ICOMMANDSCHEDULER_H_ -#define ICOMMANDSCHEDULER_H_ +#ifndef ICOMMANDCHECKER_H +#define ICOMMANDCHECKER_H #include #include "../ScheduledCommand.h" @@ -50,4 +50,4 @@ public: -#endif /* ICOMMANDSCHEDULER_H_ */ +#endif // ICOMMANDCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 6b92cd96..7a430ac6 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -36,7 +36,7 @@ */ #include "PowerDownChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h index df7a2a9a..a1b5f53d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef POWERDOWNCHECKER_H_ -#define POWERDOWNCHECKER_H_ +#ifndef POWERDOWNCHECKER_H +#define POWERDOWNCHECKER_H #include @@ -60,5 +60,5 @@ private: Command pdnCmd) const; }; -#endif /* POWERDOWNCHECKER_H_ */ +#endif // POWERDOWNCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 97c8a103..f559bf38 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -33,7 +33,7 @@ */ #include "PreBChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const { sc_assert(cmd.getCommand() == Command::PreB); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h index f37241d9..980901a3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h @@ -31,11 +31,14 @@ * * Author: Éder F. Zulian */ -#ifndef PREB_CHECKER_H_ -#define PREB_CHECKER_H_ + +#ifndef PREBCHECKER_H +#define PREBCHECKER_H + #include "ICommandChecker.h" #include "../../configuration/Configuration.h" #include "../../../ControllerState.h" + class PreBChecker: public ICommandChecker { public: @@ -48,4 +51,5 @@ private: const Configuration &config; ControllerState &state; }; -#endif /* PREB_CHECKER_H_ */ + +#endif // PREBCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 31b5732e..f666408d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -36,7 +36,7 @@ */ #include "PrechargeAllChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand &command) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h index 62e8a0f2..41133b4b 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h @@ -34,14 +34,13 @@ * Matthias Jung */ -#ifndef PRECHARGEALLCHECKER_H_ -#define PRECHARGEALLCHECKER_H_ +#ifndef PRECHARGEALLCHECKER_H +#define PRECHARGEALLCHECKER_H #include "ICommandChecker.h" #include "../../configuration/Configuration.h" #include "../../../ControllerState.h" - class PrechargeAllChecker: public ICommandChecker { public: @@ -62,4 +61,4 @@ private: }; -#endif /* PRECHARGEALLCHECKER_H_ */ +#endif // PRECHARGEALLCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index c51fb2b1..6767be1f 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -35,7 +35,7 @@ */ #include "PrechargeChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand &command) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h index 4977dd55..05b94dc1 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h @@ -34,14 +34,13 @@ * Matthias Jung */ -#ifndef PRECHARGECHECKER_H_ -#define PRECHARGECHECKER_H_ +#ifndef PRECHARGECHECKER_H +#define PRECHARGECHECKER_H #include "ICommandChecker.h" #include "../../configuration/Configuration.h" #include "../../../ControllerState.h" - class PrechargeChecker: public ICommandChecker { public: @@ -57,4 +56,4 @@ private: }; -#endif /* PRECHARGECHECKER_H_ */ +#endif // PRECHARGECHECKER_ diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index b5917e42..f8ea3319 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -35,8 +35,8 @@ */ #include "ReadChecker.h" -#include "../../TimingCalculation.h" -#include "../../../../common/Utils.h" +#include "../../timingCalculations.h" +#include "../../../../common/rename_utils.h" #include "WriteChecker.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h index 1fd31f2b..d9c9cce8 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef READCHECKER_H_ -#define READCHECKER_H_ +#ifndef READCHECKER_H +#define READCHECKER_H #include "ICommandChecker.h" #include "../../configuration/Configuration.h" @@ -65,5 +65,5 @@ private: ScheduledCommand &strobeCommand) const; }; -#endif /* READCHECKER_H_ */ +#endif // READCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index f7d110f0..aad23f4a 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -36,7 +36,7 @@ */ #include "RefreshChecker.h" -#include "../../TimingCalculation.h" +#include "../../timingCalculations.h" void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h index 1dd8655d..919531da 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h @@ -34,15 +34,14 @@ * Matthias Jung */ -#ifndef REFRESHCHECKER_H_ -#define REFRESHCHECKER_H_ +#ifndef REFRESHCHECKER_H +#define REFRESHCHECKER_H #include "ICommandChecker.h" #include "../../../ControllerState.h" #include "../../configuration/Configuration.h" #include - class RefreshChecker: public ICommandChecker { public: @@ -64,4 +63,4 @@ private: }; -#endif /* REFRESHCHECKER_H_ */ +#endif // REFRESHCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index 226d24aa..d793041b 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -35,8 +35,8 @@ */ #include "WriteChecker.h" -#include "../../TimingCalculation.h" -#include "../../../../common/Utils.h" +#include "../../timingCalculations.h" +#include "../../../../common/rename_utils.h" #include "ReadChecker.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h index 5b8c46f8..fa7eafba 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h @@ -34,14 +34,13 @@ * Matthias Jung */ -#ifndef WRITECHECKER_H_ -#define WRITECHECKER_H_ +#ifndef WRITECHECKER_H +#define WRITECHECKER_H #include "ICommandChecker.h" #include "../../configuration/Configuration.h" #include "../../../ControllerState.h" - class WriteChecker: public ICommandChecker { public: @@ -64,4 +63,4 @@ private: }; -#endif /* WRITECHECKER_H_ */ +#endif // WRITECHECKER_H diff --git a/DRAMSys/library/src/controller/core/TimingCalculation.cpp b/DRAMSys/library/src/controller/core/timingCalculations.cpp similarity index 98% rename from DRAMSys/library/src/controller/core/TimingCalculation.cpp rename to DRAMSys/library/src/controller/core/timingCalculations.cpp index 224fd7b1..6a94cbc0 100644 --- a/DRAMSys/library/src/controller/core/TimingCalculation.cpp +++ b/DRAMSys/library/src/controller/core/timingCalculations.cpp @@ -34,12 +34,12 @@ * Matthias Jung */ -#include "TimingCalculation.h" +#include "timingCalculations.h" #include "configuration/MemSpec.h" #include "ControllerCore.h" #include "../../common/DebugManager.h" #include "configuration/Configuration.h" -#include "../../common/Utils.h" +#include "../../common/rename_utils.h" diff --git a/DRAMSys/library/src/controller/core/TimingCalculation.h b/DRAMSys/library/src/controller/core/timingCalculations.h similarity index 94% rename from DRAMSys/library/src/controller/core/TimingCalculation.h rename to DRAMSys/library/src/controller/core/timingCalculations.h index 03fa1918..7a938f8b 100644 --- a/DRAMSys/library/src/controller/core/TimingCalculation.h +++ b/DRAMSys/library/src/controller/core/timingCalculations.h @@ -34,12 +34,12 @@ * Matthias Jung */ -#ifndef UTILS_H_ -#define UTILS_H_ +#ifndef TIMINGCALCULATIONS_H +#define TIMINGCALCULATIONS_H #include #include -#include "../../common/dramExtension.h" +#include "../../common/dramExtensions.h" #include "../Command.h" @@ -56,4 +56,4 @@ const sc_time clkAlign(sc_time time, Alignment alignment = UP); bool isClkAligned(sc_time time, sc_time clk); const sc_time FrequencyToClk(double frequencyMhz); -#endif /* UTILS_H_ */ +#endif // TIMINGCALCULATIONS_H diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.h b/DRAMSys/library/src/controller/scheduler/Fifo.h index 14a9f34c..83f14124 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.h +++ b/DRAMSys/library/src/controller/scheduler/Fifo.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef FIFO_H_ -#define FIFO_H_ +#ifndef FIFO_H +#define FIFO_H #include #include @@ -60,4 +60,4 @@ private: std::map> buffer; }; -#endif /* FIFO_H_ */ +#endif // FIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.h b/DRAMSys/library/src/controller/scheduler/FifoStrict.h index 4adf3990..2cf8c3dd 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.h +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.h @@ -65,5 +65,5 @@ private: std::deque> buffer; }; -#endif /* FIFOSTRICT_H */ +#endif // FIFOSTRICT_H diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp index c51b9192..6aefbe29 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp @@ -36,7 +36,7 @@ */ #include "FrFcfs.h" -#include "../../common/dramExtension.h" +#include "../../common/dramExtensions.h" #include "../core/configuration/Configuration.h" #include diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.h b/DRAMSys/library/src/controller/scheduler/FrFcfs.h index ea8d250e..92fd34f3 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.h @@ -35,8 +35,8 @@ * Matthias Jung */ -#ifndef FRFCFS_H_ -#define FRFCFS_H_ +#ifndef FRFCFS_H +#define FRFCFS_H #include "IScheduler.h" #include "../core/ControllerCore.h" @@ -63,4 +63,4 @@ private: }; -#endif // FRFCFS_H_ +#endif // FRFCFS_H diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.h b/DRAMSys/library/src/controller/scheduler/IScheduler.h index 0b0cf0f5..80b6debd 100644 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.h +++ b/DRAMSys/library/src/controller/scheduler/IScheduler.h @@ -40,7 +40,7 @@ #include -#include "../../common/dramExtension.h" +#include "../../common/dramExtensions.h" #include "../Command.h" #include "../core/ControllerCore.h" diff --git a/DRAMSys/library/src/controller/scheduler/SMS.h b/DRAMSys/library/src/controller/scheduler/SMS.h index d60c033a..4019836b 100644 --- a/DRAMSys/library/src/controller/scheduler/SMS.h +++ b/DRAMSys/library/src/controller/scheduler/SMS.h @@ -7,7 +7,7 @@ #include "IScheduler.h" #include "../core/ControllerCore.h" #include "../core/configuration/Configuration.h" -#include "../../common/dramExtension.h" +#include "../../common/dramExtensions.h" #include "../../common/DebugManager.h" #define LOW_SYSTEM_LOAD 16 diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 86d1d1c9..672862c8 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -35,8 +35,8 @@ * Eder F. Zulian */ -#ifndef ARBITER_H_ -#define ARBITER_H_ +#ifndef ARBITER_H +#define ARBITER_H #include #include @@ -47,8 +47,8 @@ #include #include #include "../common/XmlAddressDecoder.h" -#include "../common/dramExtension.h" -#include "../controller/core/TimingCalculation.h" +#include "../common/dramExtensions.h" +#include "../controller/core/timingCalculations.h" #include "../controller/core/configuration/ConfigurationLoader.h" using namespace std; @@ -102,4 +102,4 @@ private: void printDebugMessage(std::string message); }; -#endif /* ARBITER_H_ */ +#endif // ARBITER_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 1e3e5d1b..a01a1cc8 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -50,7 +50,7 @@ #include "../common/CongenAddressDecoder.h" #include "../controller/core/ControllerCore.h" #include "../controller/core/configuration/ConfigurationLoader.h" -#include "../common/Utils.h" +#include "../common/rename_utils.h" #include "../simulation/TemperatureController.h" #include "../controller/Controller.h" #include "../error/ecchamming.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 774e60d3..a2fead62 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -36,8 +36,8 @@ * Felipe S. Prado */ -#ifndef DRAMSYS_H_ -#define DRAMSYS_H_ +#ifndef DRAMSYS_H +#define DRAMSYS_H #include #include @@ -108,4 +108,4 @@ private: void setupDebugManager(const string &traceName); }; -#endif /* SIMULATIONMANAGER_H_ */ +#endif // DRAMSYS_H diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 68b3acb0..0c7388d1 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -49,12 +49,12 @@ #include #include #include "../common/DebugManager.h" -#include "../common/dramExtension.h" +#include "../common/dramExtensions.h" #include "../controller/Controller.h" -#include "../controller/core/TimingCalculation.h" +#include "../controller/core/timingCalculations.h" #include "../controller/core/configuration/Configuration.h" #include "../common/protocol.h" -#include "../common/Utils.h" +#include "../common/rename_utils.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../error/errormodel.h" diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 20817be9..6712070d 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -37,8 +37,8 @@ * Felipe S. Prado */ -#ifndef DRAM_H_ -#define DRAM_H_ +#ifndef DRAM_H +#define DRAM_H #include #include @@ -97,5 +97,5 @@ public: void setDramController(Controller *contr); }; -#endif /* DRAM_H_ */ +#endif // DRAM_H diff --git a/DRAMSys/library/src/simulation/ExampleInitiator.h b/DRAMSys/library/src/simulation/ExampleInitiator.h index f8b60b9e..6440d5a7 100644 --- a/DRAMSys/library/src/simulation/ExampleInitiator.h +++ b/DRAMSys/library/src/simulation/ExampleInitiator.h @@ -1,11 +1,11 @@ -#ifndef EXAMPLEINITIATOR -#define EXAMPLEINITIATOR +#ifndef EXAMPLEINITIATOR_H +#define EXAMPLEINITIATOR_H #include #include #include "MemoryManager.h" -#include "../common/dramExtension.h" +#include "../common/dramExtensions.h" #include "TracePlayer.h" using namespace std; @@ -202,4 +202,4 @@ struct ExampleInitiator: sc_module { tlm_utils::peq_with_cb_and_phase m_peq; }; -#endif // EXAMPLEINITIATOR +#endif // EXAMPLEINITIATOR_H diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 88c1231b..5dc93a6a 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef IARBITER_H_ -#define IARBITER_H_ +#ifndef IARBITER_H +#define IARBITER_H #include #include @@ -139,4 +139,4 @@ protected: } }; -#endif /* IARBITER_H_ */ +#endif // IARBITER_H diff --git a/DRAMSys/library/src/simulation/MemoryManager.h b/DRAMSys/library/src/simulation/MemoryManager.h index 8b431ca5..83baa275 100644 --- a/DRAMSys/library/src/simulation/MemoryManager.h +++ b/DRAMSys/library/src/simulation/MemoryManager.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef MEMORYMANAGER_H_ -#define MEMORYMANAGER_H_ +#ifndef MEMORYMANAGER_H +#define MEMORYMANAGER_H #include #include @@ -55,4 +55,4 @@ private: std::vector freePayloads; }; -#endif /* MEMORYMANAGER_H_ */ +#endif // MEMORYMANAGER_H diff --git a/DRAMSys/library/src/simulation/RecordableDram.h b/DRAMSys/library/src/simulation/RecordableDram.h index 669eb3cc..191fc868 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.h +++ b/DRAMSys/library/src/simulation/RecordableDram.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef RECORDABLEDRAM_H_ -#define RECORDABLEDRAM_H_ +#ifndef RECORDABLEDRAM_H +#define RECORDABLEDRAM_H #include "Dram.h" #include "../common/TlmRecorder.h" @@ -74,5 +74,5 @@ private: void recordPower(); }; -#endif /* RECORDABLEDRAM_H_ */ +#endif // RECORDABLEDRAM_H diff --git a/DRAMSys/library/src/simulation/Setup.h b/DRAMSys/library/src/simulation/Setup.h index a8398686..8b8542ce 100644 --- a/DRAMSys/library/src/simulation/Setup.h +++ b/DRAMSys/library/src/simulation/Setup.h @@ -39,7 +39,7 @@ #include #include -#include "../common/Utils.h" +#include "../common/rename_utils.h" #include "TracePlayer.h" #include "StlPlayer.h" diff --git a/DRAMSys/library/src/simulation/SimpleArbiter.h b/DRAMSys/library/src/simulation/SimpleArbiter.h index bc2f7b9e..5434576b 100644 --- a/DRAMSys/library/src/simulation/SimpleArbiter.h +++ b/DRAMSys/library/src/simulation/SimpleArbiter.h @@ -39,8 +39,8 @@ #include "IArbiter.h" #include "../common/XmlAddressDecoder.h" -#include "../common/dramExtension.h" -#include "../controller/core/TimingCalculation.h" +#include "../common/dramExtensions.h" +#include "../controller/core/timingCalculations.h" using namespace std; using namespace tlm; diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index d26dc2d7..3f510d97 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef TEMPERATURE_CONTROLLER_H_ -#define TEMPERATURE_CONTROLLER_H_ +#ifndef TEMPERATURECONTROLLER_H +#define TEMPERATURECONTROLLER_H #include #include @@ -43,7 +43,7 @@ #include #include "../common/DebugManager.h" -#include "../common/Utils.h" +#include "../common/rename_utils.h" #include "../controller/core/configuration/Configuration.h" #ifdef THERMALSIM @@ -152,5 +152,5 @@ private: void printDebugMessage(std::string message); }; -#endif /* TEMPERATURE_CONTROLLER_H_ */ +#endif // TEMPERATURECONTROLLER_H diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index 04d9cc49..3019b6f5 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -86,5 +86,5 @@ private: unsigned int transCounter; }; -#endif +#endif // TRACEGENERATOR_H diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index 5adbd09e..5a34df28 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -36,8 +36,8 @@ * Felipe S. Prado */ -#ifndef TRACEPLAYER_H_ -#define TRACEPLAYER_H_ +#ifndef TRACEPLAYER_H +#define TRACEPLAYER_H #include #include @@ -50,7 +50,7 @@ #include "../controller/core/configuration/Configuration.h" #include "../common/DebugManager.h" #include "../common/XmlAddressDecoder.h" -#include "../controller/core/TimingCalculation.h" +#include "../controller/core/timingCalculations.h" #include "TracePlayerListener.h" using namespace std; @@ -85,4 +85,4 @@ private: bool finished; }; -#endif /* TRACEPLAYER_H_ */ +#endif // TRACEPLAYER_H diff --git a/DRAMSys/library/src/simulation/TraceSetup.h b/DRAMSys/library/src/simulation/TraceSetup.h index 901b6756..c4c39279 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.h +++ b/DRAMSys/library/src/simulation/TraceSetup.h @@ -39,7 +39,7 @@ #include #include -#include "../common/Utils.h" +#include "../common/rename_utils.h" #include "TracePlayer.h" #include "StlPlayer.h" From abcd2a910bfc520450e5363b37d1b02654944ac5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 12 Jun 2019 20:25:38 +0200 Subject: [PATCH 15/30] Renaming files (Commit 2 of 2) --- DRAMSys/library/library.pro | 11 +++-- .../src/common/CongenAddressDecoder.cpp | 2 +- .../library/src/common/CongenAddressDecoder.h | 3 +- DRAMSys/library/src/common/DebugManager.h | 2 +- DRAMSys/library/src/common/TlmRecorder.h | 2 +- .../library/src/common/XmlAddressDecoder.cpp | 2 +- .../library/src/common/XmlAddressDecoder.h | 5 +-- DRAMSys/library/src/common/dramExtensions.cpp | 2 +- DRAMSys/library/src/common/dramExtensions.h | 1 - .../common/{rename_utils.cpp => utils.cpp} | 2 +- .../src/common/{rename_utils.h => utils.h} | 0 DRAMSys/library/src/controller/Command.h | 1 - DRAMSys/library/src/controller/Controller.h | 3 +- DRAMSys/library/src/controller/IController.h | 2 +- .../src/controller/RowBufferStates.cpp | 2 +- .../src/controller/core/ControllerCore.cpp | 2 +- .../core/configuration/Configuration.h | 4 +- .../core/configuration/ConfigurationLoader.h | 2 +- .../controller/core/configuration/MemSpec.h | 7 ++- ...rmalSimConfig.h => TemperatureSimConfig.h} | 12 ++--- .../controller/core/powerdown/NoPowerDown.h | 2 +- .../core/powerdown/PowerDownManager.cpp | 2 +- .../powerdown/PowerDownManagerBankwise.cpp | 2 +- .../powerdown/PowerDownManagerTimeout.cpp | 2 +- .../PowerDownManagerTimeoutBankwise.cpp | 2 +- .../src/controller/core/refresh/RGR.cpp | 2 +- .../core/refresh/RefreshManager.cpp | 2 +- .../core/refresh/RefreshManagerBankwise.cpp | 2 +- .../core/refresh/RefreshManagerBankwise.h | 6 +-- .../core/scheduling/ScheduledCommand.cpp | 2 +- .../core/scheduling/ScheduledCommand.h | 2 +- .../src/controller/core/scheduling/Trigger.h | 44 ------------------- .../core/scheduling/checker/ActBChecker.cpp | 2 +- .../scheduling/checker/ActivateChecker.cpp | 2 +- .../core/scheduling/checker/ReadChecker.cpp | 2 +- .../core/scheduling/checker/RefreshChecker.h | 2 +- .../core/scheduling/checker/WriteChecker.cpp | 2 +- .../core/scheduling/checker/WriteChecker.h | 2 +- .../controller/core/timingCalculations.cpp | 2 +- .../src/controller/core/timingCalculations.h | 1 - .../src/controller/scheduler/IScheduler.h | 1 - DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/DRAMSys.h | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 2 +- .../library/src/simulation/ExampleInitiator.h | 3 +- DRAMSys/library/src/simulation/IArbiter.h | 3 +- DRAMSys/library/src/simulation/Setup.h | 2 +- DRAMSys/library/src/simulation/StlPlayer.h | 3 +- .../src/simulation/TemperatureController.h | 2 +- .../library/src/simulation/TraceGenerator.h | 4 +- DRAMSys/library/src/simulation/TracePlayer.h | 3 +- DRAMSys/library/src/simulation/TraceSetup.h | 2 +- 52 files changed, 66 insertions(+), 115 deletions(-) rename DRAMSys/library/src/common/{rename_utils.cpp => utils.cpp} (99%) rename DRAMSys/library/src/common/{rename_utils.h => utils.h} (100%) rename DRAMSys/library/src/controller/core/configuration/{thermalSimConfig.h => TemperatureSimConfig.h} (96%) delete mode 100644 DRAMSys/library/src/controller/core/scheduling/Trigger.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 2c4050f5..ab7ca602 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -141,9 +141,9 @@ SOURCES += \ src/simulation/Arbiter.cpp \ src/common/CongenAddressDecoder.cpp \ src/common/XmlAddressDecoder.cpp \ - src/common/rename_utils.cpp \ src/controller/core/timingCalculations.cpp \ - src/common/dramExtensions.cpp + src/common/dramExtensions.cpp \ + src/common/utils.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -173,7 +173,6 @@ HEADERS += \ src/controller/core/scheduling/checker/ActivateChecker.h \ src/controller/core/scheduling/checker/PreBChecker.h \ src/controller/core/scheduling/checker/ActBChecker.h \ - src/controller/core/scheduling/Trigger.h \ src/controller/core/scheduling/ScheduledCommand.h \ src/controller/core/Slots.h \ src/controller/core/ControllerCore.h \ @@ -184,7 +183,6 @@ HEADERS += \ src/common/libDRAMPower.h \ src/simulation/ReorderBuffer.h \ src/controller/core/configuration/MemSpec.h \ - src/controller/core/configuration/thermalSimConfig.h \ src/simulation/StlPlayer.h \ src/simulation/TracePlayerListener.h \ src/simulation/TraceGenerator.h \ @@ -219,9 +217,10 @@ HEADERS += \ src/common/AddressDecoder.h \ src/common/CongenAddressDecoder.h \ src/common/XmlAddressDecoder.h \ - src/common/rename_utils.h \ src/controller/core/timingCalculations.h \ - src/common/dramExtensions.h + src/common/dramExtensions.h \ + src/common/utils.h \ + src/controller/core/configuration/TemperatureSimConfig.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.cpp b/DRAMSys/library/src/common/CongenAddressDecoder.cpp index 8ca2ce74..ea11dcbc 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.cpp +++ b/DRAMSys/library/src/common/CongenAddressDecoder.cpp @@ -34,7 +34,7 @@ */ #include "CongenAddressDecoder.h" -#include "rename_utils.h" +#include "utils.h" #include diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.h b/DRAMSys/library/src/common/CongenAddressDecoder.h index e2d210a5..51778ecf 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.h +++ b/DRAMSys/library/src/common/CongenAddressDecoder.h @@ -47,8 +47,7 @@ using std::vector; using std::pair; using std::map; -class CongenAddressDecoder - : private AddressDecoder +class CongenAddressDecoder : private AddressDecoder { // Friendship needed so that the AddressDecoder can access the // constructor of this class to create the object in CreateInstance. diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index f3810dee..dd35b796 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -40,7 +40,7 @@ #include #include #include -#include "rename_utils.h" +#include "utils.h" class DebugManager { diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 8b8ef016..c69ad4f6 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -51,7 +51,7 @@ #include #include "XmlAddressDecoder.h" #include "DebugManager.h" -#include "rename_utils.h" +#include "utils.h" using namespace std; diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index caa49062..f94011d2 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -37,7 +37,7 @@ #include "XmlAddressDecoder.h" #include -#include "rename_utils.h" +#include "utils.h" #include "bitset" #include "../controller/core/configuration/Configuration.h" diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.h b/DRAMSys/library/src/common/XmlAddressDecoder.h index 488eb4a7..dfd65072 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.h +++ b/DRAMSys/library/src/common/XmlAddressDecoder.h @@ -40,12 +40,11 @@ #include -#include "rename_utils.h" +#include "utils.h" #include "third_party/tinyxml2/tinyxml2.h" #include "AddressDecoder.h" -class XmlAddressDecoder - : private AddressDecoder +class XmlAddressDecoder : private AddressDecoder { // Friendship needed so that the AddressDecoder can access the // constructor of this class to create the object in CreateInstance. diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 51ee8578..9a2b9da3 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -38,7 +38,7 @@ #include "dramExtensions.h" #include "../controller/core/configuration/Configuration.h" #include "map" -#include "rename_utils.h" +#include "utils.h" using namespace tlm; diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 2f62ab94..3a4b1a51 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -41,7 +41,6 @@ #include #include - class Thread { public: diff --git a/DRAMSys/library/src/common/rename_utils.cpp b/DRAMSys/library/src/common/utils.cpp similarity index 99% rename from DRAMSys/library/src/common/rename_utils.cpp rename to DRAMSys/library/src/common/utils.cpp index 9e0c19a8..69c6f899 100644 --- a/DRAMSys/library/src/common/rename_utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -35,7 +35,7 @@ * Matthias Jung */ -#include "rename_utils.h" +#include "utils.h" #include #include #include diff --git a/DRAMSys/library/src/common/rename_utils.h b/DRAMSys/library/src/common/utils.h similarity index 100% rename from DRAMSys/library/src/common/rename_utils.h rename to DRAMSys/library/src/common/utils.h diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index c2b87464..e8aa28e7 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -39,7 +39,6 @@ #include #include - enum class Command { NOP, PreB, diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 0a743632..133f10f9 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -53,7 +53,7 @@ #include "../common/DebugManager.h" #include "../common/protocol.h" #include "../common/TlmRecorder.h" -#include "../common/rename_utils.h" +#include "../common/utils.h" #include "core/configuration/Configuration.h" #include "core/configuration/MemSpec.h" #include "Command.h" @@ -62,7 +62,6 @@ #include "IController.h" #include "core/powerdown/IPowerDownManager.h" #include "core/scheduling/ScheduledCommand.h" -#include "core/scheduling/Trigger.h" #include "core/timingCalculations.h" #include "scheduler/Fifo.h" #include "scheduler/Grp.h" diff --git a/DRAMSys/library/src/controller/IController.h b/DRAMSys/library/src/controller/IController.h index 4504c4c3..b61fc0d7 100644 --- a/DRAMSys/library/src/controller/IController.h +++ b/DRAMSys/library/src/controller/IController.h @@ -41,9 +41,9 @@ #include #include #include "core/scheduling/ScheduledCommand.h" -#include "core/scheduling/Trigger.h" #include "../common/dramExtensions.h" +enum Trigger {REFTrigger, PDNTrigger}; // Utiliy class to pass around the Controller class to the controller Core and various schedulers, without having to propagate the template defintions // throughout all classes diff --git a/DRAMSys/library/src/controller/RowBufferStates.cpp b/DRAMSys/library/src/controller/RowBufferStates.cpp index 4c57d257..e47f5298 100644 --- a/DRAMSys/library/src/controller/RowBufferStates.cpp +++ b/DRAMSys/library/src/controller/RowBufferStates.cpp @@ -37,7 +37,7 @@ #include "RowBufferStates.h" #include "core/ControllerCore.h" #include "../common/DebugManager.h" -#include "../common/rename_utils.h" +#include "../common/utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 92dfe1a1..f966c965 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -50,7 +50,7 @@ #include "refresh/RefreshManager.h" #include "refresh/RGR.h" #include "../../common/dramExtensions.h" -#include "../../common/rename_utils.h" +#include "../../common/utils.h" #include "timingCalculations.h" #include "powerdown/PowerDownManager.h" diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index 6472a4c5..bd1e4bfe 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -43,8 +43,8 @@ #include #include #include "MemSpec.h" -#include "thermalSimConfig.h" -#include "../../../common/rename_utils.h" +#include "TemperatureSimConfig.h" +#include "../../../common/utils.h" #include "../../../error/eccbaseclass.h" diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h index fe701b59..c4b77530 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h @@ -39,7 +39,7 @@ #include #include "../../../common/third_party/tinyxml2/tinyxml2.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" #include "Configuration.h" class ConfigurationLoader diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 79b10329..9a5e06d5 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -34,14 +34,13 @@ * Matthias Jung */ -#ifndef MemSpec_H_ -#define MemSpec_H_ +#ifndef MEMSPEC_H +#define MEMSPEC_H #include #include #include "../../../common/dramExtensions.h" - struct RefreshTiming { RefreshTiming() {} RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tRFC2(SC_ZERO_TIME), @@ -165,5 +164,5 @@ struct MemSpec { } }; -#endif /* MemSpec_H_ */ +#endif // MEMSPEC_H diff --git a/DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h b/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h similarity index 96% rename from DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h rename to DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h index 8d13a77d..b9acd733 100644 --- a/DRAMSys/library/src/controller/core/configuration/thermalSimConfig.h +++ b/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h @@ -34,8 +34,8 @@ * Matthias Jung */ -#ifndef THERMALSIM_CONFIG_H -#define THERMALSIM_CONFIG_H +#ifndef TEMPERATURESIMCONFIG_H +#define TEMPERATURESIMCONFIG_H #include #include @@ -43,10 +43,10 @@ #include "../../../common/DebugManager.h" #include "../../../common/third_party/tinyxml2/tinyxml2.h" -#include "../../../common/rename_utils.h" - -struct TemperatureSimConfig { +#include "../../../common/utils.h" +struct TemperatureSimConfig +{ // Temperature Scale std::string TemperatureScale; std::string pathToResources; @@ -132,5 +132,5 @@ struct TemperatureSimConfig { } }; -#endif /* THERMALSIM_CONFIG_H */ +#endif // TEMPERATURESIMCONFIG_H diff --git a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h index e68d344a..19a53403 100644 --- a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h +++ b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h @@ -45,7 +45,7 @@ -class NoPowerDown: public IPowerDownManager +class NoPowerDown : public IPowerDownManager { public: NoPowerDown() {} diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp index 9d3a5258..d5281e05 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp @@ -42,7 +42,7 @@ #include "../timingCalculations.h" #include "../../../common/DebugManager.h" #include -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" using namespace tlm; using namespace std; diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp index 344b1700..a73d7674 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp @@ -36,7 +36,7 @@ #include "PowerDownManager.h" #include "../ControllerCore.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" #include "../../../common/DebugManager.h" #include "../timingCalculations.h" diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp index 88a97766..997e9c37 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp @@ -38,7 +38,7 @@ #include "PowerDownManagerTimeout.h" #include "../ControllerCore.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" #include "../../../common/DebugManager.h" #include "../timingCalculations.h" diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp index 2e4a2a1a..cd743e02 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp @@ -38,7 +38,7 @@ #include "PowerDownManagerTimeoutBankwise.h" #include "../ControllerCore.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" #include "../../../common/DebugManager.h" #include "../timingCalculations.h" diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index ff4c72e5..e7f5b652 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -37,7 +37,7 @@ #include "RGR.h" #include "../ControllerCore.h" #include "../timingCalculations.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" #define TRUE 1 #define FALSE !(TRUE) diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index ad1cea5b..8b4981ec 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -40,7 +40,7 @@ #include "RefreshManager.h" #include "../ControllerCore.h" #include "../timingCalculations.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index ab878ff0..a496ab8e 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -38,7 +38,7 @@ #include "RefreshManagerBankwise.h" #include "../ControllerCore.h" #include "../timingCalculations.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h index 1c84d83e..a4728f4e 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h @@ -35,8 +35,8 @@ * Éder F. Zulian */ -#ifndef BANKWISEREFRESHMANAGER_H -#define BANKWISEREFRESHMANAGER_H +#ifndef REFRESHMANAGERBANKWISE_H +#define REFRESHMANAGERBANKWISE_H //#include "../../../common/dramExtension.h" #include "IRefreshManager.h" @@ -79,5 +79,5 @@ private: void printDebugMessage(std::string message); }; -#endif // BANKWISEREFRESHMANAGER_H +#endif // REFRESHMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index 718e25f3..2945cc74 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -36,7 +36,7 @@ #include "ScheduledCommand.h" #include "../timingCalculations.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" #include "../configuration/Configuration.h" bool ScheduledCommand::isNoCommand() const diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h index aa2f1121..bc4721b7 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h @@ -41,7 +41,7 @@ #include #include "../../Command.h" #include "../../../common/dramExtensions.h" -#include "../../../common/rename_utils.h" +#include "../../../common/utils.h" class ScheduledCommand { diff --git a/DRAMSys/library/src/controller/core/scheduling/Trigger.h b/DRAMSys/library/src/controller/core/scheduling/Trigger.h deleted file mode 100644 index 3900bdbe..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/Trigger.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef TRIGGER_H -#define TRIGGER_H - - -enum Trigger {REFTrigger, PDNTrigger}; - - -#endif // TRIGGER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 2313d6cb..55edd9a9 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -39,7 +39,7 @@ #include "../../timingCalculations.h" #include "../../../../common/DebugManager.h" #include "../../../Command.h" -#include "../../../../common/rename_utils.h" +#include "../../../../common/utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 51a10ea7..18236ba3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -41,7 +41,7 @@ #include "../../timingCalculations.h" #include "../../../../common/DebugManager.h" #include "../../../Command.h" -#include "../../../../common/rename_utils.h" +#include "../../../../common/utils.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index f8ea3319..048f5cd5 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -36,7 +36,7 @@ #include "ReadChecker.h" #include "../../timingCalculations.h" -#include "../../../../common/rename_utils.h" +#include "../../../../common/utils.h" #include "WriteChecker.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h index 919531da..ae7a4c9e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h @@ -42,7 +42,7 @@ #include "../../configuration/Configuration.h" #include -class RefreshChecker: public ICommandChecker +class RefreshChecker : public ICommandChecker { public: RefreshChecker(const Configuration &config, ControllerState &state) : diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index d793041b..b2aed2d2 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -36,7 +36,7 @@ #include "WriteChecker.h" #include "../../timingCalculations.h" -#include "../../../../common/rename_utils.h" +#include "../../../../common/utils.h" #include "ReadChecker.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h index fa7eafba..4bddeb69 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h @@ -41,7 +41,7 @@ #include "../../configuration/Configuration.h" #include "../../../ControllerState.h" -class WriteChecker: public ICommandChecker +class WriteChecker : public ICommandChecker { public: WriteChecker(const Configuration &config, diff --git a/DRAMSys/library/src/controller/core/timingCalculations.cpp b/DRAMSys/library/src/controller/core/timingCalculations.cpp index 6a94cbc0..2f4b65cb 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.cpp +++ b/DRAMSys/library/src/controller/core/timingCalculations.cpp @@ -39,7 +39,7 @@ #include "ControllerCore.h" #include "../../common/DebugManager.h" #include "configuration/Configuration.h" -#include "../../common/rename_utils.h" +#include "../../common/utils.h" diff --git a/DRAMSys/library/src/controller/core/timingCalculations.h b/DRAMSys/library/src/controller/core/timingCalculations.h index 7a938f8b..e9f80d4e 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.h +++ b/DRAMSys/library/src/controller/core/timingCalculations.h @@ -42,7 +42,6 @@ #include "../../common/dramExtensions.h" #include "../Command.h" - sc_time getMinExecutionTimeForPowerDownCmd(Command command); sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload); diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.h b/DRAMSys/library/src/controller/scheduler/IScheduler.h index 80b6debd..b40f29ec 100644 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.h +++ b/DRAMSys/library/src/controller/scheduler/IScheduler.h @@ -38,7 +38,6 @@ #ifndef ISCHEDULER_H #define ISCHEDULER_H - #include #include "../../common/dramExtensions.h" #include "../Command.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index a01a1cc8..46be1af4 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -50,7 +50,7 @@ #include "../common/CongenAddressDecoder.h" #include "../controller/core/ControllerCore.h" #include "../controller/core/configuration/ConfigurationLoader.h" -#include "../common/rename_utils.h" +#include "../common/utils.h" #include "../simulation/TemperatureController.h" #include "../controller/Controller.h" #include "../error/ecchamming.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index a2fead62..288820e8 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -53,7 +53,7 @@ #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" -class DRAMSys: public sc_module +class DRAMSys : public sc_module { public: tlm_utils::multi_passthrough_target_socket tSocket; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 0c7388d1..e18f1456 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -54,7 +54,7 @@ #include "../controller/core/timingCalculations.h" #include "../controller/core/configuration/Configuration.h" #include "../common/protocol.h" -#include "../common/rename_utils.h" +#include "../common/utils.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../error/errormodel.h" diff --git a/DRAMSys/library/src/simulation/ExampleInitiator.h b/DRAMSys/library/src/simulation/ExampleInitiator.h index 6440d5a7..7b227709 100644 --- a/DRAMSys/library/src/simulation/ExampleInitiator.h +++ b/DRAMSys/library/src/simulation/ExampleInitiator.h @@ -10,7 +10,8 @@ using namespace std; -struct ExampleInitiator: sc_module { +struct ExampleInitiator : sc_module +{ // TLM-2 socket, defaults to 32-bits wide, base protocol tlm_utils::simple_initiator_socket socket; diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 5dc93a6a..872fd929 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -49,7 +49,8 @@ using namespace std; using namespace tlm; -struct IArbiter: public sc_module { +struct IArbiter : public sc_module +{ public: tlm_utils::multi_passthrough_target_socket tSocket; tlm_utils::multi_passthrough_initiator_socket iSocket; diff --git a/DRAMSys/library/src/simulation/Setup.h b/DRAMSys/library/src/simulation/Setup.h index 8b8542ce..34d064e1 100644 --- a/DRAMSys/library/src/simulation/Setup.h +++ b/DRAMSys/library/src/simulation/Setup.h @@ -39,7 +39,7 @@ #include #include -#include "../common/rename_utils.h" +#include "../common/utils.h" #include "TracePlayer.h" #include "StlPlayer.h" diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index b8b0e9a8..b8e23bbd 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -46,7 +46,8 @@ using namespace std; using namespace tlm; -template class StlPlayer: public TracePlayer +template +class StlPlayer : public TracePlayer { public: StlPlayer(sc_module_name /*name*/, diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index 3f510d97..8d91d56a 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -43,7 +43,7 @@ #include #include "../common/DebugManager.h" -#include "../common/rename_utils.h" +#include "../common/utils.h" #include "../controller/core/configuration/Configuration.h" #ifdef THERMALSIM diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index 3019b6f5..7a1ebec4 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -38,13 +38,13 @@ #ifndef TRACEGENERATOR_H #define TRACEGENERATOR_H - #include "TracePlayer.h" using namespace std; using namespace tlm; -struct TraceGenerator: public TracePlayer { +struct TraceGenerator : public TracePlayer +{ public: TraceGenerator(sc_module_name /*name*/, unsigned int clkMhz, TracePlayerListener *listener) : TracePlayer(listener), transCounter(0) diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index 5a34df28..fbc2e004 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -56,7 +56,8 @@ using namespace std; using namespace tlm; -struct TracePlayer: public sc_module { +struct TracePlayer : public sc_module +{ public: tlm_utils::simple_initiator_socket iSocket; TracePlayer(TracePlayerListener *listener); diff --git a/DRAMSys/library/src/simulation/TraceSetup.h b/DRAMSys/library/src/simulation/TraceSetup.h index c4c39279..49f91049 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.h +++ b/DRAMSys/library/src/simulation/TraceSetup.h @@ -39,7 +39,7 @@ #include #include -#include "../common/rename_utils.h" +#include "../common/utils.h" #include "TracePlayer.h" #include "StlPlayer.h" From 24a8f7f48384b1f73eab36521dc31e87e0adf806 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 13 Jun 2019 23:41:22 +0200 Subject: [PATCH 16/30] Code refactoring. --- DRAMSys/library/src/controller/Controller.cpp | 110 ++++++++++-------- DRAMSys/library/src/controller/Controller.h | 2 +- .../src/controller/core/ControllerCore.cpp | 57 +++++---- .../src/controller/scheduler/FifoStrict.h | 10 +- .../src/controller/scheduler/FrFcfs.cpp | 27 +++-- .../library/src/controller/scheduler/FrFcfs.h | 2 +- 6 files changed, 118 insertions(+), 90 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 242bde35..178c7e69 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -93,7 +93,8 @@ void Controller::send(const ScheduledCommand &command, tlm_phase phase; - switch (command.getCommand()) { + switch (command.getCommand()) + { //TODO: refactor tlm recorder case Command::Read: phase = BEGIN_RD; @@ -108,9 +109,9 @@ void Controller::send(const ScheduledCommand &command, phase = BEGIN_WRA; break; case Command::AutoRefresh: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_REFA; - } else + else phase = BEGIN_REFB; break; case Command::Activate: @@ -129,39 +130,39 @@ void Controller::send(const ScheduledCommand &command, phase = BEGIN_PRE_ALL; break; case Command::PDNA: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_PDNA; - } else + else phase = BEGIN_PDNAB; break; case Command::PDNAX: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = END_PDNA; - } else + else phase = END_PDNAB; break; case Command::PDNP: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_PDNP; - } else + else phase = BEGIN_PDNPB; break; case Command::PDNPX: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = END_PDNP; - } else + else phase = END_PDNPB; break; case Command::SREF: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_SREF; - } else + else phase = BEGIN_SREFB; break; case Command::SREFX: - if (!Configuration::getInstance().BankwiseLogic) { + if (!Configuration::getInstance().BankwiseLogic) phase = END_SREF; - } else + else phase = END_SREFB; break; default: @@ -200,18 +201,23 @@ void Controller::send(Trigger trigger, sc_time time, void Controller::controllerCorePEQCallback(tlm_generic_payload &payload, const tlm_phase &phase) { - if (phase == REF_TRIGGER) { + if (phase == REF_TRIGGER) + { controllerCore->triggerRefresh(payload); - } else if (phase == PDN_TRIGGER) { + } + else if (phase == PDN_TRIGGER) + { controllerCore->powerDownManager->sleep(DramExtension::getExtension( payload).getBank(), sc_time_stamp()); - } else { + } + else + { Bank bank = DramExtension::getBank(payload); sendToDram(payload, phase, SC_ZERO_TIME); - if (phase == BEGIN_RD || phase == BEGIN_WR) { + if (phase == BEGIN_RD || phase == BEGIN_WR) scheduleNextFromScheduler(DramExtension::getBank(payload)); - } else if (phase == BEGIN_REFB) + else if (phase == BEGIN_REFB) printDebugMessage("Entering REFB on bank " + to_string(bank.ID())); else if (phase == BEGIN_REFA) printDebugMessage("Entering REFA"); @@ -242,20 +248,20 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload, { sc_time notDelay = fwDelay; - if (phase == BEGIN_REQ) { + if (phase == BEGIN_REQ) + { notDelay += Configuration::getInstance().memSpec.clk; // Bandwidth IDLE - if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState) { + if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState) endBandwidthIdleCollector(); - } } - else if (phase == END_RESP) { + else if (phase == END_RESP) + { // Bandwidth IDLE // TODO: getTotalNumberOfPayloadsInSystem() == 1 && !idleState ?? - if (getTotalNumberOfPayloadsInSystem() == 1) { + if (getTotalNumberOfPayloadsInSystem() == 1) startBandwidthIdleCollector(); - } } printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + @@ -275,24 +281,26 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, { if (phase == BEGIN_REQ) { - printDebugMessage(string("Payload in system: ") + + printDebugMessage(string("Payloads in system: ") + to_string(getTotalNumberOfPayloadsInSystem())); payload.acquire(); payloadEntersSystem(payload); + // TODO: Different queues: Fifo: queue per bank, FifoStrict: queue per channel if (getTotalNumberOfPayloadsInSystem() > controllerCore->config.MaxNrOfTransactions) { printDebugMessage("##Backpressure: Max number of transactions in system reached"); backpressure = &payload; - return; } - payload.set_response_status(tlm::TLM_OK_RESPONSE); - // tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME) - sendToFrontend(payload, END_REQ, SC_ZERO_TIME); + else + { + payload.set_response_status(tlm::TLM_OK_RESPONSE); + sendToFrontend(payload, END_REQ, SC_ZERO_TIME); + // tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME) - scheduler->storeRequest(&payload); - // TODO: (current position in code) - scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); + scheduler->storeRequest(&payload); + scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); + } } else if (phase == PendingRequest) { @@ -330,15 +338,14 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, void Controller::payloadEntersSystem(tlm_generic_payload &payload) { Bank bank = DramExtension::getExtension(payload).getBank(); - // TODO: first increase numberOfPayloadsInSystem[bank], then printDebugMessage ?? + numberOfPayloadsInSystem[bank]++; printDebugMessage( "Payload enters system on bank " + to_string(bank.ID()) + ". Total number of payloads in Controller: " + to_string(getTotalNumberOfPayloadsInSystem())); - numberOfPayloadsInSystem[bank]++; // Set Start Time for Simulation - // TODO: startTimeSet always false at this point?? - if (startTimeSet == false) { + if (!startTimeSet) + { printDebugMessage("Simulation Timer Start"); startTime = sc_time_stamp() - Configuration::getInstance().memSpec.clk; startTimeSet = true; @@ -359,9 +366,8 @@ void Controller::payloadLeavesSystem(tlm_generic_payload &payload) unsigned int Controller::getTotalNumberOfPayloadsInSystem() { unsigned int sum = 0; - for (Bank bank : controllerCore->getBanks()) { + for (Bank bank : controllerCore->getBanks()) sum += numberOfPayloadsInSystem[bank]; - } return sum; } @@ -374,7 +380,8 @@ void Controller::scheduleNextFromScheduler(Bank bank) bool rescheduled = true; pair nextRequest = scheduler->getNextRequest(bank); - if (nextRequest.second != NULL) { + if (nextRequest.second != NULL) + { schedule(nextRequest.first, *nextRequest.second); } else @@ -398,19 +405,27 @@ void Controller::scheduleNextFromScheduler(Bank bank) pair nextRequest = scheduler->getNextRequest(bank); - if (nextRequest.second != NULL) { + if (nextRequest.second != NULL) + { schedule(nextRequest.first, *nextRequest.second); - } else { + } + else + { gp *pendingRequest = scheduler->getPendingRequest(bank); - if (pendingRequest != NULL) { + if (pendingRequest != NULL) + { //Pending request - if (!rescheduled) { + if (!rescheduled) + { // TODO: never reached, rescheduled is always true rescheduled = true; frontendPEQ.notify(*(pendingRequest), PendingRequest, Configuration::getInstance().memSpec.clk); - } else + } + else + { blocked.push(bank); + } } } } @@ -421,7 +436,8 @@ void Controller::schedule(Command command, gp &payload) { controllerCore->powerDownManager->wakeUp(DramExtension::getBank(payload), sc_time_stamp()); - if (controllerCore->scheduleRequest(command, payload)) { + if (controllerCore->scheduleRequest(command, payload)) + { printDebugMessage("\t-> Next payload was scheduled by core [" + commandToString( command) + "] (unblocked)"); } diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 133f10f9..d3d5490b 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -160,7 +160,7 @@ protected: sc_time idleTime; sc_time endTime; sc_time startTime; - int startTimeSet = false; + bool startTimeSet = false; void startBandwidthIdleCollector(); void endBandwidthIdleCollector(); diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index f966c965..654d0333 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -138,27 +138,27 @@ ControllerCore::~ControllerCore() void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload) { /* Refresh can be disabled for tests purpose */ - if (config.ControllerCoreRefDisable == false) { + if (config.ControllerCoreRefDisable == false) + { sc_time time = sc_time_stamp(); Bank bank = DramExtension::getExtension(payload).getBank(); state->cleanUp(time); if (!refreshManager->isInvalidated(payload, time) - && !powerDownManager->isInSelfRefresh(bank)) { + && !powerDownManager->isInSelfRefresh(bank)) + { printDebugMessage("Triggering refresh on bank " + to_string(bank.ID())); powerDownManager->wakeUpForRefresh(bank, time); //expects PDNA and PDNP to exit without delay bool pdnpToSrefTransition = false; - if (config.PowerDownMode == EPowerDownMode::Staggered) { - pdnpToSrefTransition = state->getLastCommand(Command::PDNPX, - bank).getStart() >= time; - } - if (pdnpToSrefTransition) { + if (config.PowerDownMode == EPowerDownMode::Staggered) + pdnpToSrefTransition = (state->getLastCommand(Command::PDNPX, + bank).getStart() >= time); + if (pdnpToSrefTransition) powerDownManager->sleep(bank, time); - } else { + else refreshManager->scheduleRefresh(payload, time); - } } } } @@ -169,13 +169,17 @@ bool ControllerCore::scheduleRequest(Command command, sc_time start = clkAlign(sc_time_stamp()); state->cleanUp(start); ScheduledCommand scheduledCommand = schedule(command, start, payload); - if (config.ControllerCoreRefDisable) { + if (config.ControllerCoreRefDisable) + { state->change(scheduledCommand); controller.send(scheduledCommand, payload); return true; - } else { + } + else + { if (!((command == Command::Precharge || command == Command::Activate) - && refreshManager->hasCollision(scheduledCommand))) { + && refreshManager->hasCollision(scheduledCommand))) + { state->change(scheduledCommand); controller.send(scheduledCommand, payload); return true; @@ -189,17 +193,17 @@ ScheduledCommand ControllerCore::schedule(Command command, sc_time start, { ControllerCore::printDebugMessage("Scheduling command " + commandToString( command) + " on " + DramExtension::getBank(payload).toString()); - ICommandChecker &checker = getCommandChecker(command); sc_time executionTime = getExecutionTime(command, payload); ScheduledCommand scheduledCommand(command, start, executionTime, DramExtension::getExtension(payload)); - checker.delayToSatisfyConstraints(scheduledCommand); + getCommandChecker(command).delayToSatisfyConstraints(scheduledCommand); return scheduledCommand; } bool ControllerCore::hasPendingRequests() { - for (Bank bank : getBanks()) { + for (Bank bank : getBanks()) + { if (numberOfPayloads[bank] != 0) return true; } @@ -217,22 +221,31 @@ bool ControllerCore::bankIsBusy(Bank bank) ScheduledCommand lastScheduledCommand = state->getLastScheduledCommand(bank); if (lastScheduledCommand.isNoCommand()) + { return false; - else if (lastScheduledCommand.commandIsIn( { Command::Write, Command::Read })) { + } + else if (lastScheduledCommand.commandIsIn({Command::Write, Command::Read})) + { // Read and writes can overlap, so the bank should not be busy during a rd/wr return (time < lastScheduledCommand.getStart()); } - else if (lastScheduledCommand.commandIsIn( { Command::WriteA, Command::ReadA, Command::PreB, Command::Precharge, Command::PrechargeAll, Command::ActB, Command::Activate })) { + else if (lastScheduledCommand.commandIsIn({Command::WriteA, Command::ReadA, Command::PreB, + Command::Precharge, Command::PrechargeAll, + Command::ActB, Command::Activate})) + { return (time < lastScheduledCommand.getEnd()); } - else if (lastScheduledCommand.getCommand() == Command::AutoRefresh) { + else if (lastScheduledCommand.getCommand() == Command::AutoRefresh) + { return (time < lastScheduledCommand.getEnd()); - } else if (lastScheduledCommand.commandIsIn( { Command::SREFX, Command::PDNPX, Command::PDNAX, Command::SREF, Command::PDNP, - Command::PDNA - })) { + } + else if (lastScheduledCommand.commandIsIn({Command::SREFX, Command::PDNPX, Command::PDNAX, + Command::SREF, Command::PDNP, Command::PDNA})) + { return false; } - else { + else + { SC_REPORT_FATAL("Core", "Last command unkown"); return false; } diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.h b/DRAMSys/library/src/controller/scheduler/FifoStrict.h index 2cf8c3dd..5404cb8c 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.h +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.h @@ -51,14 +51,14 @@ class FifoStrict : public IScheduler { public: IController &controller; - FifoStrict(IController &controller, - ControllerCore &controllerCore) : IScheduler(controllerCore), - controller(controller) {} + FifoStrict(IController &controller, ControllerCore &controllerCore) + : IScheduler(controllerCore), controller(controller) {} + virtual ~FifoStrict() {} void storeRequest(gp *payload) override; - std::pair getNextRequest( - Bank bank) override; + std::pair + getNextRequest(Bank bank) override; virtual gp *getPendingRequest(Bank bank) override; private: diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp index 6aefbe29..afa12aa2 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp @@ -70,23 +70,23 @@ void FrFcfs::storeRequest(gp *payload) std::pair FrFcfs::getNextRequest(Bank bank) { // If the bank is empty like Bank0 in the example we do nothing - if (buffer[bank].empty()) { - return pair(Command::NOP, NULL); - } + if (buffer[bank].empty()) + return std::pair(Command::NOP, NULL); // In FR_FCFS row hits have always the highest priority, therefore we search // for row hits. If we find a row hit, we remove the transaction from the // queue and send it to the DRAM. - deque::iterator it = FindRowHit(bank); - if (it != buffer[bank].end()) { + std::deque::iterator it = findRowHit(bank); + if (it != buffer[bank].end()) + { gp *payload = *it; buffer[bank].erase(it); - return pair(getReadWriteCommand(payload), payload); + return std::pair(getReadWriteCommand(payload), payload); } // If there is no row hit, the FR_FCFS takes always the oldest transaction // in the buffer, i.e. the transaction in the front. - return pair(getNextCommand(buffer[bank].front()), + return std::pair(getNextCommand(buffer[bank].front()), buffer[bank].front()); } @@ -97,21 +97,20 @@ std::pair FrFcfs::getNextRequest(Bank bank) // deque container. The past-the-end element is the theoretical element that // would follow the last element in the deque container. It does not point to // any element, and thus shall not be dereferenced. -deque::iterator FrFcfs::FindRowHit(Bank bank) +std::deque::iterator FrFcfs::findRowHit(Bank bank) { - deque &queue = buffer[bank]; + std::deque &queue = buffer[bank]; + Row activeRow = controllerCore.getRowBufferStates().getRowInRowBuffer(bank); if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) return queue.end(); // Traverse the scheduling queue of the specific bank: - for (auto it = queue.begin(); it != queue.end(); it++) { - gp *payload = *it; + for (auto it = queue.begin(); it != queue.end(); it++) + { //Found row-hit and return the according iterator - if (DramExtension::getRow(payload) - == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { + if (DramExtension::getRow(*it) == activeRow) return it; - } } return queue.end(); diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.h b/DRAMSys/library/src/controller/scheduler/FrFcfs.h index 92fd34f3..b3fa643b 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.h @@ -57,7 +57,7 @@ public: protected: std::map> buffer; - std::deque::iterator FindRowHit(Bank bank); + std::deque::iterator findRowHit(Bank bank); private: From a97a20b148eedbbd872198c1bd2bf1d0214d1432 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 17 Jun 2019 17:41:46 +0200 Subject: [PATCH 17/30] Added specific MemSpecs, commit not running! --- .../src/controller/core/ControllerCore.cpp | 3 + .../configuration/ConfigurationLoader.cpp | 70 +++++++++++-------- .../controller/core/configuration/MemSpec.h | 66 +++++++++++++---- 3 files changed, 96 insertions(+), 43 deletions(-) diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 654d0333..b1c801a7 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -87,6 +87,8 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, if (config.RowGranularRef) { refreshManager = new RGR("RGR", *this); + // TODO: How to use asserts with new memspec? + /* assert(config.getTrasb() <= config.memSpec.tRAS); assert(config.getTrasb() >= config.memSpec.tRCD); assert(config.getTrrdb_L() <= config.memSpec.tRRD_L); @@ -94,6 +96,7 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, assert(config.getTrpb() <= config.memSpec.tRP); assert(config.getTrcb() <= config.memSpec.tRC); assert(config.getTfawb() <= config.memSpec.tNAW); + */ } else { if (config.BankwiseLogic) { refreshManager = new RefreshManagerBankwise("refManagerBw", *this); diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index a8fb37c8..093479c8 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -101,34 +101,6 @@ void ConfigurationLoader::loadConfigFromUri(Configuration &config, loadConfig(config, e); } -void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) -{ - tinyxml2::XMLDocument doc; - config.memspecUri = memspecUri; - loadXML(memspecUri, doc); - XMLElement *memspec = doc.FirstChildElement("memspec"); - loadMemSpec(config, memspec); -} - -void ConfigurationLoader::loadMemSpec(Configuration &config, - XMLElement *memspec) -{ - config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId"); - config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType"); - - if (config.memSpec.MemoryType == "DDR4") { - loadDDR4(config, memspec); - } else if (config.memSpec.MemoryType == "DDR3") { - loadDDR3(config, memspec); - } else if (config.memSpec.MemoryType == "LPDDR4") { - loadLPDDR4(config, memspec); - } else if (config.memSpec.MemoryType == "WIDEIO_SDR") { - loadWideIO(config, memspec); - } else { - reportFatal("ConfigurationLoader", "Unsupported DRAM type"); - } -} - void ConfigurationLoader::loadMCConfig(Configuration &config, string mcconfigUri) { @@ -155,6 +127,48 @@ void ConfigurationLoader::loadMCConfig(Configuration &config, } +void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) +{ + tinyxml2::XMLDocument doc; + config.memspecUri = memspecUri; + loadXML(memspecUri, doc); + XMLElement *memspec = doc.FirstChildElement("memspec"); + loadMemSpec(config, memspec); +} + +void ConfigurationLoader::loadMemSpec(Configuration &config, + XMLElement *memspec) +{ + config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId"); + config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType"); + + std::cout << "Before" << std::endl; + if (config.memSpec.MemoryType == "DDR4") { + delete(&Configuration::getInstance().memSpec); + Configuration::getInstance().memSpec = + *new MemSpecDDR4; + loadDDR4(config, memspec); + } else if (config.memSpec.MemoryType == "DDR3") { + delete(&Configuration::getInstance().memSpec); + Configuration::getInstance().memSpec = + *new MemSpecDDR3; + loadDDR3(config, memspec); + } else if (config.memSpec.MemoryType == "LPDDR4") { + delete(&Configuration::getInstance().memSpec); + Configuration::getInstance().memSpec = + *new MemSpecLPDDR4; + loadLPDDR4(config, memspec); + } else if (config.memSpec.MemoryType == "WIDEIO_SDR") { + delete(&Configuration::getInstance().memSpec); + Configuration::getInstance().memSpec = + *new MemSpecWideIO; + loadWideIO(config, memspec); + } else { + reportFatal("ConfigurationLoader", "Unsupported DRAM type"); + } + std::cout << "After" << std::endl; +} + void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) { //MemArchitecture diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 9a5e06d5..00a48073 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -41,7 +41,8 @@ #include #include "../../../common/dramExtensions.h" -struct RefreshTiming { +struct RefreshTiming +{ RefreshTiming() {} RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tRFC2(SC_ZERO_TIME), tRFC4(SC_ZERO_TIME), tREFI(tREFI) {} @@ -53,7 +54,8 @@ struct RefreshTiming { sc_time tREFI; }; -struct MemSpec { +struct MemSpec +{ MemSpec() { //default DDR4 @@ -89,24 +91,31 @@ struct MemSpec { // Memspec Variables: double clkMHz; sc_time clk; - sc_time tRP; //precharge-time (pre -> act same bank) + sc_time tRP; //precharge-time (pre -> act same bank + sc_time tRTP; //Read to precharge + sc_time tRCD; //act -> read/write + sc_time tRL; //read latency (read command start to data strobe) + sc_time tWL; //write latency + sc_time tWR; //write recovery (write to precharge) + sc_time tCKESR; //min time in sref + sc_time tCKE; //min time in pdna or pdnp + + sc_time tRFC; //min ref->act delay 1X mode + sc_time tRFC2; //min ref->act delay 2X mode + sc_time tRFC4; //min ref->act delay 4X mode + sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI + + // TODO: move to specific memspecs sc_time tRPAB; //precharge-all time only for LPDDR4 sc_time tRAS; //active-time (act -> pre same bank) sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank) sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd sc_time tCCD_L; - sc_time tRTP; //Read to precharge sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group) sc_time tRRD_L; //.. (same bank group) - sc_time tRCD; //act -> read/write sc_time tNAW; //n activate window - sc_time tRL; //read latency (read command start to data strobe) - sc_time tWL; //write latency - sc_time tWR; //write recovery (write to precharge) sc_time tWTR_S; //write to read (different bank group) sc_time tWTR_L; //.. (same bank group) - sc_time tCKESR; //min time in sref - sc_time tCKE; //min time in pdna or pdnp sc_time tXP; //min delay to row access command after pdnpx pdnax sc_time tXPDLL; //min delay to row access command after pdnpx pdnax for dll commands sc_time tXSR; //min delay to row access command after srefx @@ -114,11 +123,6 @@ struct MemSpec { sc_time tAL; //additive delay (delayed execution in dram) sc_time tDQSCK; - sc_time tRFC; //min ref->act delay 1X mode - sc_time tRFC2; //min ref->act delay 2X mode - sc_time tRFC4; //min ref->act delay 4X mode - sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI - // Currents and Voltages: double iDD0; double iDD02; @@ -164,5 +168,37 @@ struct MemSpec { } }; +struct MemSpecDDR3 : public MemSpec +{ + MemSpecDDR3() + { + std::cout << "Generated MemSpecDDR3" << std::endl; + } +}; + +struct MemSpecDDR4 : public MemSpec +{ + MemSpecDDR4() + { + std::cout << "Generated MemSpecDDR4" << std::endl; + } +}; + +struct MemSpecWideIO : public MemSpec +{ + MemSpecWideIO() + { + std::cout << "Generated MemSpecWideIO" << std::endl; + } +}; + +struct MemSpecLPDDR4 : public MemSpec +{ + MemSpecLPDDR4() + { + std::cout << "Generated MemSpecLPDDR4" << std::endl; + } +}; + #endif // MEMSPEC_H From 7540388cfe33794426b2071d7d677686f03b2928 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 17 Jun 2019 19:31:21 +0200 Subject: [PATCH 18/30] Preparation for specific memspecs (member memSpec is now dynamic). --- DRAMSys/library/src/common/TlmRecorder.cpp | 6 +- .../library/src/common/XmlAddressDecoder.cpp | 4 +- DRAMSys/library/src/common/dramExtensions.cpp | 2 +- DRAMSys/library/src/controller/Controller.cpp | 10 +- .../src/controller/ControllerState.cpp | 14 +- .../library/src/controller/ControllerState.h | 2 +- .../src/controller/RowBufferStates.cpp | 4 +- .../src/controller/core/ControllerCore.cpp | 16 +- .../core/configuration/Configuration.cpp | 26 +- .../core/configuration/Configuration.h | 4 +- .../configuration/ConfigurationLoader.cpp | 528 +++++++++--------- .../core/configuration/ConfigurationLoader.h | 5 +- .../controller/core/configuration/MemSpec.h | 25 +- .../src/controller/core/refresh/RGR.cpp | 8 +- .../core/refresh/RefreshManager.cpp | 8 +- .../core/refresh/RefreshManagerBankwise.cpp | 8 +- .../core/scheduling/ScheduledCommand.cpp | 10 +- .../core/scheduling/checker/ActBChecker.cpp | 30 +- .../scheduling/checker/ActivateChecker.cpp | 32 +- .../scheduling/checker/PowerDownChecker.cpp | 26 +- .../core/scheduling/checker/PreBChecker.cpp | 18 +- .../checker/PrechargeAllChecker.cpp | 28 +- .../scheduling/checker/PrechargeChecker.cpp | 12 +- .../core/scheduling/checker/ReadChecker.cpp | 20 +- .../scheduling/checker/RefreshChecker.cpp | 28 +- .../core/scheduling/checker/WriteChecker.cpp | 14 +- .../controller/core/timingCalculations.cpp | 46 +- .../src/controller/scheduler/FrFcfsGrp.cpp | 4 +- .../library/src/controller/scheduler/Grp.cpp | 4 +- .../library/src/controller/scheduler/SMS.cpp | 2 +- DRAMSys/library/src/error/errormodel.cpp | 10 +- DRAMSys/library/src/simulation/Arbiter.cpp | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 156 +++--- .../library/src/simulation/RecordableDram.cpp | 2 +- .../library/src/simulation/RecordableDram.h | 2 +- DRAMSys/library/src/simulation/StlPlayer.h | 2 +- .../library/src/simulation/TraceGenerator.h | 4 +- 37 files changed, 553 insertions(+), 569 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index c365c060..8619e3ca 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -323,9 +323,9 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 2, simulationTimeCoveredByRecording.value()); sqlite3_bind_int(insertGeneralInfoStatement, 3, - Configuration::getInstance().memSpec.NumberOfBanks); + Configuration::getInstance().memSpec->NumberOfBanks); sqlite3_bind_int(insertGeneralInfoStatement, 4, - Configuration::getInstance().memSpec.clk.value()); + Configuration::getInstance().memSpec->clk.value()); sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, NULL); sqlite3_bind_text(insertGeneralInfoStatement, 6, mcconfig.c_str(), mcconfig.length(), NULL); @@ -337,7 +337,7 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 9, 0); else sqlite3_bind_int64(insertGeneralInfoStatement, 9, - (Configuration::getInstance().memSpec.clk * + (Configuration::getInstance().memSpec->clk * Configuration::getInstance().WindowSize).value()); if (Configuration::getInstance().ControllerCoreRefEnablePostpone || Configuration::getInstance().ControllerCoreRefEnablePullIn) { diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index f94011d2..dfbb4dd8 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -84,8 +84,8 @@ DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) //result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"]; result.bank = (addr & masks["bank"]) >> shifts["bank"]; result.bankgroup = result.bank % - Configuration::getInstance().memSpec.NumberOfBankGroups; - result.rank = result.bank % Configuration::getInstance().memSpec.NumberOfRanks; + Configuration::getInstance().memSpec->NumberOfBankGroups; + result.rank = result.bank % Configuration::getInstance().memSpec->NumberOfRanks; result.row = (addr & masks["row"]) >> shifts["row"]; result.column = (addr & masks["column"]) >> shifts["column"]; result.bytes = (addr & masks["bytes"]) >> shifts["bytes"]; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 9a2b9da3..ed1d0b0d 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -281,7 +281,7 @@ bool operator !=(const Row &lhs, const Row &rhs) const Row Row::operator ++() { - id = (id + 1) % Configuration::getInstance().memSpec.NumberOfRows; + id = (id + 1) % Configuration::getInstance().memSpec->NumberOfRows; return *this; } diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 178c7e69..5e469c8f 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -250,7 +250,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_REQ) { - notDelay += Configuration::getInstance().memSpec.clk; + notDelay += Configuration::getInstance().memSpec->clk; // Bandwidth IDLE if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState) @@ -347,7 +347,7 @@ void Controller::payloadEntersSystem(tlm_generic_payload &payload) if (!startTimeSet) { printDebugMessage("Simulation Timer Start"); - startTime = sc_time_stamp() - Configuration::getInstance().memSpec.clk; + startTime = sc_time_stamp() - Configuration::getInstance().memSpec->clk; startTimeSet = true; } } @@ -392,7 +392,7 @@ void Controller::scheduleNextFromScheduler(Bank bank) { rescheduled = true; frontendPEQ.notify(*(pendingRequest), PendingRequest, - Configuration::getInstance().memSpec.clk); + Configuration::getInstance().memSpec->clk); } } @@ -420,7 +420,7 @@ void Controller::scheduleNextFromScheduler(Bank bank) // TODO: never reached, rescheduled is always true rescheduled = true; frontendPEQ.notify(*(pendingRequest), PendingRequest, - Configuration::getInstance().memSpec.clk); + Configuration::getInstance().memSpec->clk); } else { @@ -579,7 +579,7 @@ void Controller::endBandwidthIdleCollector() { printDebugMessage("IDLE End"); idleTime += sc_time_stamp() - idleStart + - Configuration::getInstance().memSpec.clk; + Configuration::getInstance().memSpec->clk; idleState = false; } diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index a94905f8..c7318363 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -51,7 +51,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command) { ScheduledCommand max; - for (unsigned int i = 0; i < config->memSpec.NumberOfBanks; ++i) { + for (unsigned int i = 0; i < config->memSpec->NumberOfBanks; ++i) { ScheduledCommand current = getLastCommand(command, Bank(i)); if (current.getStart() > max.getStart()) max = current; @@ -65,7 +65,7 @@ const ScheduledCommand ControllerState::getLastScheduledCommand() ScheduledCommand lastCommand; for (Command cmd : getAllCommands()) { - for (Bank bank : Configuration::getInstance().memSpec.getBanks()) { + for (Bank bank : Configuration::getInstance().memSpec->getBanks()) { ScheduledCommand ¤t = lastScheduledByCommandAndBank[cmd][bank]; if (current.getStart() > lastCommand.getStart()) lastCommand = current; @@ -154,17 +154,17 @@ void ControllerState::cleanUp(sc_time time) vector tmp; for (ScheduledCommand &command : lastDataStrobeCommands) { if (command.getEnd() >= time - || getDistance(command.getEnd(), time) <= config->memSpec.tDataStrobeHistory()) + || getDistance(command.getEnd(), time) <= config->memSpec->tDataStrobeHistory()) tmp.push_back(command); } lastDataStrobeCommands = tmp; - if (time >= config->memSpec.tActHistory()) + if (time >= config->memSpec->tActHistory()) lastActivates.erase(lastActivates.begin(), - lastActivates.lower_bound(time - config->memSpec.tActHistory())); + lastActivates.lower_bound(time - config->memSpec->tActHistory())); - if (time >= config->memSpec.tActBHistory()) + if (time >= config->memSpec->tActBHistory()) lastActivatesB.erase(lastActivatesB.begin(), - lastActivatesB.lower_bound(time - config->memSpec.tActBHistory())); + lastActivatesB.lower_bound(time - config->memSpec->tActBHistory())); } void ControllerState::printDebugMessage(std::string message) diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 77b99799..a5d9d609 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -49,7 +49,7 @@ class ControllerState { public: ControllerState(std::string ownerName, - Configuration *config) : bus(config->memSpec.clk), ownerName(ownerName), + Configuration *config) : bus(config->memSpec->clk), ownerName(ownerName), config(config) { rowBufferStates = new RowBufferState(ownerName); diff --git a/DRAMSys/library/src/controller/RowBufferStates.cpp b/DRAMSys/library/src/controller/RowBufferStates.cpp index e47f5298..4db36b8a 100644 --- a/DRAMSys/library/src/controller/RowBufferStates.cpp +++ b/DRAMSys/library/src/controller/RowBufferStates.cpp @@ -76,7 +76,7 @@ void RowBufferState::closeRowBuffer(Bank bank) bool RowBufferState::allRowBuffersAreClosed() const { - for (unsigned int i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks; + for (unsigned int i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; ++i) { if (rowBufferIsOpen(Bank(i))) return false; @@ -86,7 +86,7 @@ bool RowBufferState::allRowBuffersAreClosed() const void RowBufferState::closeAllRowBuffers() { - for (unsigned int i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks; + for (unsigned int i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; ++i) { rowsInRowBuffers[Bank(i)] = Row::NO_ROW; } diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index b1c801a7..5c43afcc 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -89,13 +89,13 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, refreshManager = new RGR("RGR", *this); // TODO: How to use asserts with new memspec? /* - assert(config.getTrasb() <= config.memSpec.tRAS); - assert(config.getTrasb() >= config.memSpec.tRCD); - assert(config.getTrrdb_L() <= config.memSpec.tRRD_L); - assert(config.getTrrdb_S() <= config.memSpec.tRRD_S); - assert(config.getTrpb() <= config.memSpec.tRP); - assert(config.getTrcb() <= config.memSpec.tRC); - assert(config.getTfawb() <= config.memSpec.tNAW); + assert(config.getTrasb() <= config.memSpec->tRAS); + assert(config.getTrasb() >= config.memSpec->tRCD); + assert(config.getTrrdb_L() <= config.memSpec->tRRD_L); + assert(config.getTrrdb_S() <= config.memSpec->tRRD_S); + assert(config.getTrpb() <= config.memSpec->tRP); + assert(config.getTrcb() <= config.memSpec->tRC); + assert(config.getTfawb() <= config.memSpec->tNAW); */ } else { if (config.BankwiseLogic) { @@ -259,7 +259,7 @@ const std::vector &ControllerCore::getBanks() static std::vector banks; if (banks.size() == 0) { - for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; i++) { + for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; i++) { banks.push_back(Bank(i)); } } diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index 52904001..eb0918f3 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -349,10 +349,10 @@ void Configuration::setParameters(std::map std::uint64_t Configuration::getSimMemSizeInBytes() { // 1. Get number of banks, rows, columns and data width in bits for one die (or chip) - std::uint64_t banks = memSpec.NumberOfBanks; - std::uint64_t rows = memSpec.NumberOfRows; - std::uint64_t columns = memSpec.NumberOfColumns; - std::uint64_t bitWidth = memSpec.bitWidth; + std::uint64_t banks = memSpec->NumberOfBanks; + std::uint64_t rows = memSpec->NumberOfRows; + std::uint64_t columns = memSpec->NumberOfColumns; + std::uint64_t bitWidth = memSpec->bitWidth; // 2. Calculate size of one DRAM chip in bits std::uint64_t chipBitSize = banks * rows * columns * bitWidth; // 3. Calculate size of one DRAM chip in bytes @@ -381,7 +381,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() // The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc. unsigned int Configuration::getDataBusWidth() { - unsigned int dataBusWidth = memSpec.bitWidth * NumberOfDevicesOnDIMM; + unsigned int dataBusWidth = memSpec->bitWidth * NumberOfDevicesOnDIMM; assert(dataBusWidth > 0); return dataBusWidth; } @@ -390,7 +390,7 @@ unsigned int Configuration::getDataBusWidth() unsigned int Configuration::getBytesPerBurst() { // First multiply to get the number of bits in a burst, then divide by 8 to get the value in bytes. The order is important. Think on a single x4 device. - unsigned int bytesPerBurst = (memSpec.BurstLength * getDataBusWidth()) / 8; + unsigned int bytesPerBurst = (memSpec->BurstLength * getDataBusWidth()) / 8; assert(bytesPerBurst > 0); if (NumberOfDevicesOnDIMM > 1) { @@ -399,7 +399,7 @@ unsigned int Configuration::getBytesPerBurst() // or burst element has N bytes. N = 2^(# bits for byte offset)). unsigned int burstElementSizeInBytes = AddressDecoder::getInstance().amount["bytes"]; - assert(bytesPerBurst == (burstElementSizeInBytes * memSpec.BurstLength)); + assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->BurstLength)); } return bytesPerBurst; @@ -407,27 +407,27 @@ unsigned int Configuration::getBytesPerBurst() sc_time Configuration::getTrasb() { - return trasbclk * memSpec.clk; + return trasbclk * memSpec->clk; } sc_time Configuration::getTrrdb_L() { - return trrdblclk * memSpec.clk; + return trrdblclk * memSpec->clk; } sc_time Configuration::getTrrdb_S() { - return trrdbsclk * memSpec.clk; + return trrdbsclk * memSpec->clk; } sc_time Configuration::getTrpb() { - return trpbclk * memSpec.clk; + return trpbclk * memSpec->clk; } sc_time Configuration::getTrcb() { - return trcbclk * memSpec.clk; + return trcbclk * memSpec->clk; } sc_time Configuration::getTfawb() { - return tfawbclk * memSpec.clk; + return tfawbclk * memSpec->clk; } bool Configuration::getRGRBank(unsigned int w) { diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index bd1e4bfe..51d4079e 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -72,7 +72,7 @@ struct Configuration unsigned int Capsize = 5; sc_time getPowerDownTimeout() { - return powerDownTimeoutInClk * memSpec.clk; + return powerDownTimeoutInClk * memSpec->clk; } EPowerDownMode PowerDownMode = EPowerDownMode::Staggered; bool ReadWriteGrouping = false; @@ -139,7 +139,7 @@ struct Configuration unsigned long long int AddressOffset = 0; // MemSpec (from DRAM-Power XML) - MemSpec memSpec; + MemSpec *memSpec; void setParameter(std::string name, std::string value); void setParameters(std::map parameterMap); diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 093479c8..79b9965f 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -139,34 +139,35 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) void ConfigurationLoader::loadMemSpec(Configuration &config, XMLElement *memspec) { - config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId"); - config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType"); + string memoryType = queryStringParameter(memspec, "memoryType"); - std::cout << "Before" << std::endl; - if (config.memSpec.MemoryType == "DDR4") { - delete(&Configuration::getInstance().memSpec); + if (memoryType == "DDR4") { Configuration::getInstance().memSpec = - *new MemSpecDDR4; + new MemSpecDDR4; loadDDR4(config, memspec); - } else if (config.memSpec.MemoryType == "DDR3") { - delete(&Configuration::getInstance().memSpec); + } else if (memoryType == "DDR3") { Configuration::getInstance().memSpec = - *new MemSpecDDR3; + new MemSpecDDR3; loadDDR3(config, memspec); - } else if (config.memSpec.MemoryType == "LPDDR4") { - delete(&Configuration::getInstance().memSpec); + } else if (memoryType == "LPDDR4") { Configuration::getInstance().memSpec = - *new MemSpecLPDDR4; + new MemSpecLPDDR4; loadLPDDR4(config, memspec); - } else if (config.memSpec.MemoryType == "WIDEIO_SDR") { - delete(&Configuration::getInstance().memSpec); + } else if (memoryType == "WIDEIO_SDR") { Configuration::getInstance().memSpec = - *new MemSpecWideIO; + new MemSpecWideIO; loadWideIO(config, memspec); } else { reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } - std::cout << "After" << std::endl; + + loadCommons(config, memspec); +} + +void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *memspec) +{ + config.memSpec->MemoryId = queryStringParameter(memspec, "memoryId"); + config.memSpec->MemoryType = queryStringParameter(memspec, "memoryType"); } void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) @@ -174,153 +175,152 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) //MemArchitecture XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec.NumberOfBankGroups = 1; - config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec.nActivate = 4; - config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec.NumberOfColumns = queryUIntParameter(architecture, + config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + config.memSpec->NumberOfBankGroups = 1; + config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + config.memSpec->nActivate = 4; + config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec.DLL = true; - config.memSpec.termination = true; + config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); + config.memSpec->DLL = true; + config.memSpec->termination = true; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz); - sc_time clk = config.memSpec.clk; - config.memSpec.tRP = clk * queryUIntParameter(timings, "RP"); - config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec.tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD"); - config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD"); - config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW"); - config.memSpec.tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec.tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec.tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR"); - config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec.tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); - config.memSpec.tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); + sc_time clk = config.memSpec->clk; + config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec.refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) { - config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, - config.memSpec.tREFI); + config.memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { + config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, + config.memSpec->tREFI); } // Currents and Volatages: TODO Check if this is correct. XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec.iDD02 = 0; - config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0"); - config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0"); - config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec.iDD62 = 0; - config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec.vDD2 = 0; + config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec->iDD02 = 0; + config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec->iDD62 = 0; + config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec->vDD2 = 0; } - void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) { //MemArchitecture XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec.NumberOfBankGroups = queryUIntParameter(architecture, + config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + config.memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); - config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec.nActivate = 4; - config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec.NumberOfColumns = queryUIntParameter(architecture, + config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + config.memSpec->nActivate = 4; + config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec.DLL = true; - config.memSpec.termination = true; + config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); + config.memSpec->DLL = true; + config.memSpec->termination = true; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz); - sc_time clk = config.memSpec.clk; - config.memSpec.tRP = clk * queryUIntParameter(timings, "RP"); - config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec.tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); - config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); - config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); - config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); - config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW"); - config.memSpec.tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec.tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec.tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); - config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); - config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec.tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); - config.memSpec.tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec.tRFC2 = clk * queryUIntParameter(timings, "RFC2"); - config.memSpec.tRFC4 = clk * queryUIntParameter(timings, "RFC4"); - config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); + sc_time clk = config.memSpec->clk; + config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); + config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); + config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); + config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); + config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); + config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + config.memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); + config.memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); + config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec.refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) { - config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, - config.memSpec.tRFC2, - config.memSpec.tRFC4, - config.memSpec.tREFI); + config.memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { + config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, + config.memSpec->tRFC2, + config.memSpec->tRFC4, + config.memSpec->tREFI); } // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0"); - config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0"); - config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62"); - config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2"); + config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } // TODO: fix this for LPDDR4 @@ -329,76 +329,76 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec) //MemArchitecture: XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec.NumberOfBankGroups = 1; - config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec.nActivate = 4; - config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec.NumberOfColumns = queryUIntParameter(architecture, + config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + config.memSpec->NumberOfBankGroups = 1; + config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + config.memSpec->nActivate = 4; + config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec.DLL = false; // TODO: Correct? - config.memSpec.termination = true; // TODO: Correct? + config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); + config.memSpec->DLL = false; // TODO: Correct? + config.memSpec->termination = true; // TODO: Correct? //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz); - sc_time clk = config.memSpec.clk; - config.memSpec.tRP = clk * queryUIntParameter(timings, "RPPB"); - config.memSpec.tRPAB = clk * queryUIntParameter(timings, "RPAB"); - config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec.tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD"); - config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD"); - config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW"); - config.memSpec.tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec.tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec.tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR"); - config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec.tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XP"); - config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XS"); - config.memSpec.tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFCAB"); - // TODO: config.memSpec.tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFIAB"); - // TODO: config.memSpec.tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); - config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); + sc_time clk = config.memSpec->clk; + config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); + config.memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); + config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); + // TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); + config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); + // TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); + config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec.refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) { - config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, - config.memSpec.tREFI); + config.memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { + config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, + config.memSpec->tREFI); } // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p"); - config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p2"); - config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p"); - config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p2"); - config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62"); - config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2"); + config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); + config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); + config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); + config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); + config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) @@ -406,79 +406,79 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) //MemSpecification XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec.NumberOfBankGroups = 1; - config.memSpec.NumberOfRanks = 1; - config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec.nActivate = 2; - config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec.NumberOfColumns = queryUIntParameter(architecture, + config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + config.memSpec->NumberOfBankGroups = 1; + config.memSpec->NumberOfRanks = 1; + config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + config.memSpec->nActivate = 2; + config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec.bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec.DLL = false; - config.memSpec.termination = false; + config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); + config.memSpec->DLL = false; + config.memSpec->termination = false; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec.clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec.clk = FrequencyToClk(config.memSpec.clkMHz); - sc_time clk = config.memSpec.clk; - config.memSpec.tRP = clk * queryUIntParameter(timings, "RP"); - config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec.tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec.tRRD_L = config.memSpec.tRRD_S; - config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec.tCCD_L = config.memSpec.tCCD_S; - config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec.tNAW = clk * queryUIntParameter(timings, "TAW"); - config.memSpec.tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec.tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec.tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec.tWTR_L = config.memSpec.tWTR_S; - config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec.tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec.tXPDLL = config.memSpec.tXP; - config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec.tXSRDLL = config.memSpec.tXSR; - config.memSpec.tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI"); + config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); + sc_time clk = config.memSpec->clk; + config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tRRD_L = config.memSpec->tRRD_S; + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tCCD_L = config.memSpec->tCCD_S; + config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); + config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_L = config.memSpec->tWTR_S; + config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + config.memSpec->tXPDLL = config.memSpec->tXP; + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = config.memSpec->tXSR; + config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec.refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) { - config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, - config.memSpec.tREFI); + config.memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { + config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, + config.memSpec->tREFI); } // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0"); - config.memSpec.iDD2P02 = queryDoubleParameter(powers, "idd2p02"); - config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - config.memSpec.iDD2P12 = queryDoubleParameter(powers, "idd2p12"); - config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec.iDD2N2 = queryDoubleParameter(powers, "idd2n2"); - config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0"); - config.memSpec.iDD3P02 = queryDoubleParameter(powers, "idd3p02"); - config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - config.memSpec.iDD3P12 = queryDoubleParameter(powers, "idd3p12"); - config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec.iDD3N2 = queryDoubleParameter(powers, "idd3n2"); - config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec.iDD4R2 = queryDoubleParameter(powers, "idd4r2"); - config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec.iDD4W2 = queryDoubleParameter(powers, "idd4w2"); - config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec.iDD52 = queryDoubleParameter(powers, "idd52"); - config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62"); - config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2"); + config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + config.memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); + config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + config.memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12"); + config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2"); + config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + config.memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02"); + config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + config.memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12"); + config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2"); + config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2"); + config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2"); + config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec->iDD52 = queryDoubleParameter(powers, "idd52"); + config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h index c4b77530..d7a12c57 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h @@ -65,8 +65,9 @@ private: static void loadConfig(Configuration &config, tinyxml2::XMLElement *configNode); static void loadConfigFromUri(Configuration &config, std::string uri, std::string first_element); - - //specific loader + // Loads common config of DRAMs + static void loadCommons(Configuration &config, tinyxml2::XMLElement *memspec); + // Load specific config static void loadDDR3(Configuration &config, tinyxml2::XMLElement *memspec); static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec); static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 00a48073..fc4fb576 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -56,11 +56,6 @@ struct RefreshTiming struct MemSpec { - MemSpec() - { - //default DDR4 - } - const std::vector &getBanks() const { static std::vector banks; @@ -170,34 +165,22 @@ struct MemSpec struct MemSpecDDR3 : public MemSpec { - MemSpecDDR3() - { - std::cout << "Generated MemSpecDDR3" << std::endl; - } + }; struct MemSpecDDR4 : public MemSpec { - MemSpecDDR4() - { - std::cout << "Generated MemSpecDDR4" << std::endl; - } + }; struct MemSpecWideIO : public MemSpec { - MemSpecWideIO() - { - std::cout << "Generated MemSpecWideIO" << std::endl; - } + }; struct MemSpecLPDDR4 : public MemSpec { - MemSpecLPDDR4() - { - std::cout << "Generated MemSpecLPDDR4" << std::endl; - } + }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index e7f5b652..f5cea5d0 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -46,19 +46,19 @@ using namespace std; RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), - timing(ctrlcore.config.memSpec.refreshTimings[ccore.getBanks()[0]]) + timing(ctrlcore.config.memSpec->refreshTimings[ccore.getBanks()[0]]) { fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst; bwl = ccore.config.BankwiseLogic; ri = ccore.config.getRowInc(); - auto nr = ccore.config.memSpec.NumberOfRows; + auto nr = ccore.config.memSpec->NumberOfRows; auto nar = ccore.config.getNumAR(); auto m = ccore.config.getRefMode(); rpr = (nr / m) / nar; assert(rpr > 0); tREFIx = timing.tREFI / m; trp = ccore.config.getTrpb(); - trcd = ccore.config.memSpec.tRCD; + trcd = ccore.config.memSpec->tRCD; postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone; pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn; maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m; @@ -73,7 +73,7 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), } #if INITIAL_DISPLACEMENT == TRUE if (bwl) { - auto nbs = ccore.config.memSpec.NumberOfBanks; + auto nbs = ccore.config.memSpec->NumberOfBanks; for (Bank b : ccore.getBanks()) { nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs; } diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index 8b4981ec..b088ca97 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -46,7 +46,7 @@ using namespace tlm; RefreshManager::RefreshManager(sc_module_name, ControllerCore &controller) : controllerCore(controller), - timing(controller.config.memSpec.refreshTimings[Bank(0)]) + timing(controller.config.memSpec->refreshTimings[Bank(0)]) { auto m = controllerCore.config.getRefMode(); tREFIx = timing.tREFI / m; @@ -159,7 +159,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec.tRP; + nrt += controllerCore.config.memSpec->tRP; nextRefTiming = nrt; nextState = ST_PULLIN; } else { @@ -175,7 +175,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec.tRP; + nrt += controllerCore.config.memSpec->tRP; nextRefTiming = nrt; nextState = ST_PULLIN; } else { @@ -220,7 +220,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, } else { nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec.tRP; + nrt += controllerCore.config.memSpec->tRP; nextRefTiming = nrt; nextState = ST_BURST; } diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index a496ab8e..c53f779b 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -44,7 +44,7 @@ using namespace std; RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name, ControllerCore &controller) : controllerCore(controller), - timing(controller.config.memSpec.refreshTimings[Bank(0)]) + timing(controller.config.memSpec->refreshTimings[Bank(0)]) { auto m = controllerCore.config.getRefMode(); tREFIx = timing.tREFI / m; @@ -146,7 +146,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec.tRP; + nrt += controllerCore.config.memSpec->tRP; nextRefTiming = nrt; nextState[bank] = ST_PULLIN; } else { @@ -162,7 +162,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec.tRP; + nrt += controllerCore.config.memSpec->tRP; nextRefTiming = nrt; nextState[bank] = ST_PULLIN; } else { @@ -208,7 +208,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, } else { nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec.tRP; + nrt += controllerCore.config.memSpec->tRP; nextRefTiming = nrt; nextState[bank] = ST_BURST; } diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index 2945cc74..4207b9ff 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -127,13 +127,13 @@ TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const || getCommand() == Command::Write || getCommand() == Command::WriteA); - MemSpec &timings = Configuration::getInstance().memSpec; + MemSpec *timings = Configuration::getInstance().memSpec; if (getCommand() == Command::Read || getCommand() == Command::ReadA) { - return TimeInterval(getStart() + timings.tRL, - getStart() + timings.tRL + getReadAccessTime()); + return TimeInterval(getStart() + timings->tRL, + getStart() + timings->tRL + getReadAccessTime()); } else { - return TimeInterval(getStart() + timings.tWL - timings.clk / 2, - getStart() + timings.tWL + getWriteAccessTime() - timings.clk / 2); + return TimeInterval(getStart() + timings->tWL - timings->clk / 2, + getStart() + timings->tWL + getWriteAccessTime() - timings->clk / 2); } } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 55edd9a9..16557602 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -53,27 +53,27 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const Configuration::getInstance().getTrpb()); } else if (lcb.getCommand() == Command::Precharge || lcb.getCommand() == Command::PrechargeAll) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRP); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRP); } else if (lcb.getCommand() == Command::ReadA) { cmd.establishMinDistanceFromStart(lcb.getStart(), - config.memSpec.tRTP + config.memSpec.tRP); + config.memSpec->tRTP + config.memSpec->tRP); } else if (lcb.getCommand() == Command::WriteA) { cmd.establishMinDistanceFromStart(lcb.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + - config.memSpec.tRP); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tRP); } else if (lcb.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRFC4); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC4); else if (m == 2) - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRFC2); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC2); else - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tRFC); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC); } else if (lcb.getCommand() == Command::PDNPX || lcb.getCommand() == Command::PDNAX) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tXP); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP); } else if (lcb.getCommand() == Command::SREFX) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec.tXSR); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXSR); } else { reportFatal("ActB Checker", "ActB can not follow " + commandToString(lcb.getCommand())); @@ -81,13 +81,13 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const } ScheduledCommand lc; if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec.tRP); + cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP); } delay_to_satisfy_activateToActivate_sameBank(cmd); while (!(state.bus.isFree(cmd.getStart()) && satsfies_activateToActivate_differentBank(cmd) && satisfies_nActivateWindow(cmd))) { - cmd.delayStart(config.memSpec.clk); + cmd.delayStart(config.memSpec->clk); } } @@ -97,7 +97,7 @@ void ActBChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand lastActOnBank = state.getLastCommand(Command::Activate, cmd.getBank()); if (lastActOnBank.isValidCommand()) { - cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec.tRC); + cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec->tRC); } ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ActB, cmd.getBank()); @@ -121,7 +121,7 @@ bool ActBChecker::satsfies_activateToActivate_differentBank( } for (auto act : state.lastActivates) { sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ? - config.memSpec.tRRD_L : config.memSpec.tRRD_S); + config.memSpec->tRRD_L : config.memSpec->tRRD_S); if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t && t - cmd.getStart() < tRRD)) { return false; @@ -132,11 +132,11 @@ bool ActBChecker::satsfies_activateToActivate_differentBank( bool ActBChecker::satisfies_nActivateWindow(ScheduledCommand &cmd) const { - if (state.lastActivatesB.size() >= config.memSpec.nActivate) { + if (state.lastActivatesB.size() >= config.memSpec->nActivate) { maplastActivates = state.lastActivatesB; lastActivates.emplace(cmd.getStart(), cmd); auto upper = lastActivates.begin(); - advance(upper, config.memSpec.nActivate); + advance(upper, config.memSpec->nActivate); auto lower = lastActivates.begin(); while (upper != lastActivates.end()) { if (upper->first - lower->first < Configuration::getInstance().getTfawb()) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 18236ba3..f2bb8033 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -56,32 +56,32 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const || lastCommandOnBank.getCommand() == Command::Precharge || lastCommandOnBank.getCommand() == Command::PrechargeAll) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRP); + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRTP + config.memSpec.tRP); + config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + - config.memSpec.tRP); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRFC4); + config.memSpec->tRFC4); else if (m == 2) command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRFC2); + config.memSpec->tRFC2); else command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRFC); + config.memSpec->tRFC); } else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else if (lastCommandOnBank.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tXSR); + config.memSpec->tXSR); } else reportFatal("Activate Checker", "Activate can not follow " + commandToString(lastCommandOnBank.getCommand())); @@ -92,7 +92,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const while (!(state.bus.isFree(command.getStart()) && satsfies_activateToActivate_differentBank(command) && satisfies_nActivateWindow(command))) { - command.delayStart(config.memSpec.clk); + command.delayStart(config.memSpec->clk); } } @@ -104,14 +104,14 @@ void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank( command.getBank()); if (lastActivateOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), - config.memSpec.tRC); + config.memSpec->tRC); } ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ActB, command.getBank()); if (lastActBOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), - config.memSpec.tRC); + config.memSpec->tRC); } } @@ -121,7 +121,7 @@ bool ActivateChecker::satsfies_activateToActivate_differentBank( for (auto act : state.lastActivates) { sc_time time = act.first; sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? - config.memSpec.tRRD_L : config.memSpec.tRRD_S; + config.memSpec->tRRD_L : config.memSpec->tRRD_S; if ((time < command.getStart() && command.getStart() - time < tRRD) || (command.getStart() <= time && time - command.getStart() < tRRD)) @@ -137,15 +137,15 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand &command) const * command in a copied set (not necessarily the last in time), * and check if the n-act constraint holds for the whole set. */ - if (state.lastActivates.size() >= config.memSpec.nActivate) { + if (state.lastActivates.size() >= config.memSpec->nActivate) { map lastActivates = state.lastActivates; lastActivates.emplace(command.getStart(), command); auto upper = lastActivates.begin(); - advance(upper, config.memSpec.nActivate); + advance(upper, config.memSpec->nActivate); auto lower = lastActivates.begin(); while (upper != lastActivates.end()) { - if (upper->first - lower->first < config.memSpec.tNAW) + if (upper->first - lower->first < config.memSpec->tNAW) return false; ++upper; ++lower; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 7a430ac6..723c74ec 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -47,26 +47,26 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, sc_time constraint; if (lastCmd == Command::Read || lastCmd == Command::ReadA) { - constraint = config.memSpec.tRL + getReadAccessTime() + config.memSpec.clk; + constraint = config.memSpec->tRL + getReadAccessTime() + config.memSpec->clk; } else if (lastCmd == Command::Write) { - constraint = config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR; + constraint = config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR; } else if (lastCmd == Command::WriteA) { - constraint = config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + - config.memSpec.clk; + constraint = config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->clk; } else if (lastCmd == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) - constraint = config.memSpec.tRFC4; + constraint = config.memSpec->tRFC4; else if (m == 2) - constraint = config.memSpec.tRFC2; + constraint = config.memSpec->tRFC2; else - constraint = config.memSpec.tRFC; + constraint = config.memSpec->tRFC; } else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) { - constraint = config.memSpec.tXP; + constraint = config.memSpec->tXP; } else if (lastCmd == Command::SREFX) { - constraint = config.memSpec.tXSR; + constraint = config.memSpec->tXSR; } else if (lastCmd == Command::Precharge || lastCmd == Command::PrechargeAll) { - constraint = config.memSpec.tRP; + constraint = config.memSpec->tRP; } else { reportFatal("Powerdown checker", commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); @@ -117,17 +117,17 @@ const } else if (pdnCmd == Command::PDNAX) { // Leaving Active Power Down - timeConstraint = config.memSpec.tCKE; + timeConstraint = config.memSpec->tCKE; command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNA, bank).getStart(), timeConstraint); } else if (pdnCmd == Command::PDNPX) { // Leaving Precharge Power Down - timeConstraint = config.memSpec.tCKE; + timeConstraint = config.memSpec->tCKE; command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNP, bank).getStart(), timeConstraint); } else if (pdnCmd == Command::SREFX) { // Leaving Self Refresh - timeConstraint = config.memSpec.tCKESR; + timeConstraint = config.memSpec->tCKESR; command.establishMinDistanceFromStart(state.getLastCommand(Command::SREF, bank).getStart(), timeConstraint); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index f559bf38..44e23882 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -43,21 +43,21 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), Configuration::getInstance().getTrpb()); } else if (lastCmd.getCommand() == Command::Precharge) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRP); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP); } else if (lastCmd.getCommand() == Command::PrechargeAll) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRP); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP); } else if (lastCmd.getCommand() == Command::ActB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), - config.memSpec.tRCD); // XXX: trcd is less than the NEW! trasb! ok! + config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok! } else if (lastCmd.getCommand() == Command::Activate) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRCD); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); } else if (lastCmd.getCommand() == Command::Read) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tRTP); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRTP); } else if (lastCmd.getCommand() == Command::Write) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR); } else if (lastCmd.getCommand() == Command::PDNAX) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec.tXP); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP); } else { reportFatal("PreB Checker", "PreB can not follow " + commandToString(lastCmd.getCommand())); @@ -65,11 +65,11 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const } ScheduledCommand lc; if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec.tRP); + cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP); } if ((lc = state.getLastCommand(Command::Activate, cmd.getBank())).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec.tRAS); + cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); } if ((lc = state.getLastCommand(Command::ActB, cmd.getBank())).isValidCommand()) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index f666408d..f6ee06d9 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -45,48 +45,48 @@ const sc_assert(command.getCommand() == Command::PrechargeAll); // Consider all banks for the constraints, since precharge all command is supposed to happen at the same time on all banks - for (unsigned int bank = 0; bank < config.memSpec.NumberOfBanks; ++bank) { + for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); if (lastCommand.isValidCommand()) { if (lastCommand.getCommand() == Command::Precharge || lastCommand.getCommand() == Command::PreB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRP); + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRCD); + config.memSpec->tRCD); } else if (lastCommand.getCommand() == Command::Read) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRTP); + config.memSpec->tRTP); } else if (lastCommand.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRTP + config.memSpec.tRP); + config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::Write) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR); } else if (lastCommand.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + - config.memSpec.tRP); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRFC4); + config.memSpec->tRFC4); else if (m == 2) command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRFC2); + config.memSpec->tRFC2); else command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRFC); + config.memSpec->tRFC); } else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else if (lastCommand.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXSR); + config.memSpec->tXSR); } else reportFatal("Precharge All Checker", "Precharge All can not follow " + commandToString(lastCommand.getCommand())); @@ -97,7 +97,7 @@ const command.getBank()); if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), - config.memSpec.tRAS); + config.memSpec->tRAS); } state.bus.moveCommandToNextFreeSlot(command); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index 6767be1f..75a8ebdc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -52,23 +52,23 @@ const if (lastCommand.getCommand() == Command::Precharge || lastCommand.getCommand() == Command::PreB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRP); + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRCD); + config.memSpec->tRCD); } else if (lastCommand.getCommand() == Command::Read) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRTP); + config.memSpec->tRTP); } else if (lastCommand.getCommand() == Command::Write) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR); } else if (lastCommand.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else reportFatal("Precharge Checker", "Precharge can not follow " + commandToString(lastCommand.getCommand())); @@ -78,7 +78,7 @@ const command.getBank()); if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), - config.memSpec.tRAS); + config.memSpec->tRAS); } state.bus.moveCommandToNextFreeSlot(command); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 048f5cd5..06a121a6 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -52,7 +52,7 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRCD); + config.memSpec->tRCD); } else if (lastCommand.getCommand() == Command::Read) { command.establishMinDistanceFromStart(lastCommand.getStart(), ReadChecker::readToRead(lastCommand, command)); @@ -62,14 +62,14 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommand.getCommand() == Command::PDNPX || lastCommand.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else reportFatal("Read Checker", "Read can not follow " + commandToString(lastCommand.getCommand())); } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { - command.delayStart(config.memSpec.clk); + command.delayStart(config.memSpec->clk); } } @@ -112,7 +112,7 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), - config.memSpec.tXSRDLL); + config.memSpec->tXSRDLL); } sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, @@ -123,9 +123,9 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, sc_assert(secondRead.getCommand() == Command::Read || secondRead.getCommand() == Command::ReadA); - MemSpec &config = Configuration::getInstance().memSpec; + MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? - config.tCCD_L : config.tCCD_S; + config->tCCD_L : config->tCCD_S; return max(tCCD, getReadAccessTime()); } @@ -137,9 +137,9 @@ sc_time ReadChecker::writeToRead(ScheduledCommand &write, sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); - MemSpec &config = Configuration::getInstance().memSpec; - sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config.tWTR_L : - config.tWTR_S; - return config.tWL + getWriteAccessTime() + tWTR; + MemSpec *config = Configuration::getInstance().memSpec; + sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L : + config->tWTR_S; + return config->tWL + getWriteAccessTime() + tWTR; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index aad23f4a..eea8f763 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -50,53 +50,53 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommandOnBank.getCommand() == Command::Precharge || lastCommandOnBank.getCommand() == Command::PrechargeAll) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRP); + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tRTP + config.memSpec.tRP); + config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + - config.memSpec.tRP); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else if (lastCommandOnBank.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec.tXSR); + config.memSpec->tXSR); } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { } else reportFatal("Refresh Checker", "Refresh can not follow " + commandToString(lastCommandOnBank.getCommand())); } } else { - for (unsigned int bank = 0; bank < config.memSpec.NumberOfBanks; ++bank) { + for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); if (lastCommand.isValidCommand()) { if (lastCommand.getCommand() == Command::Precharge || lastCommand.getCommand() == Command::PrechargeAll || lastCommand.getCommand() == Command::PreB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRP); + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRCD); + config.memSpec->tRCD); } else if (lastCommand.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRTP + config.memSpec.tRP); + config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + - config.memSpec.tRP); + config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else if (lastCommand.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXSR); + config.memSpec->tXSR); } else if (lastCommand.getCommand() == Command::AutoRefresh) { } else reportFatal("Refresh Checker", diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index b2aed2d2..38eafdaa 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -52,7 +52,7 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tRCD); + config.memSpec->tRCD); } else if (lastCommand.getCommand() == Command::Read) { command.establishMinDistanceFromStart(lastCommand.getStart(), WriteChecker::readToWrite(lastCommand, command)); @@ -62,14 +62,14 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommand.getCommand() == Command::PDNPX || lastCommand.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec.tXP); + config.memSpec->tXP); } else reportFatal("Write Checker", "Write can not follow " + commandToString(lastCommand.getCommand())); } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { - command.delayStart(config.memSpec.clk); + command.delayStart(config.memSpec->clk); } } @@ -114,9 +114,9 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, sc_assert(secondWrite.getCommand() == Command::Write || secondWrite.getCommand() == Command::WriteA); - MemSpec &config = Configuration::getInstance().memSpec; + MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? - config.tCCD_L : config.tCCD_S; + config->tCCD_L : config->tCCD_S; return max(tCCD, getWriteAccessTime()); } @@ -128,7 +128,7 @@ sc_time WriteChecker::readToWrite(ScheduledCommand &read __attribute__(( sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); - MemSpec &config = Configuration::getInstance().memSpec; - return config.tRL + getReadAccessTime() - config.tWL + config.clk * 2; + MemSpec *config = Configuration::getInstance().memSpec; + return config->tRL + getReadAccessTime() - config->tWL + config->clk * 2; } diff --git a/DRAMSys/library/src/controller/core/timingCalculations.cpp b/DRAMSys/library/src/controller/core/timingCalculations.cpp index 2f4b65cb..077e5d22 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.cpp +++ b/DRAMSys/library/src/controller/core/timingCalculations.cpp @@ -59,7 +59,7 @@ const sc_time FrequencyToClk(double frequencyMhz) const sc_time clkAlign(sc_time time, Alignment alignment) { - sc_time clk = Configuration::getInstance().memSpec.clk; + sc_time clk = Configuration::getInstance().memSpec->clk; if (alignment == UP) return ceil(time / clk) * clk; else @@ -69,39 +69,39 @@ const sc_time clkAlign(sc_time time, Alignment alignment) // Returns the execution time for commands that have a fixed execution time sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) { - MemSpec &config = Configuration::getInstance().memSpec; + MemSpec *config = Configuration::getInstance().memSpec; if (command == Command::PreB) { return Configuration::getInstance().getTrpb(); } else if (command == Command::Precharge || command == Command::PrechargeAll) { - return config.tRP; + return config->tRP; } else if (command == Command::ActB) { - return config.tRCD; + return config->tRCD; } else if (command == Command::Activate) { - return config.tRCD; + return config->tRCD; } else if (command == Command::Read) { - return config.tRL + getReadAccessTime(); + return config->tRL + getReadAccessTime(); } else if (command == Command::ReadA) { - return config.tRTP + config.tRP; + return config->tRTP + config->tRP; } else if (command == Command::Write) { - return config.tWL + getWriteAccessTime(); + return config->tWL + getWriteAccessTime(); } else if (command == Command::WriteA) { - return config.tWL + getWriteAccessTime() + config.tWR + config.tRP; + return config->tWL + getWriteAccessTime() + config->tWR + config->tRP; } else if (command == Command::PrechargeAll) { - return config.tRP; + return config->tRP; } else if (command == Command::AutoRefresh) { if (Configuration::getInstance().getRefMode() == 4) - return getElementFromMap(config.refreshTimings, + return getElementFromMap(config->refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC4; else if (Configuration::getInstance().getRefMode() == 2) - return getElementFromMap(config.refreshTimings, + return getElementFromMap(config->refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC2; else - return getElementFromMap(config.refreshTimings, + return getElementFromMap(config->refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC; } else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) { - return config.clk; + return config->clk; } else { SC_REPORT_FATAL("getExecutionTime", "command not known or command doesn't have a fixed execution time"); @@ -112,11 +112,11 @@ sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) // Returns the minimum execution time for commands that have a variable execution time sc_time getMinExecutionTimeForPowerDownCmd(Command command) { - MemSpec &config = Configuration::getInstance().memSpec; + MemSpec *config = Configuration::getInstance().memSpec; if (command == Command::PDNA || command == Command::PDNP) { - return config.tCKE; + return config->tCKE; } else if (command == Command::SREF) { - return config.tCKESR; + return config->tCKESR; } else { SC_REPORT_FATAL("getMinimalExecutionTime", "command is not know or command has a fixed execution time"); @@ -133,19 +133,19 @@ bool isClkAligned(sc_time time, sc_time clk) sc_time getReadAccessTime() { Configuration &config = Configuration::getInstance(); - return (config.memSpec.BurstLength / config.memSpec.DataRate) * - config.memSpec.clk; + return (config.memSpec->BurstLength / config.memSpec->DataRate) * + config.memSpec->clk; } sc_time getWriteAccessTime() { Configuration &config = Configuration::getInstance(); - if (config.memSpec.DataRate == 1) { - return config.memSpec.clk * (config.memSpec.BurstLength); + if (config.memSpec->DataRate == 1) { + return config.memSpec->clk * (config.memSpec->BurstLength); } else { - return config.memSpec.clk * (config.memSpec.BurstLength / - config.memSpec.DataRate); + return config.memSpec->clk * (config.memSpec->BurstLength / + config.memSpec->DataRate); } } diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp index ef5d1bc1..3b41fd43 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp @@ -132,7 +132,7 @@ std::pair FrFcfsGrp::getNextRequest(Bank bank) // If nothing was found we check the other banks before we switch the mode: pair other(Command::NOP, NULL); - unsigned int B = Configuration::getInstance().memSpec.NumberOfBanks; + unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; for (unsigned int i = 1; i < B; i++) { Bank nextBank((bank.ID() + i) % B); @@ -175,7 +175,7 @@ unsigned int FrFcfsGrp::getNumberOfRequest(tlm::tlm_command cmd) { unsigned int numberOfRequests = 0; for (unsigned int i = 0; - i < Configuration::getInstance().memSpec.NumberOfBanks; + i < Configuration::getInstance().memSpec->NumberOfBanks; i++) { for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { gp *trans = *it; diff --git a/DRAMSys/library/src/controller/scheduler/Grp.cpp b/DRAMSys/library/src/controller/scheduler/Grp.cpp index aa6c49cf..cf4dffe2 100644 --- a/DRAMSys/library/src/controller/scheduler/Grp.cpp +++ b/DRAMSys/library/src/controller/scheduler/Grp.cpp @@ -118,7 +118,7 @@ std::pair Grp::getNextRequest(Bank bank) // If nothing was found we check the other banks before we switch the mode: pair other(Command::NOP, NULL); - unsigned int B = Configuration::getInstance().memSpec.NumberOfBanks; + unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; for (unsigned int i = 1; i < B; i++) { Bank nextBank((bank.ID() + i) % B); @@ -161,7 +161,7 @@ unsigned int Grp::getNumberOfRequest(tlm::tlm_command cmd) { unsigned int numberOfRequests = 0; for (unsigned int i = 0; - i < Configuration::getInstance().memSpec.NumberOfBanks; + i < Configuration::getInstance().memSpec->NumberOfBanks; i++) { for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { gp *trans = *it; diff --git a/DRAMSys/library/src/controller/scheduler/SMS.cpp b/DRAMSys/library/src/controller/scheduler/SMS.cpp index 42530571..f01267d7 100644 --- a/DRAMSys/library/src/controller/scheduler/SMS.cpp +++ b/DRAMSys/library/src/controller/scheduler/SMS.cpp @@ -46,7 +46,7 @@ std::pair SMS::getNextRequest(Bank bank) void SMS::batchScheduler() { - sc_time memClk = Configuration::getInstance().memSpec.clk; + sc_time memClk = Configuration::getInstance().memSpec->clk; std::default_random_engine generator; std::bernoulli_distribution distribution((double) SJFprobability / 100.0); diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index eb70a964..861df60a 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -46,15 +46,15 @@ void errorModel::init() powerAnalysis = Configuration::getInstance().PowerAnalysis; thermalSim = Configuration::getInstance().ThermalSimulation; // Get Configuration parameters: - burstLenght = Configuration::getInstance().memSpec.BurstLength; - numberOfColumns = Configuration::getInstance().memSpec.NumberOfColumns; + burstLenght = Configuration::getInstance().memSpec->BurstLength; + numberOfColumns = Configuration::getInstance().memSpec->NumberOfColumns; bytesPerColumn = AddressDecoder::getInstance().amount["bytes"]; // Adjust number of bytes per column dynamically to the selected ecc controller bytesPerColumn = Configuration::getInstance().adjustNumBytesAfterECC( bytesPerColumn); - numberOfRows = Configuration::getInstance().memSpec.NumberOfRows; + numberOfRows = Configuration::getInstance().memSpec->NumberOfRows; numberOfBitErrorEvents = 0; @@ -253,7 +253,7 @@ void errorModel::markBitFlips() { double temp = getTemperature(); for (unsigned int row = 0; - row < Configuration::getInstance().memSpec.NumberOfRows; row++) { + row < Configuration::getInstance().memSpec->NumberOfRows; row++) { // If the row has never been accessed ignore it and go to the next one if (lastRowAccess[row] != SC_ZERO_TIME) { // Get the time interval between now and the last acivate/refresh @@ -498,7 +498,7 @@ double errorModel::getTemperature() // TODO // check if this is best way to request information to DRAMPower. unsigned long long clk_cycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec.clk.value(); + Configuration::getInstance().memSpec->clk.value(); DRAMPower->calcWindowEnergy(clk_cycles); float average_power = (float)DRAMPower->getPower().average_power; temperature = TemperatureController::getInstance().getTemperature( diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 0459445d..b1287f7e 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -82,7 +82,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, } else if (phase == END_RESP) { - notDelay += Configuration::getInstance().memSpec.clk; + notDelay += Configuration::getInstance().memSpec->clk; payload.release(); } diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index e18f1456..5dc28899 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -90,26 +90,26 @@ Dram::Dram(sc_module_name) : tSocket("socket") if (powerAnalysis) { - sc_time clk = Configuration::getInstance().memSpec.clk; + sc_time clk = Configuration::getInstance().memSpec->clk; MemArchitectureSpec memArchSpec; memArchSpec.burstLength = - Configuration::getInstance().memSpec.BurstLength; - memArchSpec.dataRate = Configuration::getInstance().memSpec.DataRate; + Configuration::getInstance().memSpec->BurstLength; + memArchSpec.dataRate = Configuration::getInstance().memSpec->DataRate; memArchSpec.nbrOfRows = - Configuration::getInstance().memSpec.NumberOfRows; + Configuration::getInstance().memSpec->NumberOfRows; memArchSpec.nbrOfBanks = - Configuration::getInstance().memSpec.NumberOfBanks; + Configuration::getInstance().memSpec->NumberOfBanks; memArchSpec.nbrOfColumns = - Configuration::getInstance().memSpec.NumberOfColumns; + Configuration::getInstance().memSpec->NumberOfColumns; memArchSpec.nbrOfRanks = - Configuration::getInstance().memSpec.NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec.bitWidth; + Configuration::getInstance().memSpec->NumberOfRanks; + memArchSpec.width = Configuration::getInstance().memSpec->bitWidth; memArchSpec.nbrOfBankGroups = - Configuration::getInstance().memSpec.NumberOfBankGroups; - memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 + Configuration::getInstance().memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec->vDD2 == 0 ? false : true); - memArchSpec.dll = Configuration::getInstance().memSpec.DLL; + memArchSpec.dll = Configuration::getInstance().memSpec->DLL; MemTimingSpec memTimingSpec; memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; @@ -119,74 +119,74 @@ Dram::Dram(sc_module_name) : tSocket("socket") memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = Configuration::getInstance().memSpec.tAL / clk; - memTimingSpec.CCD = Configuration::getInstance().memSpec.tCCD_S / clk; - memTimingSpec.CCD_L = Configuration::getInstance().memSpec.tCCD_L / clk; - memTimingSpec.CCD_S = Configuration::getInstance().memSpec.tCCD_S / clk; - memTimingSpec.CKE = Configuration::getInstance().memSpec.tCKE / clk; - memTimingSpec.CKESR = Configuration::getInstance().memSpec.tCKESR / clk; - memTimingSpec.clkMhz = Configuration::getInstance().memSpec.clkMHz; + memTimingSpec.AL = Configuration::getInstance().memSpec->tAL / clk; + memTimingSpec.CCD = Configuration::getInstance().memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = Configuration::getInstance().memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = Configuration::getInstance().memSpec->tCCD_S / clk; + memTimingSpec.CKE = Configuration::getInstance().memSpec->tCKE / clk; + memTimingSpec.CKESR = Configuration::getInstance().memSpec->tCKESR / clk; + memTimingSpec.clkMhz = Configuration::getInstance().memSpec->clkMHz; // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec.clkMHz; - memTimingSpec.DQSCK = Configuration::getInstance().memSpec.tDQSCK / clk; - memTimingSpec.FAW = Configuration::getInstance().memSpec.tNAW / clk; - memTimingSpec.RAS = Configuration::getInstance().memSpec.tRAS / clk; - memTimingSpec.RC = Configuration::getInstance().memSpec.tRC / clk; - memTimingSpec.RCD = Configuration::getInstance().memSpec.tRCD / clk; - memTimingSpec.REFI = Configuration::getInstance().memSpec.tREFI / clk; + memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec->clkMHz; + memTimingSpec.DQSCK = Configuration::getInstance().memSpec->tDQSCK / clk; + memTimingSpec.FAW = Configuration::getInstance().memSpec->tNAW / clk; + memTimingSpec.RAS = Configuration::getInstance().memSpec->tRAS / clk; + memTimingSpec.RC = Configuration::getInstance().memSpec->tRC / clk; + memTimingSpec.RCD = Configuration::getInstance().memSpec->tRCD / clk; + memTimingSpec.REFI = Configuration::getInstance().memSpec->tREFI / clk; auto m = Configuration::getInstance().getRefMode(); if (m == 4) - memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC4 / clk; + memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC4 / clk; else if (m == 2) - memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC2 / clk; + memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC2 / clk; else - memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC / clk; - memTimingSpec.RL = Configuration::getInstance().memSpec.tRL / clk; - memTimingSpec.RP = Configuration::getInstance().memSpec.tRP / clk; - memTimingSpec.RRD = Configuration::getInstance().memSpec.tRRD_S / clk; - memTimingSpec.RRD_L = Configuration::getInstance().memSpec.tRRD_L / clk; - memTimingSpec.RRD_S = Configuration::getInstance().memSpec.tRRD_S / clk; - memTimingSpec.RTP = Configuration::getInstance().memSpec.tRTP / clk; - memTimingSpec.TAW = Configuration::getInstance().memSpec.tNAW / clk; - memTimingSpec.WL = Configuration::getInstance().memSpec.tWL / clk; - memTimingSpec.WR = Configuration::getInstance().memSpec.tWR / clk; - memTimingSpec.WTR = Configuration::getInstance().memSpec.tWTR_S / clk; - memTimingSpec.WTR_L = Configuration::getInstance().memSpec.tWTR_L / clk; - memTimingSpec.WTR_S = Configuration::getInstance().memSpec.tWTR_S / clk; - memTimingSpec.XP = Configuration::getInstance().memSpec.tXP / clk; - memTimingSpec.XPDLL = Configuration::getInstance().memSpec.tXPDLL / clk; - memTimingSpec.XS = Configuration::getInstance().memSpec.tXSR / clk; - memTimingSpec.XSDLL = Configuration::getInstance().memSpec.tXSRDLL / clk; + memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC / clk; + memTimingSpec.RL = Configuration::getInstance().memSpec->tRL / clk; + memTimingSpec.RP = Configuration::getInstance().memSpec->tRP / clk; + memTimingSpec.RRD = Configuration::getInstance().memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = Configuration::getInstance().memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = Configuration::getInstance().memSpec->tRRD_S / clk; + memTimingSpec.RTP = Configuration::getInstance().memSpec->tRTP / clk; + memTimingSpec.TAW = Configuration::getInstance().memSpec->tNAW / clk; + memTimingSpec.WL = Configuration::getInstance().memSpec->tWL / clk; + memTimingSpec.WR = Configuration::getInstance().memSpec->tWR / clk; + memTimingSpec.WTR = Configuration::getInstance().memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = Configuration::getInstance().memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = Configuration::getInstance().memSpec->tWTR_S / clk; + memTimingSpec.XP = Configuration::getInstance().memSpec->tXP / clk; + memTimingSpec.XPDLL = Configuration::getInstance().memSpec->tXPDLL / clk; + memTimingSpec.XS = Configuration::getInstance().memSpec->tXSR / clk; + memTimingSpec.XSDLL = Configuration::getInstance().memSpec->tXSRDLL / clk; MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = Configuration::getInstance().memSpec.iDD0; - memPowerSpec.idd02 = Configuration::getInstance().memSpec.iDD02; - memPowerSpec.idd2p0 = Configuration::getInstance().memSpec.iDD2P0; - memPowerSpec.idd2p02 = Configuration::getInstance().memSpec.iDD2P02; - memPowerSpec.idd2p1 = Configuration::getInstance().memSpec.iDD2P1; - memPowerSpec.idd2p12 = Configuration::getInstance().memSpec.iDD2P12; - memPowerSpec.idd2n = Configuration::getInstance().memSpec.iDD2N; - memPowerSpec.idd2n2 = Configuration::getInstance().memSpec.iDD2N2; - memPowerSpec.idd3p0 = Configuration::getInstance().memSpec.iDD3P0; - memPowerSpec.idd3p02 = Configuration::getInstance().memSpec.iDD3P02; - memPowerSpec.idd3p1 = Configuration::getInstance().memSpec.iDD3P1; - memPowerSpec.idd3p12 = Configuration::getInstance().memSpec.iDD3P12; - memPowerSpec.idd3n = Configuration::getInstance().memSpec.iDD3N; - memPowerSpec.idd3n2 = Configuration::getInstance().memSpec.iDD3N2; - memPowerSpec.idd4r = Configuration::getInstance().memSpec.iDD4R; - memPowerSpec.idd4r2 = Configuration::getInstance().memSpec.iDD4R2; - memPowerSpec.idd4w = Configuration::getInstance().memSpec.iDD4W; - memPowerSpec.idd4w2 = Configuration::getInstance().memSpec.iDD4W2; - memPowerSpec.idd5 = Configuration::getInstance().memSpec.iDD5; - memPowerSpec.idd52 = Configuration::getInstance().memSpec.iDD52; - memPowerSpec.idd6 = Configuration::getInstance().memSpec.iDD6; - memPowerSpec.idd62 = Configuration::getInstance().memSpec.iDD62; - memPowerSpec.vdd = Configuration::getInstance().memSpec.vDD; - memPowerSpec.vdd2 = Configuration::getInstance().memSpec.vDD2; + memPowerSpec.idd0 = Configuration::getInstance().memSpec->iDD0; + memPowerSpec.idd02 = Configuration::getInstance().memSpec->iDD02; + memPowerSpec.idd2p0 = Configuration::getInstance().memSpec->iDD2P0; + memPowerSpec.idd2p02 = Configuration::getInstance().memSpec->iDD2P02; + memPowerSpec.idd2p1 = Configuration::getInstance().memSpec->iDD2P1; + memPowerSpec.idd2p12 = Configuration::getInstance().memSpec->iDD2P12; + memPowerSpec.idd2n = Configuration::getInstance().memSpec->iDD2N; + memPowerSpec.idd2n2 = Configuration::getInstance().memSpec->iDD2N2; + memPowerSpec.idd3p0 = Configuration::getInstance().memSpec->iDD3P0; + memPowerSpec.idd3p02 = Configuration::getInstance().memSpec->iDD3P02; + memPowerSpec.idd3p1 = Configuration::getInstance().memSpec->iDD3P1; + memPowerSpec.idd3p12 = Configuration::getInstance().memSpec->iDD3P12; + memPowerSpec.idd3n = Configuration::getInstance().memSpec->iDD3N; + memPowerSpec.idd3n2 = Configuration::getInstance().memSpec->iDD3N2; + memPowerSpec.idd4r = Configuration::getInstance().memSpec->iDD4R; + memPowerSpec.idd4r2 = Configuration::getInstance().memSpec->iDD4R2; + memPowerSpec.idd4w = Configuration::getInstance().memSpec->iDD4W; + memPowerSpec.idd4w2 = Configuration::getInstance().memSpec->iDD4W2; + memPowerSpec.idd5 = Configuration::getInstance().memSpec->iDD5; + memPowerSpec.idd52 = Configuration::getInstance().memSpec->iDD52; + memPowerSpec.idd6 = Configuration::getInstance().memSpec->iDD6; + memPowerSpec.idd62 = Configuration::getInstance().memSpec->iDD62; + memPowerSpec.vdd = Configuration::getInstance().memSpec->vDD; + memPowerSpec.vdd2 = Configuration::getInstance().memSpec->vDD2; MemorySpecification memSpec; - memSpec.id = Configuration::getInstance().memSpec.MemoryId; - memSpec.memoryType = Configuration::getInstance().memSpec.MemoryType; + memSpec.id = Configuration::getInstance().memSpec->MemoryId; + memSpec.memoryType = Configuration::getInstance().memSpec->MemoryType; memSpec.memTimingSpec = memTimingSpec; memSpec.memPowerSpec = memPowerSpec; memSpec.memArchSpec = memArchSpec; @@ -202,7 +202,7 @@ Dram::Dram(sc_module_name) : tSocket("socket") // For each bank in a channel a error Model is created: if (StoreMode == StorageMode::ErrorModel) { - for (unsigned i = 0; i < Configuration::getInstance().memSpec.NumberOfBanks; + for (unsigned i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; i++) { errorModel *em; @@ -242,9 +242,9 @@ Dram::~Dram() // Bandwidth: sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec.BurstLength - / Configuration::getInstance().memSpec.DataRate - * Configuration::getInstance().memSpec.clk; + * Configuration::getInstance().memSpec->BurstLength + / Configuration::getInstance().memSpec->DataRate + * Configuration::getInstance().memSpec->clk; sc_time idleTime = dramController->getIdleTime(); sc_time endTime = dramController->getEndTime(); @@ -255,11 +255,11 @@ Dram::~Dram() double maxBandwidth = ( // clk in Mhz e.g. 800 [MHz]: - (1000000 / Configuration::getInstance().memSpec.clk.to_double()) + (1000000 / Configuration::getInstance().memSpec->clk.to_double()) // DataRate e.g. 2 - * Configuration::getInstance().memSpec.DataRate + * Configuration::getInstance().memSpec->DataRate // BusWidth e.g. 8 or 64 - * Configuration::getInstance().memSpec.bitWidth + * Configuration::getInstance().memSpec->bitWidth // Number of devices on a DIMM e.g. 8 * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); @@ -303,7 +303,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (powerAnalysis) { cycle = sc_time_stamp().value() / - Configuration::getInstance().memSpec.clk.value(); + Configuration::getInstance().memSpec->clk.value(); } if (phase == BEGIN_PREB) diff --git a/DRAMSys/library/src/simulation/RecordableDram.cpp b/DRAMSys/library/src/simulation/RecordableDram.cpp index 7ba789ef..295cac31 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.cpp +++ b/DRAMSys/library/src/simulation/RecordableDram.cpp @@ -105,7 +105,7 @@ void RecordableDram::powerWindow() wait(powerWindowSize); clk_cycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec.clk.value(); + Configuration::getInstance().memSpec->clk.value(); DRAMPower->calcWindowEnergy(clk_cycles); diff --git a/DRAMSys/library/src/simulation/RecordableDram.h b/DRAMSys/library/src/simulation/RecordableDram.h index 191fc868..a362f2cc 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.h +++ b/DRAMSys/library/src/simulation/RecordableDram.h @@ -56,7 +56,7 @@ protected: private: TlmRecorder *tlmRecorder; - sc_time powerWindowSize = Configuration::getInstance().memSpec.clk * + sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * Configuration::getInstance().WindowSize; // When working with floats, we have to decide ourselves what is an diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index b8e23bbd..cace8884 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -61,7 +61,7 @@ public: SC_REPORT_FATAL(0, (string("Could not open trace ") + pathToTrace).c_str()); this->playerClk = playerClk; - this->burstlength = Configuration::getInstance().memSpec.BurstLength; + this->burstlength = Configuration::getInstance().memSpec->BurstLength; this->dataLength = Configuration::getInstance().getBytesPerBurst(); this->lineCnt = 0; } diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index 7a1ebec4..c6e5cd12 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -50,11 +50,11 @@ public: TracePlayerListener *listener) : TracePlayer(listener), transCounter(0) { if (clkMhz == 0) - clk = Configuration::getInstance().memSpec.clk; + clk = Configuration::getInstance().memSpec->clk; else clk = FrequencyToClk(clkMhz); - this->burstlenght = Configuration::getInstance().memSpec.BurstLength; + this->burstlenght = Configuration::getInstance().memSpec->BurstLength; } virtual void nextPayload() override From 388a2623af0ae1e3e7d4b8b1e2211f90351217fc Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 18 Jun 2019 10:52:04 +0200 Subject: [PATCH 19/30] Preparation for merge with master. --- DRAMSys/library/resources/configs/simulator/ddr3.xml | 2 +- DRAMSys/library/src/controller/Controller.cpp | 4 +--- DRAMSys/library/src/simulation/Arbiter.cpp | 1 - 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index f43e4b8c..1613737f 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,6 +1,6 @@ - + diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 2623616e..d9bf6d89 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -332,7 +332,7 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, to_string(getTotalNumberOfPayloadsInSystem())); payload.acquire(); payloadEntersSystem(payload); - // TODO: Different queues: Fifo: queue per bank, FifoStrict: queue per channel + if (getTotalNumberOfPayloadsInSystem() > controllerCore->config.MaxNrOfTransactions) { @@ -343,7 +343,6 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, { payload.set_response_status(tlm::TLM_OK_RESPONSE); sendToFrontend(payload, END_REQ, SC_ZERO_TIME); - // tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME) scheduler->storeRequest(&payload); scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); @@ -360,7 +359,6 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, { printDebugMessage("##Backpressure released"); backpressure->set_response_status(tlm::TLM_OK_RESPONSE); - // tSocket->nb_transport_bw(*backpressure, END_REQ, SC_ZERO_TIME) sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME); scheduler->storeRequest(backpressure); diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index b1287f7e..c68927f8 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -66,7 +66,6 @@ Arbiter::Arbiter(sc_module_name /*name*/) : payloadEventQueue(this, &Arbiter::pe tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, tlm_phase &phase, sc_time &fwDelay) { - // TODO: clkAlign necessary? sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) - (sc_time_stamp() + fwDelay); if (phase == BEGIN_REQ) From 8f0e59c85e02a407ffb23caddc2d9244c42abc55 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 19 Jun 2019 11:16:38 +0200 Subject: [PATCH 20/30] Included templates for new DRAMs. --- DRAMSys/library/library.pro | 12 ++++- .../configuration/ConfigurationLoader.cpp | 1 + .../core/configuration/ConfigurationLoader.h | 1 + .../controller/core/configuration/MemSpec.h | 1 + DRAMSys/library/src/simulation/DramDDR3.cpp | 41 ++++++++++++++++ DRAMSys/library/src/simulation/DramDDR3.h | 47 +++++++++++++++++++ DRAMSys/library/src/simulation/DramDDR4.cpp | 6 +++ DRAMSys/library/src/simulation/DramDDR4.h | 12 +++++ .../library/src/simulation/DramRecordable.cpp | 41 ++++++++++++++++ .../library/src/simulation/DramRecordable.h | 46 ++++++++++++++++++ .../src/simulation/DramRecordablePower.cpp | 41 ++++++++++++++++ .../src/simulation/DramRecordablePower.h | 46 ++++++++++++++++++ .../library/src/simulation/RecordableDram.cpp | 8 ++-- .../library/src/simulation/RecordableDram.h | 2 +- 14 files changed, 298 insertions(+), 7 deletions(-) create mode 100644 DRAMSys/library/src/simulation/DramDDR3.cpp create mode 100644 DRAMSys/library/src/simulation/DramDDR3.h create mode 100644 DRAMSys/library/src/simulation/DramDDR4.cpp create mode 100644 DRAMSys/library/src/simulation/DramDDR4.h create mode 100644 DRAMSys/library/src/simulation/DramRecordable.cpp create mode 100644 DRAMSys/library/src/simulation/DramRecordable.h create mode 100644 DRAMSys/library/src/simulation/DramRecordablePower.cpp create mode 100644 DRAMSys/library/src/simulation/DramRecordablePower.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index ab7ca602..6fbf6467 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -143,7 +143,11 @@ SOURCES += \ src/common/XmlAddressDecoder.cpp \ src/controller/core/timingCalculations.cpp \ src/common/dramExtensions.cpp \ - src/common/utils.cpp + src/common/utils.cpp \ + src/simulation/DramDDR3.cpp \ + src/simulation/DramDDR4.cpp \ + src/simulation/DramRecordable.cpp \ + src/simulation/DramRecordablePower.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -220,7 +224,11 @@ HEADERS += \ src/controller/core/timingCalculations.h \ src/common/dramExtensions.h \ src/common/utils.h \ - src/controller/core/configuration/TemperatureSimConfig.h + src/controller/core/configuration/TemperatureSimConfig.h \ + src/simulation/DramDDR3.h \ + src/simulation/DramDDR4.h \ + src/simulation/DramRecordable.h \ + src/simulation/DramRecordablePower.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 79b9965f..def1d129 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -32,6 +32,7 @@ * Authors: * Janik Schlemminger * Matthias Jung + * Lukas Steiner */ #include "ConfigurationLoader.h" diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h index d7a12c57..7a4e0410 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h @@ -32,6 +32,7 @@ * Authors: * Janik Schlemminger * Matthias Jung + * Lukas Steiner */ #ifndef CONFIGURATIONLOADER_H diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index fc4fb576..d13f2701 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -32,6 +32,7 @@ * Authors: * Janik Schlemminger * Matthias Jung + * Lukas Steiner */ #ifndef MEMSPEC_H diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp new file mode 100644 index 00000000..1999d3a5 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramDDR3.h" + +DramDDR3::DramDDR3(sc_module_name name) : Dram(name) +{ + +} diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h new file mode 100644 index 00000000..a64cdeaf --- /dev/null +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMDDR3_H +#define DRAMDDR3_H + +#include "Dram.h" + +class DramDDR3 : public Dram +{ +public: + DramDDR3(sc_module_name); +}; + +#endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp new file mode 100644 index 00000000..1390f29d --- /dev/null +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -0,0 +1,6 @@ +#include "DramDDR4.h" + +DramDDR4::DramDDR4(sc_module_name name) : Dram(name) +{ + +} diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h new file mode 100644 index 00000000..14212125 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -0,0 +1,12 @@ +#ifndef DRAMDDR4_H +#define DRAMDDR4_H + +#include "Dram.h" + +class DramDDR4 : public Dram +{ +public: + DramDDR4(sc_module_name); +}; + +#endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp new file mode 100644 index 00000000..85d9d73a --- /dev/null +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramRecordable.h" + +DramRecordable::DramRecordable() +{ + +} diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h new file mode 100644 index 00000000..cbbfea32 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMRECORDABLE_H +#define DRAMRECORDABLE_H + + +class DramRecordable +{ +public: + DramRecordable(); +}; + +#endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.cpp b/DRAMSys/library/src/simulation/DramRecordablePower.cpp new file mode 100644 index 00000000..c1287cd3 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramRecordablePower.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramRecordablePower.h" + +DramRecordablePower::DramRecordablePower() +{ + +} diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.h b/DRAMSys/library/src/simulation/DramRecordablePower.h new file mode 100644 index 00000000..032022bd --- /dev/null +++ b/DRAMSys/library/src/simulation/DramRecordablePower.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMRECORDABLEPOWER_H +#define DRAMRECORDABLEPOWER_H + + +class DramRecordablePower +{ +public: + DramRecordablePower(); +}; + +#endif // DRAMRECORDABLEPOWER_H diff --git a/DRAMSys/library/src/simulation/RecordableDram.cpp b/DRAMSys/library/src/simulation/RecordableDram.cpp index 295cac31..699f0a74 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.cpp +++ b/DRAMSys/library/src/simulation/RecordableDram.cpp @@ -98,19 +98,19 @@ tlm_sync_enum RecordableDram::nb_transport_fw(tlm_generic_payload &payload, // It estimates the current average power which will be stored in the trace database for visualization purposes. void RecordableDram::powerWindow() { - unsigned long long clk_cycles = 0; + unsigned long long clkCycles = 0; do { // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clk_cycles = sc_time_stamp().value() / + clkCycles = sc_time_stamp().value() / Configuration::getInstance().memSpec->clk.value(); - DRAMPower->calcWindowEnergy(clk_cycles); + DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!is_equal(DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database recordPower(); diff --git a/DRAMSys/library/src/simulation/RecordableDram.h b/DRAMSys/library/src/simulation/RecordableDram.h index a362f2cc..0434177a 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.h +++ b/DRAMSys/library/src/simulation/RecordableDram.h @@ -62,7 +62,7 @@ private: // When working with floats, we have to decide ourselves what is an // acceptable definition for "equal". Here the number is compared with a // suitable error margin (0.00001). - bool is_equal(double a, double b, const double epsilon = 1e-05) + bool isEqual(double a, double b, const double epsilon = 1e-05) { return std::fabs(a - b) < epsilon; } From d69cb555ac5ba564439d93ad63907f0a51485b74 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 19 Jun 2019 13:59:01 +0200 Subject: [PATCH 21/30] Templating for DRAMs is working. --- DRAMSys/library/src/simulation/DRAMSys.cpp | 9 ++++- DRAMSys/library/src/simulation/DramDDR3.cpp | 1 + DRAMSys/library/src/simulation/DramDDR3.h | 1 + DRAMSys/library/src/simulation/DramDDR4.cpp | 36 +++++++++++++++++++ DRAMSys/library/src/simulation/DramDDR4.h | 1 + .../library/src/simulation/DramRecordable.cpp | 8 ++++- .../library/src/simulation/DramRecordable.h | 10 ++++-- .../src/simulation/DramRecordablePower.cpp | 8 ++++- .../src/simulation/DramRecordablePower.h | 8 +++-- 9 files changed, 75 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index ee5b7c51..563c2a41 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -54,6 +54,10 @@ #include "../simulation/TemperatureController.h" #include "../controller/Controller.h" #include "../error/ecchamming.h" +#include "DramRecordable.h" +#include "DramRecordablePower.h" +#include "DramDDR3.h" +#include "RecordableDram.h" using namespace std; @@ -240,6 +244,8 @@ void DRAMSys::instantiateModules(const string &traceName, // Create arbiter arbiter = new Arbiter("arbiter"); + std::string testString = "test"; + //DramRecordable testDram(testString.c_str(), tlmRecorders[0]); // Create DRAM for (size_t i = 0; @@ -257,7 +263,8 @@ void DRAMSys::instantiateModules(const string &traceName, str = "dram" + std::to_string(i); Dram *dram; if (recordingEnabled) - dram = new RecordableDram(str.c_str(), tlmRecorders[i]); + //dram = new RecordableDram(str.c_str(), tlmRecorders[i]); + dram = new DramRecordablePower(str.c_str(), tlmRecorders[i]); else dram = new Dram(str.c_str()); drams.push_back(dram); diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 1999d3a5..416f7c63 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -34,6 +34,7 @@ */ #include "DramDDR3.h" +#include "Dram.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index a64cdeaf..c1aa87ca 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -42,6 +42,7 @@ class DramDDR3 : public Dram { public: DramDDR3(sc_module_name); + SC_HAS_PROCESS(DramDDR3); }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 1390f29d..4eb6bb39 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -1,4 +1,40 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + #include "DramDDR4.h" +#include "Dram.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index 14212125..855a3aaf 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -7,6 +7,7 @@ class DramDDR4 : public Dram { public: DramDDR4(sc_module_name); + SC_HAS_PROCESS(DramDDR4); }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 85d9d73a..9b1fec3c 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -34,8 +34,14 @@ */ #include "DramRecordable.h" +#include "RecordableDram.h" -DramRecordable::DramRecordable() +template +DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder) + : BaseDram(name, tlmRecorder) { } + +template class DramRecordable; + diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index cbbfea32..95139b1f 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -36,11 +36,17 @@ #ifndef DRAMRECORDABLE_H #define DRAMRECORDABLE_H +#include "DramDDR3.h" +#include "DramDDR4.h" +#include "RecordableDram.h" +#include "../common/TlmRecorder.h" -class DramRecordable +template +class DramRecordable : public BaseDram { public: - DramRecordable(); + DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder); + SC_HAS_PROCESS(DramRecordable); }; #endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.cpp b/DRAMSys/library/src/simulation/DramRecordablePower.cpp index c1287cd3..bc855e77 100644 --- a/DRAMSys/library/src/simulation/DramRecordablePower.cpp +++ b/DRAMSys/library/src/simulation/DramRecordablePower.cpp @@ -34,8 +34,14 @@ */ #include "DramRecordablePower.h" +#include "RecordableDram.h" -DramRecordablePower::DramRecordablePower() +template +DramRecordablePower::DramRecordablePower + (sc_module_name name, TlmRecorder *tlmRecorder) + : DramRecordable(name, tlmRecorder) { } + +template class DramRecordablePower; diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.h b/DRAMSys/library/src/simulation/DramRecordablePower.h index 032022bd..b38dacb2 100644 --- a/DRAMSys/library/src/simulation/DramRecordablePower.h +++ b/DRAMSys/library/src/simulation/DramRecordablePower.h @@ -36,11 +36,15 @@ #ifndef DRAMRECORDABLEPOWER_H #define DRAMRECORDABLEPOWER_H +#include "DramRecordable.h" +#include "../common/TlmRecorder.h" -class DramRecordablePower +template +class DramRecordablePower : public DramRecordable { public: - DramRecordablePower(); + DramRecordablePower(sc_module_name name, TlmRecorder *tlmRecorder); + SC_HAS_PROCESS(DramRecordablePower); }; #endif // DRAMRECORDABLEPOWER_H From 27fed220035e89af0a039e1e0036f9369b6df0c1 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 22 Jun 2019 20:49:57 +0200 Subject: [PATCH 22/30] Revert "Templating for DRAMs is working." This reverts commit d69cb555ac5ba564439d93ad63907f0a51485b74. --- DRAMSys/library/src/simulation/DRAMSys.cpp | 9 +---- DRAMSys/library/src/simulation/DramDDR3.cpp | 1 - DRAMSys/library/src/simulation/DramDDR3.h | 1 - DRAMSys/library/src/simulation/DramDDR4.cpp | 36 ------------------- DRAMSys/library/src/simulation/DramDDR4.h | 1 - .../library/src/simulation/DramRecordable.cpp | 8 +---- .../library/src/simulation/DramRecordable.h | 10 ++---- .../src/simulation/DramRecordablePower.cpp | 8 +---- .../src/simulation/DramRecordablePower.h | 8 ++--- 9 files changed, 7 insertions(+), 75 deletions(-) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 563c2a41..ee5b7c51 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -54,10 +54,6 @@ #include "../simulation/TemperatureController.h" #include "../controller/Controller.h" #include "../error/ecchamming.h" -#include "DramRecordable.h" -#include "DramRecordablePower.h" -#include "DramDDR3.h" -#include "RecordableDram.h" using namespace std; @@ -244,8 +240,6 @@ void DRAMSys::instantiateModules(const string &traceName, // Create arbiter arbiter = new Arbiter("arbiter"); - std::string testString = "test"; - //DramRecordable testDram(testString.c_str(), tlmRecorders[0]); // Create DRAM for (size_t i = 0; @@ -263,8 +257,7 @@ void DRAMSys::instantiateModules(const string &traceName, str = "dram" + std::to_string(i); Dram *dram; if (recordingEnabled) - //dram = new RecordableDram(str.c_str(), tlmRecorders[i]); - dram = new DramRecordablePower(str.c_str(), tlmRecorders[i]); + dram = new RecordableDram(str.c_str(), tlmRecorders[i]); else dram = new Dram(str.c_str()); drams.push_back(dram); diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 416f7c63..1999d3a5 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -34,7 +34,6 @@ */ #include "DramDDR3.h" -#include "Dram.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index c1aa87ca..a64cdeaf 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -42,7 +42,6 @@ class DramDDR3 : public Dram { public: DramDDR3(sc_module_name); - SC_HAS_PROCESS(DramDDR3); }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 4eb6bb39..1390f29d 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -1,40 +1,4 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - #include "DramDDR4.h" -#include "Dram.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index 855a3aaf..14212125 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -7,7 +7,6 @@ class DramDDR4 : public Dram { public: DramDDR4(sc_module_name); - SC_HAS_PROCESS(DramDDR4); }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 9b1fec3c..85d9d73a 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -34,14 +34,8 @@ */ #include "DramRecordable.h" -#include "RecordableDram.h" -template -DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder) - : BaseDram(name, tlmRecorder) +DramRecordable::DramRecordable() { } - -template class DramRecordable; - diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index 95139b1f..cbbfea32 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -36,17 +36,11 @@ #ifndef DRAMRECORDABLE_H #define DRAMRECORDABLE_H -#include "DramDDR3.h" -#include "DramDDR4.h" -#include "RecordableDram.h" -#include "../common/TlmRecorder.h" -template -class DramRecordable : public BaseDram +class DramRecordable { public: - DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder); - SC_HAS_PROCESS(DramRecordable); + DramRecordable(); }; #endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.cpp b/DRAMSys/library/src/simulation/DramRecordablePower.cpp index bc855e77..c1287cd3 100644 --- a/DRAMSys/library/src/simulation/DramRecordablePower.cpp +++ b/DRAMSys/library/src/simulation/DramRecordablePower.cpp @@ -34,14 +34,8 @@ */ #include "DramRecordablePower.h" -#include "RecordableDram.h" -template -DramRecordablePower::DramRecordablePower - (sc_module_name name, TlmRecorder *tlmRecorder) - : DramRecordable(name, tlmRecorder) +DramRecordablePower::DramRecordablePower() { } - -template class DramRecordablePower; diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.h b/DRAMSys/library/src/simulation/DramRecordablePower.h index b38dacb2..032022bd 100644 --- a/DRAMSys/library/src/simulation/DramRecordablePower.h +++ b/DRAMSys/library/src/simulation/DramRecordablePower.h @@ -36,15 +36,11 @@ #ifndef DRAMRECORDABLEPOWER_H #define DRAMRECORDABLEPOWER_H -#include "DramRecordable.h" -#include "../common/TlmRecorder.h" -template -class DramRecordablePower : public DramRecordable +class DramRecordablePower { public: - DramRecordablePower(sc_module_name name, TlmRecorder *tlmRecorder); - SC_HAS_PROCESS(DramRecordablePower); + DramRecordablePower(); }; #endif // DRAMRECORDABLEPOWER_H From 882a0eaa90e78529e44eec9c86f2363b8bddc1b1 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 22 Jun 2019 20:50:07 +0200 Subject: [PATCH 23/30] Revert "Included templates for new DRAMs." This reverts commit 8f0e59c85e02a407ffb23caddc2d9244c42abc55. --- DRAMSys/library/library.pro | 12 +---- .../configuration/ConfigurationLoader.cpp | 1 - .../core/configuration/ConfigurationLoader.h | 1 - .../controller/core/configuration/MemSpec.h | 1 - DRAMSys/library/src/simulation/DramDDR3.cpp | 41 ---------------- DRAMSys/library/src/simulation/DramDDR3.h | 47 ------------------- DRAMSys/library/src/simulation/DramDDR4.cpp | 6 --- DRAMSys/library/src/simulation/DramDDR4.h | 12 ----- .../library/src/simulation/DramRecordable.cpp | 41 ---------------- .../library/src/simulation/DramRecordable.h | 46 ------------------ .../src/simulation/DramRecordablePower.cpp | 41 ---------------- .../src/simulation/DramRecordablePower.h | 46 ------------------ .../library/src/simulation/RecordableDram.cpp | 8 ++-- .../library/src/simulation/RecordableDram.h | 2 +- 14 files changed, 7 insertions(+), 298 deletions(-) delete mode 100644 DRAMSys/library/src/simulation/DramDDR3.cpp delete mode 100644 DRAMSys/library/src/simulation/DramDDR3.h delete mode 100644 DRAMSys/library/src/simulation/DramDDR4.cpp delete mode 100644 DRAMSys/library/src/simulation/DramDDR4.h delete mode 100644 DRAMSys/library/src/simulation/DramRecordable.cpp delete mode 100644 DRAMSys/library/src/simulation/DramRecordable.h delete mode 100644 DRAMSys/library/src/simulation/DramRecordablePower.cpp delete mode 100644 DRAMSys/library/src/simulation/DramRecordablePower.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 6fbf6467..ab7ca602 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -143,11 +143,7 @@ SOURCES += \ src/common/XmlAddressDecoder.cpp \ src/controller/core/timingCalculations.cpp \ src/common/dramExtensions.cpp \ - src/common/utils.cpp \ - src/simulation/DramDDR3.cpp \ - src/simulation/DramDDR4.cpp \ - src/simulation/DramRecordable.cpp \ - src/simulation/DramRecordablePower.cpp + src/common/utils.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -224,11 +220,7 @@ HEADERS += \ src/controller/core/timingCalculations.h \ src/common/dramExtensions.h \ src/common/utils.h \ - src/controller/core/configuration/TemperatureSimConfig.h \ - src/simulation/DramDDR3.h \ - src/simulation/DramDDR4.h \ - src/simulation/DramRecordable.h \ - src/simulation/DramRecordablePower.h + src/controller/core/configuration/TemperatureSimConfig.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index def1d129..79b9965f 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -32,7 +32,6 @@ * Authors: * Janik Schlemminger * Matthias Jung - * Lukas Steiner */ #include "ConfigurationLoader.h" diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h index 7a4e0410..d7a12c57 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h @@ -32,7 +32,6 @@ * Authors: * Janik Schlemminger * Matthias Jung - * Lukas Steiner */ #ifndef CONFIGURATIONLOADER_H diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index d13f2701..fc4fb576 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -32,7 +32,6 @@ * Authors: * Janik Schlemminger * Matthias Jung - * Lukas Steiner */ #ifndef MEMSPEC_H diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp deleted file mode 100644 index 1999d3a5..00000000 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#include "DramDDR3.h" - -DramDDR3::DramDDR3(sc_module_name name) : Dram(name) -{ - -} diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h deleted file mode 100644 index a64cdeaf..00000000 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#ifndef DRAMDDR3_H -#define DRAMDDR3_H - -#include "Dram.h" - -class DramDDR3 : public Dram -{ -public: - DramDDR3(sc_module_name); -}; - -#endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp deleted file mode 100644 index 1390f29d..00000000 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ /dev/null @@ -1,6 +0,0 @@ -#include "DramDDR4.h" - -DramDDR4::DramDDR4(sc_module_name name) : Dram(name) -{ - -} diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h deleted file mode 100644 index 14212125..00000000 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef DRAMDDR4_H -#define DRAMDDR4_H - -#include "Dram.h" - -class DramDDR4 : public Dram -{ -public: - DramDDR4(sc_module_name); -}; - -#endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp deleted file mode 100644 index 85d9d73a..00000000 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#include "DramRecordable.h" - -DramRecordable::DramRecordable() -{ - -} diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h deleted file mode 100644 index cbbfea32..00000000 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#ifndef DRAMRECORDABLE_H -#define DRAMRECORDABLE_H - - -class DramRecordable -{ -public: - DramRecordable(); -}; - -#endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.cpp b/DRAMSys/library/src/simulation/DramRecordablePower.cpp deleted file mode 100644 index c1287cd3..00000000 --- a/DRAMSys/library/src/simulation/DramRecordablePower.cpp +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#include "DramRecordablePower.h" - -DramRecordablePower::DramRecordablePower() -{ - -} diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.h b/DRAMSys/library/src/simulation/DramRecordablePower.h deleted file mode 100644 index 032022bd..00000000 --- a/DRAMSys/library/src/simulation/DramRecordablePower.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#ifndef DRAMRECORDABLEPOWER_H -#define DRAMRECORDABLEPOWER_H - - -class DramRecordablePower -{ -public: - DramRecordablePower(); -}; - -#endif // DRAMRECORDABLEPOWER_H diff --git a/DRAMSys/library/src/simulation/RecordableDram.cpp b/DRAMSys/library/src/simulation/RecordableDram.cpp index 699f0a74..295cac31 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.cpp +++ b/DRAMSys/library/src/simulation/RecordableDram.cpp @@ -98,19 +98,19 @@ tlm_sync_enum RecordableDram::nb_transport_fw(tlm_generic_payload &payload, // It estimates the current average power which will be stored in the trace database for visualization purposes. void RecordableDram::powerWindow() { - unsigned long long clkCycles = 0; + unsigned long long clk_cycles = 0; do { // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clkCycles = sc_time_stamp().value() / + clk_cycles = sc_time_stamp().value() / Configuration::getInstance().memSpec->clk.value(); - DRAMPower->calcWindowEnergy(clkCycles); + DRAMPower->calcWindowEnergy(clk_cycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); + assert(!is_equal(DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database recordPower(); diff --git a/DRAMSys/library/src/simulation/RecordableDram.h b/DRAMSys/library/src/simulation/RecordableDram.h index 0434177a..a362f2cc 100644 --- a/DRAMSys/library/src/simulation/RecordableDram.h +++ b/DRAMSys/library/src/simulation/RecordableDram.h @@ -62,7 +62,7 @@ private: // When working with floats, we have to decide ourselves what is an // acceptable definition for "equal". Here the number is compared with a // suitable error margin (0.00001). - bool isEqual(double a, double b, const double epsilon = 1e-05) + bool is_equal(double a, double b, const double epsilon = 1e-05) { return std::fabs(a - b) < epsilon; } From c3da6912a95db4f2c548263988fbf88de279e0c4 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 22 Jun 2019 21:49:18 +0200 Subject: [PATCH 24/30] Further renaming of schedulers. --- .../library/resources/configs/mcconfigs/fifo.xml | 2 +- .../resources/configs/mcconfigs/fifoStrict.xml | 2 +- .../resources/configs/mcconfigs/fifo_ecc.xml | 2 +- .../resources/configs/mcconfigs/fr_fcfs.xml | 2 +- .../resources/configs/mcconfigs/fr_fcfs_grp.xml | 2 +- .../resources/configs/mcconfigs/fr_fcfs_rp.xml | 2 +- .../library/resources/configs/mcconfigs/grp.xml | 2 +- .../resources/configs/mcconfigs/rgrmccfg.xml | 2 +- DRAMSys/library/src/controller/Controller.cpp | 12 ++++++------ .../library/src/controller/scheduler/FrFcfs.cpp | 4 ++-- DRAMSys/traceAnalyzer/scripts/tests.py | 4 ++-- README.md | 14 +++++++++----- 12 files changed, 27 insertions(+), 23 deletions(-) diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml index 73231bba..d01b9248 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml index dee4f5d4..ed869b57 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml index 73231bba..d01b9248 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml index e5a6579e..20db08cd 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml index 75570d40..dad77bf6 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml index 5a9f1c0c..3f636ba0 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/grp.xml b/DRAMSys/library/resources/configs/mcconfigs/grp.xml index a62969fb..753cca46 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/grp.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml index bb8b64ae..b17e59ce 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index d9bf6d89..1fac6814 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -103,17 +103,17 @@ void Controller::buildScheduler() { string selectedScheduler = Configuration::getInstance().Scheduler; - if (selectedScheduler == "FIFO") { + if (selectedScheduler == "Fifo") { scheduler = new Fifo(*controllerCore); - } else if (selectedScheduler == "FIFO_STRICT") { + } else if (selectedScheduler == "FifoStrict") { scheduler = new FifoStrict(*this, *controllerCore); - } else if (selectedScheduler == "FR_FCFS") { + } else if (selectedScheduler == "FrFcfs") { scheduler = new FrFcfs(*controllerCore); - } else if (selectedScheduler == "FR_FCFS_RP") { + } else if (selectedScheduler == "FrFcfsRp") { scheduler = new FrFcfsRp(*controllerCore); - } else if (selectedScheduler == "FR_FCFS_GRP") { + } else if (selectedScheduler == "FrFcfsGrp") { scheduler = new FrFcfsGrp(*controllerCore, this); - } else if (selectedScheduler == "GRP") { + } else if (selectedScheduler == "Grp") { scheduler = new Grp(*controllerCore, this); } else if (selectedScheduler == "SMS") { scheduler = new SMS("SMS", *controllerCore, diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp index afa12aa2..c0d742af 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp @@ -73,7 +73,7 @@ std::pair FrFcfs::getNextRequest(Bank bank) if (buffer[bank].empty()) return std::pair(Command::NOP, NULL); - // In FR_FCFS row hits have always the highest priority, therefore we search + // In FrFcfs row hits have always the highest priority, therefore we search // for row hits. If we find a row hit, we remove the transaction from the // queue and send it to the DRAM. std::deque::iterator it = findRowHit(bank); @@ -84,7 +84,7 @@ std::pair FrFcfs::getNextRequest(Bank bank) return std::pair(getReadWriteCommand(payload), payload); } - // If there is no row hit, the FR_FCFS takes always the oldest transaction + // If there is no row hit, the FrFcfs takes always the oldest transaction // in the buffer, i.e. the transaction in the front. return std::pair(getNextCommand(buffer[bank].front()), buffer[bank].front()); diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index 260853eb..2d3becd9 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -713,10 +713,10 @@ def strict_transaction_order(connection): transactions += str(currentRow[0]) + "," if (transactions != ""): - if (dramconfig.scheduler == "FIFO_STRICT"): + if (dramconfig.scheduler == "FifoStrict"): return TestFailed("Transactions {0} is/are not in Order ".format(transactions)) else: - return TestResult(True, "Transactions are not in Order, however this is okay since no FIFO_STRICT was choosen") + return TestResult(True, "Transactions are not in Order, however this is okay since no FifoStrict was choosen") return TestSuceeded() # ----------- powerdown checks --------------------------------------- diff --git a/README.md b/README.md index c23d501e..42b094de 100644 --- a/README.md +++ b/README.md @@ -706,7 +706,7 @@ Below, the sub-configurations are listed and explained. - + @@ -764,9 +764,13 @@ Below, the sub-configurations are listed and explained. - *MaxNrOfTransactions* (unsigned int) - Maximum number of transactions. - *Scheduler* (string) - - "FIFO": first in, first out - - "FIFO_STRICT": out-of-order treatment of queue elements not allowed - - "FR_FCFS": first-come, first-served + - "Fifo": first in, first out + - "FifoStrict": out-of-order treatment of queue elements not allowed + - "FrFcfs": first ready first-come-first-served + - "FrFcfsRp": first ready first-come-first-served read priority + - "FrFcfsGrp": first ready first-come-first-served grouper + - "Grp": grouper + - "SMS": will be removed - *Capsize* (unsigned int) - Capacitor cell size. - *PowerDownMode* (enum EPowerDownMode) @@ -1410,7 +1414,7 @@ Enable the error model in fr_fcfs.xml. - + From cff2455be255f2042e0fd250d3fa5ded3fc1693e Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 22 Jun 2019 22:08:00 +0200 Subject: [PATCH 25/30] Bugfix for failing tests: missing renaming. --- DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml | 2 +- DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml | 2 +- DRAMSys/tests/TLM_compliance/fifoStrict.xml | 2 +- DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml | 2 +- DRAMSys/tests/error/fr_fcfs.xml | 2 +- DRAMSys/tests/simple/fifoStrict.xml | 2 +- DRAMSys/tests/timing_compliance/fifoStrict.xml | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml index dee4f5d4..ed869b57 100644 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml index e5a6579e..20db08cd 100644 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/tests/TLM_compliance/fifoStrict.xml b/DRAMSys/tests/TLM_compliance/fifoStrict.xml index d5814755..440f465a 100644 --- a/DRAMSys/tests/TLM_compliance/fifoStrict.xml +++ b/DRAMSys/tests/TLM_compliance/fifoStrict.xml @@ -2,7 +2,7 @@ - + diff --git a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml index dee4f5d4..ed869b57 100644 --- a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/tests/error/fr_fcfs.xml b/DRAMSys/tests/error/fr_fcfs.xml index c2861799..9066796c 100644 --- a/DRAMSys/tests/error/fr_fcfs.xml +++ b/DRAMSys/tests/error/fr_fcfs.xml @@ -2,7 +2,7 @@ - + diff --git a/DRAMSys/tests/simple/fifoStrict.xml b/DRAMSys/tests/simple/fifoStrict.xml index 43744c7d..247c4de3 100644 --- a/DRAMSys/tests/simple/fifoStrict.xml +++ b/DRAMSys/tests/simple/fifoStrict.xml @@ -2,7 +2,7 @@ - + diff --git a/DRAMSys/tests/timing_compliance/fifoStrict.xml b/DRAMSys/tests/timing_compliance/fifoStrict.xml index 2c84267e..fc213074 100644 --- a/DRAMSys/tests/timing_compliance/fifoStrict.xml +++ b/DRAMSys/tests/timing_compliance/fifoStrict.xml @@ -2,7 +2,7 @@ - + From cb7b5b585ad238d97d8064eedd07dad41a336360 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Sun, 23 Jun 2019 19:10:28 +0200 Subject: [PATCH 26/30] NOT RUNNING! Adapting current DRAM to new structure. --- DRAMSys/library/library.pro | 6 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 3 +- DRAMSys/library/src/simulation/DramDDR3.h | 2 + DRAMSys/library/src/simulation/DramDDR4.h | 6 ++ .../library/src/simulation/DramRecordable.cpp | 96 ++++++++++++++++++- .../library/src/simulation/DramRecordable.h | 29 ++++++ .../src/simulation/DramRecordablePower.cpp | 47 --------- .../src/simulation/DramRecordablePower.h | 50 ---------- 8 files changed, 132 insertions(+), 107 deletions(-) delete mode 100644 DRAMSys/library/src/simulation/DramRecordablePower.cpp delete mode 100644 DRAMSys/library/src/simulation/DramRecordablePower.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 6fbf6467..dabae60c 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -146,8 +146,7 @@ SOURCES += \ src/common/utils.cpp \ src/simulation/DramDDR3.cpp \ src/simulation/DramDDR4.cpp \ - src/simulation/DramRecordable.cpp \ - src/simulation/DramRecordablePower.cpp + src/simulation/DramRecordable.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -227,8 +226,7 @@ HEADERS += \ src/controller/core/configuration/TemperatureSimConfig.h \ src/simulation/DramDDR3.h \ src/simulation/DramDDR4.h \ - src/simulation/DramRecordable.h \ - src/simulation/DramRecordablePower.h + src/simulation/DramRecordable.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 563c2a41..61fbfc63 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -55,7 +55,6 @@ #include "../controller/Controller.h" #include "../error/ecchamming.h" #include "DramRecordable.h" -#include "DramRecordablePower.h" #include "DramDDR3.h" #include "RecordableDram.h" @@ -264,7 +263,7 @@ void DRAMSys::instantiateModules(const string &traceName, Dram *dram; if (recordingEnabled) //dram = new RecordableDram(str.c_str(), tlmRecorders[i]); - dram = new DramRecordablePower(str.c_str(), tlmRecorders[i]); + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); else dram = new Dram(str.c_str()); drams.push_back(dram); diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index c1aa87ca..894809bb 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -43,6 +43,8 @@ class DramDDR3 : public Dram public: DramDDR3(sc_module_name); SC_HAS_PROCESS(DramDDR3); + + ~DramDDR3(); }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index 855a3aaf..ed884bc1 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -2,12 +2,18 @@ #define DRAMDDR4_H #include "Dram.h" +#include "systemc" +#include "tlm" + +using namespace tlm; class DramDDR4 : public Dram { public: DramDDR4(sc_module_name); SC_HAS_PROCESS(DramDDR4); + + ~DramDDR4(); }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 9b1fec3c..d7312d5c 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -34,14 +34,102 @@ */ #include "DramRecordable.h" -#include "RecordableDram.h" +#include "Dram.h" + +using namespace tlm; template DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder) - : BaseDram(name, tlmRecorder) + : BaseDram(name), tlmRecorder(tlmRecorder) { - + // Create a thread that is triggered every $powerWindowSize + // to generate a Power over Time plot in the Trace analyzer: + SC_THREAD(powerWindow); } -template class DramRecordable; +template +DramRecordable::~DramRecordable() +{ + BaseDram::DRAMPower->calcEnergy(); + recordPower(); + tlmRecorder->closeConnection(); +} + +template +tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay) +{ + // Recording time used by the traceAnalyzer + sc_time recTime = sc_time_stamp() + delay; + + // These are terminating phases recorded by the DRAM. The execution + // time of the related command must be taken into consideration. + if (phase == END_PDNA || phase == END_PDNAB) + recTime += getExecutionTime(Command::PDNAX, payload); + else if (phase == END_PDNP || phase == END_PDNPB) + recTime += getExecutionTime(Command::PDNPX, payload); + else if (phase == END_SREF || phase == END_SREFB) + recTime += getExecutionTime(Command::SREFX, payload); + + unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); + unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); + unsigned int bg = DramExtension::getExtension(payload).getBankGroup().ID(); + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); + + // TODO: printDebugMessage not inherited + printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( + bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + + to_string(col) + " at " + recTime.to_string()); + + tlmRecorder->recordPhase(payload, phase, recTime); + + return BaseDram::nb_transport_fw(payload, phase, delay); +} + +// This Thread is only triggered when Power Simulation is enabled. +// It estimates the current average power which will be stored in the trace database for visualization purposes. +template +void DramRecordable::powerWindow() +{ + unsigned long long clkCycles = 0; + + do { + // At the very beginning (zero clock cycles) the energy is 0, so we wait first + wait(powerWindowSize); + + clkCycles = sc_time_stamp().value() / + Configuration::getInstance().memSpec->clk.value(); + + DRAMPower->calcWindowEnergy(clkCycles); + + // During operation the energy should never be zero since the device is always consuming + assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); + + // Store the time (in seconds) and the current average power (in mW) into the database + recordPower(); + + // Here considering that DRAMPower provides the energy in pJ and the power in mW + printDebugMessage(string("\tWindow Energy: \t") + to_string( + DRAMPower->getEnergy().window_energy * + Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); + printDebugMessage(string("\tWindow Average Power: \t") + to_string( + DRAMPower->getPower().window_average_power * + Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); + + } while (true); +} + +template +void DramRecordable::recordPower() +{ + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + DRAMPower->getPower().window_average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM); +} + + +template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index 95139b1f..2e4231ff 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -36,17 +36,46 @@ #ifndef DRAMRECORDABLE_H #define DRAMRECORDABLE_H +#include +#include #include "DramDDR3.h" #include "DramDDR4.h" #include "RecordableDram.h" #include "../common/TlmRecorder.h" +using namespace tlm; + template class DramRecordable : public BaseDram { public: DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder); SC_HAS_PROCESS(DramRecordable); + + ~DramRecordable(); + +protected: + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay); + +private: + TlmRecorder *tlmRecorder; + sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * + Configuration::getInstance().WindowSize; + + // When working with floats, we have to decide ourselves what is an + // acceptable definition for "equal". Here the number is compared with a + // suitable error margin (0.00001). + bool isEqual(double a, double b, const double epsilon = 1e-05) + { + return std::fabs(a - b) < epsilon; + } + + // This Thread is only triggered when Power Simulation is enabled. + // It estimates the current average power which will be stored in the trace database for visualization purposes. + void powerWindow(); + + void recordPower(); }; #endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.cpp b/DRAMSys/library/src/simulation/DramRecordablePower.cpp deleted file mode 100644 index bc855e77..00000000 --- a/DRAMSys/library/src/simulation/DramRecordablePower.cpp +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#include "DramRecordablePower.h" -#include "RecordableDram.h" - -template -DramRecordablePower::DramRecordablePower - (sc_module_name name, TlmRecorder *tlmRecorder) - : DramRecordable(name, tlmRecorder) -{ - -} - -template class DramRecordablePower; diff --git a/DRAMSys/library/src/simulation/DramRecordablePower.h b/DRAMSys/library/src/simulation/DramRecordablePower.h deleted file mode 100644 index b38dacb2..00000000 --- a/DRAMSys/library/src/simulation/DramRecordablePower.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Lukas Steiner - */ - -#ifndef DRAMRECORDABLEPOWER_H -#define DRAMRECORDABLEPOWER_H - -#include "DramRecordable.h" -#include "../common/TlmRecorder.h" - -template -class DramRecordablePower : public DramRecordable -{ -public: - DramRecordablePower(sc_module_name name, TlmRecorder *tlmRecorder); - SC_HAS_PROCESS(DramRecordablePower); -}; - -#endif // DRAMRECORDABLEPOWER_H From f8baef57c6532a144373a36ed7e7dc77078b1a31 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 23 Jun 2019 20:53:08 +0200 Subject: [PATCH 27/30] Adapting current DRAM to new structure. --- DRAMSys/library/src/simulation/DRAMSys.cpp | 3 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 2 + DRAMSys/library/src/simulation/DramDDR3.h | 4 +- DRAMSys/library/src/simulation/DramDDR4.cpp | 2 + DRAMSys/library/src/simulation/DramDDR4.h | 41 +++++++++++++++++-- .../library/src/simulation/DramRecordable.cpp | 26 +++++++----- 6 files changed, 63 insertions(+), 15 deletions(-) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 61fbfc63..d4e37757 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -56,6 +56,7 @@ #include "../error/ecchamming.h" #include "DramRecordable.h" #include "DramDDR3.h" +#include "DramDDR4.h" #include "RecordableDram.h" using namespace std; @@ -263,7 +264,7 @@ void DRAMSys::instantiateModules(const string &traceName, Dram *dram; if (recordingEnabled) //dram = new RecordableDram(str.c_str(), tlmRecorders[i]); - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); else dram = new Dram(str.c_str()); drams.push_back(dram); diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 416f7c63..91ba5736 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -40,3 +40,5 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { } + +//DramDDR3::~DramDDR3() {} diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index 894809bb..0bf0a8a9 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -37,6 +37,8 @@ #define DRAMDDR3_H #include "Dram.h" +#include +#include class DramDDR3 : public Dram { @@ -44,7 +46,7 @@ public: DramDDR3(sc_module_name); SC_HAS_PROCESS(DramDDR3); - ~DramDDR3(); + //~DramDDR3(); }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 4eb6bb39..b10cd313 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -40,3 +40,5 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { } + +//DramDDR4::~DramDDR4() {} diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index ed884bc1..64bae19d 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -1,9 +1,44 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + #ifndef DRAMDDR4_H #define DRAMDDR4_H #include "Dram.h" -#include "systemc" -#include "tlm" +#include +#include using namespace tlm; @@ -13,7 +48,7 @@ public: DramDDR4(sc_module_name); SC_HAS_PROCESS(DramDDR4); - ~DramDDR4(); + //~DramDDR4(); }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index d7312d5c..e9adc271 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -34,7 +34,12 @@ */ #include "DramRecordable.h" -#include "Dram.h" +#include +#include +#include "../common/TlmRecorder.h" +#include "DramDDR3.h" +#include "DramDDR4.h" +#include "../common/utils.h" using namespace tlm; @@ -79,7 +84,7 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); // TODO: printDebugMessage not inherited - printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + BaseDram::printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + to_string(col) + " at " + recTime.to_string()); @@ -103,20 +108,20 @@ void DramRecordable::powerWindow() clkCycles = sc_time_stamp().value() / Configuration::getInstance().memSpec->clk.value(); - DRAMPower->calcWindowEnergy(clkCycles); + BaseDram::DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(BaseDram::DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database recordPower(); // Here considering that DRAMPower provides the energy in pJ and the power in mW - printDebugMessage(string("\tWindow Energy: \t") + to_string( - DRAMPower->getEnergy().window_energy * + BaseDram::printDebugMessage(string("\tWindow Energy: \t") + to_string( + BaseDram::DRAMPower->getEnergy().window_energy * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); - printDebugMessage(string("\tWindow Average Power: \t") + to_string( - DRAMPower->getPower().window_average_power * + BaseDram::printDebugMessage(string("\tWindow Average Power: \t") + to_string( + BaseDram::DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); } while (true); @@ -126,10 +131,11 @@ template void DramRecordable::recordPower() { tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power + BaseDram::DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM); } -template class DramRecordable; +template class DramRecordable; +template class DramRecordable; From 21c243b9d317d4b0f35733e097e18be5837473a9 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 23 Jun 2019 21:20:21 +0200 Subject: [PATCH 28/30] Replaced "BaseDram::" with "this->" to access members of the base class. --- .../library/src/simulation/DramRecordable.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index e9adc271..56a3196a 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -84,7 +84,7 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); // TODO: printDebugMessage not inherited - BaseDram::printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + this->printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + to_string(col) + " at " + recTime.to_string()); @@ -108,20 +108,20 @@ void DramRecordable::powerWindow() clkCycles = sc_time_stamp().value() / Configuration::getInstance().memSpec->clk.value(); - BaseDram::DRAMPower->calcWindowEnergy(clkCycles); + this->DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(BaseDram::DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(this->DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database recordPower(); // Here considering that DRAMPower provides the energy in pJ and the power in mW - BaseDram::printDebugMessage(string("\tWindow Energy: \t") + to_string( - BaseDram::DRAMPower->getEnergy().window_energy * + this->printDebugMessage(string("\tWindow Energy: \t") + to_string( + this->DRAMPower->getEnergy().window_energy * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); - BaseDram::printDebugMessage(string("\tWindow Average Power: \t") + to_string( - BaseDram::DRAMPower->getPower().window_average_power * + this->printDebugMessage(string("\tWindow Average Power: \t") + to_string( + this->DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); } while (true); @@ -131,7 +131,7 @@ template void DramRecordable::recordPower() { tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - BaseDram::DRAMPower->getPower().window_average_power + this->DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM); } From 45b05c5cf0e0f6bbe6a04d53871505fb74fb928f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 24 Jun 2019 11:59:59 +0200 Subject: [PATCH 29/30] Created DramWideIO, removed powerAnalysis switch. --- DRAMSys/library/library.pro | 6 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 33 +- DRAMSys/library/src/simulation/Dram.cpp | 407 +++++++----------- DRAMSys/library/src/simulation/Dram.h | 11 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 7 +- DRAMSys/library/src/simulation/DramDDR3.h | 2 - DRAMSys/library/src/simulation/DramDDR4.cpp | 7 +- DRAMSys/library/src/simulation/DramDDR4.h | 4 - .../library/src/simulation/DramRecordable.cpp | 2 + .../library/src/simulation/DramRecordable.h | 2 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 251 +++++++++++ DRAMSys/library/src/simulation/DramWideIO.h | 62 +++ 12 files changed, 503 insertions(+), 291 deletions(-) create mode 100644 DRAMSys/library/src/simulation/DramWideIO.cpp create mode 100644 DRAMSys/library/src/simulation/DramWideIO.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index dabae60c..05098c1f 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -146,7 +146,8 @@ SOURCES += \ src/common/utils.cpp \ src/simulation/DramDDR3.cpp \ src/simulation/DramDDR4.cpp \ - src/simulation/DramRecordable.cpp + src/simulation/DramRecordable.cpp \ + src/simulation/DramWideIO.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -226,7 +227,8 @@ HEADERS += \ src/controller/core/configuration/TemperatureSimConfig.h \ src/simulation/DramDDR3.h \ src/simulation/DramDDR4.h \ - src/simulation/DramRecordable.h + src/simulation/DramRecordable.h \ + src/simulation/DramWideIO.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index d4e37757..437c5ff2 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -57,6 +57,7 @@ #include "DramRecordable.h" #include "DramDDR3.h" #include "DramDDR4.h" +#include "DramWideIO.h" #include "RecordableDram.h" using namespace std; @@ -244,10 +245,9 @@ void DRAMSys::instantiateModules(const string &traceName, // Create arbiter arbiter = new Arbiter("arbiter"); - std::string testString = "test"; - //DramRecordable testDram(testString.c_str(), tlmRecorders[0]); // Create DRAM + std::string memoryType = Configuration::getInstance().memSpec->MemoryType; for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) { @@ -262,11 +262,32 @@ void DRAMSys::instantiateModules(const string &traceName, str = "dram" + std::to_string(i); Dram *dram; - if (recordingEnabled) - //dram = new RecordableDram(str.c_str(), tlmRecorders[i]); - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + + if (memoryType == "DDR3") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramDDR3(str.c_str()); + } + else if (memoryType == "DDR4") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramDDR4(str.c_str()); + } + else if (memoryType == "WIDEIO_SDR") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramWideIO(str.c_str()); + } else - dram = new Dram(str.c_str()); + { + SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); + } drams.push_back(dram); if (Configuration::getInstance().CheckTLM2Protocol) { diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 5b6c3901..af3a1594 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -62,180 +62,139 @@ using namespace std; using namespace tlm; using namespace Data; - Dram::Dram(sc_module_name) : tSocket("socket") { // Adjust number of bytes per burst dynamically to the selected ecc controller - bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC( - bytesPerBurst); - - std::uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes(); - if (Configuration::getInstance().UseMalloc) - { - memory = (unsigned char *)malloc(memorySize); - if (!memory) - { - SC_REPORT_FATAL(this->name(), "Memory allocation failed"); - } - } - else - { - // allocate and model storage of one DRAM channel using memory map - memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); - } + bytesPerBurst = Configuration::getInstance() + .adjustNumBytesAfterECC(bytesPerBurst); tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); - if (powerAnalysis) - { - sc_time clk = Configuration::getInstance().memSpec->clk; + // Parameters for DRAMPower + sc_time clk = Configuration::getInstance().memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = - Configuration::getInstance().memSpec->BurstLength; - memArchSpec.dataRate = Configuration::getInstance().memSpec->DataRate; - memArchSpec.nbrOfRows = - Configuration::getInstance().memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = - Configuration::getInstance().memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = - Configuration::getInstance().memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = - Configuration::getInstance().memSpec->NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = - Configuration::getInstance().memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec->vDD2 == 0 - ? false : true); - memArchSpec.dll = Configuration::getInstance().memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = + Configuration::getInstance().memSpec->BurstLength; + memArchSpec.dataRate = Configuration::getInstance().memSpec->DataRate; + memArchSpec.nbrOfRows = + Configuration::getInstance().memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = + Configuration::getInstance().memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = + Configuration::getInstance().memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = + Configuration::getInstance().memSpec->NumberOfRanks; + memArchSpec.width = Configuration::getInstance().memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = + Configuration::getInstance().memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec->vDD2 == 0 + ? false : true); + memArchSpec.dll = Configuration::getInstance().memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = Configuration::getInstance().memSpec->tAL / clk; - memTimingSpec.CCD = Configuration::getInstance().memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = Configuration::getInstance().memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = Configuration::getInstance().memSpec->tCCD_S / clk; - memTimingSpec.CKE = Configuration::getInstance().memSpec->tCKE / clk; - memTimingSpec.CKESR = Configuration::getInstance().memSpec->tCKESR / clk; - memTimingSpec.clkMhz = Configuration::getInstance().memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec->clkMHz; - memTimingSpec.DQSCK = Configuration::getInstance().memSpec->tDQSCK / clk; - memTimingSpec.FAW = Configuration::getInstance().memSpec->tNAW / clk; - memTimingSpec.RAS = Configuration::getInstance().memSpec->tRAS / clk; - memTimingSpec.RC = Configuration::getInstance().memSpec->tRC / clk; - memTimingSpec.RCD = Configuration::getInstance().memSpec->tRCD / clk; - memTimingSpec.REFI = Configuration::getInstance().memSpec->tREFI / clk; - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC / clk; - memTimingSpec.RL = Configuration::getInstance().memSpec->tRL / clk; - memTimingSpec.RP = Configuration::getInstance().memSpec->tRP / clk; - memTimingSpec.RRD = Configuration::getInstance().memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = Configuration::getInstance().memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = Configuration::getInstance().memSpec->tRRD_S / clk; - memTimingSpec.RTP = Configuration::getInstance().memSpec->tRTP / clk; - memTimingSpec.TAW = Configuration::getInstance().memSpec->tNAW / clk; - memTimingSpec.WL = Configuration::getInstance().memSpec->tWL / clk; - memTimingSpec.WR = Configuration::getInstance().memSpec->tWR / clk; - memTimingSpec.WTR = Configuration::getInstance().memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = Configuration::getInstance().memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = Configuration::getInstance().memSpec->tWTR_S / clk; - memTimingSpec.XP = Configuration::getInstance().memSpec->tXP / clk; - memTimingSpec.XPDLL = Configuration::getInstance().memSpec->tXPDLL / clk; - memTimingSpec.XS = Configuration::getInstance().memSpec->tXSR / clk; - memTimingSpec.XSDLL = Configuration::getInstance().memSpec->tXSRDLL / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = Configuration::getInstance().memSpec->tAL / clk; + memTimingSpec.CCD = Configuration::getInstance().memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = Configuration::getInstance().memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = Configuration::getInstance().memSpec->tCCD_S / clk; + memTimingSpec.CKE = Configuration::getInstance().memSpec->tCKE / clk; + memTimingSpec.CKESR = Configuration::getInstance().memSpec->tCKESR / clk; + memTimingSpec.clkMhz = Configuration::getInstance().memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec->clkMHz; + memTimingSpec.DQSCK = Configuration::getInstance().memSpec->tDQSCK / clk; + memTimingSpec.FAW = Configuration::getInstance().memSpec->tNAW / clk; + memTimingSpec.RAS = Configuration::getInstance().memSpec->tRAS / clk; + memTimingSpec.RC = Configuration::getInstance().memSpec->tRC / clk; + memTimingSpec.RCD = Configuration::getInstance().memSpec->tRCD / clk; + memTimingSpec.REFI = Configuration::getInstance().memSpec->tREFI / clk; + auto m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC / clk; + memTimingSpec.RL = Configuration::getInstance().memSpec->tRL / clk; + memTimingSpec.RP = Configuration::getInstance().memSpec->tRP / clk; + memTimingSpec.RRD = Configuration::getInstance().memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = Configuration::getInstance().memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = Configuration::getInstance().memSpec->tRRD_S / clk; + memTimingSpec.RTP = Configuration::getInstance().memSpec->tRTP / clk; + memTimingSpec.TAW = Configuration::getInstance().memSpec->tNAW / clk; + memTimingSpec.WL = Configuration::getInstance().memSpec->tWL / clk; + memTimingSpec.WR = Configuration::getInstance().memSpec->tWR / clk; + memTimingSpec.WTR = Configuration::getInstance().memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = Configuration::getInstance().memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = Configuration::getInstance().memSpec->tWTR_S / clk; + memTimingSpec.XP = Configuration::getInstance().memSpec->tXP / clk; + memTimingSpec.XPDLL = Configuration::getInstance().memSpec->tXPDLL / clk; + memTimingSpec.XS = Configuration::getInstance().memSpec->tXSR / clk; + memTimingSpec.XSDLL = Configuration::getInstance().memSpec->tXSRDLL / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = Configuration::getInstance().memSpec->iDD0; - memPowerSpec.idd02 = Configuration::getInstance().memSpec->iDD02; - memPowerSpec.idd2p0 = Configuration::getInstance().memSpec->iDD2P0; - memPowerSpec.idd2p02 = Configuration::getInstance().memSpec->iDD2P02; - memPowerSpec.idd2p1 = Configuration::getInstance().memSpec->iDD2P1; - memPowerSpec.idd2p12 = Configuration::getInstance().memSpec->iDD2P12; - memPowerSpec.idd2n = Configuration::getInstance().memSpec->iDD2N; - memPowerSpec.idd2n2 = Configuration::getInstance().memSpec->iDD2N2; - memPowerSpec.idd3p0 = Configuration::getInstance().memSpec->iDD3P0; - memPowerSpec.idd3p02 = Configuration::getInstance().memSpec->iDD3P02; - memPowerSpec.idd3p1 = Configuration::getInstance().memSpec->iDD3P1; - memPowerSpec.idd3p12 = Configuration::getInstance().memSpec->iDD3P12; - memPowerSpec.idd3n = Configuration::getInstance().memSpec->iDD3N; - memPowerSpec.idd3n2 = Configuration::getInstance().memSpec->iDD3N2; - memPowerSpec.idd4r = Configuration::getInstance().memSpec->iDD4R; - memPowerSpec.idd4r2 = Configuration::getInstance().memSpec->iDD4R2; - memPowerSpec.idd4w = Configuration::getInstance().memSpec->iDD4W; - memPowerSpec.idd4w2 = Configuration::getInstance().memSpec->iDD4W2; - memPowerSpec.idd5 = Configuration::getInstance().memSpec->iDD5; - memPowerSpec.idd52 = Configuration::getInstance().memSpec->iDD52; - memPowerSpec.idd6 = Configuration::getInstance().memSpec->iDD6; - memPowerSpec.idd62 = Configuration::getInstance().memSpec->iDD62; - memPowerSpec.vdd = Configuration::getInstance().memSpec->vDD; - memPowerSpec.vdd2 = Configuration::getInstance().memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = Configuration::getInstance().memSpec->iDD0; + memPowerSpec.idd02 = Configuration::getInstance().memSpec->iDD02; + memPowerSpec.idd2p0 = Configuration::getInstance().memSpec->iDD2P0; + memPowerSpec.idd2p02 = Configuration::getInstance().memSpec->iDD2P02; + memPowerSpec.idd2p1 = Configuration::getInstance().memSpec->iDD2P1; + memPowerSpec.idd2p12 = Configuration::getInstance().memSpec->iDD2P12; + memPowerSpec.idd2n = Configuration::getInstance().memSpec->iDD2N; + memPowerSpec.idd2n2 = Configuration::getInstance().memSpec->iDD2N2; + memPowerSpec.idd3p0 = Configuration::getInstance().memSpec->iDD3P0; + memPowerSpec.idd3p02 = Configuration::getInstance().memSpec->iDD3P02; + memPowerSpec.idd3p1 = Configuration::getInstance().memSpec->iDD3P1; + memPowerSpec.idd3p12 = Configuration::getInstance().memSpec->iDD3P12; + memPowerSpec.idd3n = Configuration::getInstance().memSpec->iDD3N; + memPowerSpec.idd3n2 = Configuration::getInstance().memSpec->iDD3N2; + memPowerSpec.idd4r = Configuration::getInstance().memSpec->iDD4R; + memPowerSpec.idd4r2 = Configuration::getInstance().memSpec->iDD4R2; + memPowerSpec.idd4w = Configuration::getInstance().memSpec->iDD4W; + memPowerSpec.idd4w2 = Configuration::getInstance().memSpec->iDD4W2; + memPowerSpec.idd5 = Configuration::getInstance().memSpec->iDD5; + memPowerSpec.idd52 = Configuration::getInstance().memSpec->iDD52; + memPowerSpec.idd6 = Configuration::getInstance().memSpec->iDD6; + memPowerSpec.idd62 = Configuration::getInstance().memSpec->iDD62; + memPowerSpec.vdd = Configuration::getInstance().memSpec->vDD; + memPowerSpec.vdd2 = Configuration::getInstance().memSpec->vDD2; - MemorySpecification memSpec; - memSpec.id = Configuration::getInstance().memSpec->MemoryId; - memSpec.memoryType = Configuration::getInstance().memSpec->MemoryType; - memSpec.memTimingSpec = memTimingSpec; - memSpec.memPowerSpec = memPowerSpec; - memSpec.memArchSpec = memArchSpec; + MemorySpecification memSpec; + memSpec.id = Configuration::getInstance().memSpec->MemoryId; + memSpec.memoryType = Configuration::getInstance().memSpec->MemoryType; + memSpec.memTimingSpec = memTimingSpec; + memSpec.memPowerSpec = memPowerSpec; + memSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(memSpec, 0); - } - - // For each bank in a channel a error Model is created: - if (StoreMode == StorageMode::ErrorModel) - { - for (unsigned i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; - i++) - { - errorModel *em; - std::string errorModelStr = "errorModel_bank" + std::to_string(i); - if (powerAnalysis) - em = new errorModel(errorModelStr.c_str(), DRAMPower); - else - em = new errorModel(errorModelStr.c_str()); - ememory.push_back(em); - } - } + DRAMPower = new libDRAMPower(memSpec, 0); } Dram::~Dram() { - if (powerAnalysis) - { - if (!Configuration::getInstance().DatabaseRecording) - DRAMPower->calcEnergy(); + if (!Configuration::getInstance().DatabaseRecording) + DRAMPower->calcEnergy(); - // Print the final total energy and the average power for - // the simulation: - cout << name() << string(" Total Energy: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" pJ") - << endl; + // Print the final total energy and the average power for + // the simulation: + cout << name() << string(" Total Energy: ") + << fixed << std::setprecision( 2 ) + << DRAMPower->getEnergy().total_energy + * Configuration::getInstance().NumberOfDevicesOnDIMM + << string(" pJ") + << endl; - cout << name() << string(" Average Power: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getPower().average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" mW") << endl; - } - - // Clean up: - for (auto e : ememory) - delete e; + cout << name() << string(" Average Power: ") + << fixed << std::setprecision( 2 ) + << DRAMPower->getPower().average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM + << string(" mW") << endl; if (Configuration::getInstance().UseMalloc) free(memory); @@ -247,232 +206,154 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: - unsigned long long cycle = 0; - if (powerAnalysis) - { - cycle = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); - } + unsigned long long cycle = sc_time_stamp().value() / + Configuration::getInstance().memSpec->clk.value(); if (phase == BEGIN_PREB) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - + DRAMPower->doCommand(MemCommand::PREB, bank, cycle); sendToController(payload, END_PREB, delay + getExecutionTime(Command::PreB, payload)); } else if (phase == BEGIN_PRE) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - + DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - + DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACTB) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - + DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); sendToController(payload, END_ACTB, delay + getExecutionTime(Command::ActB, payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->activate(row); } else if (phase == BEGIN_ACT) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - + DRAMPower->doCommand(MemCommand::ACT, bank, cycle); sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->activate(row); } else if (phase == BEGIN_WR) { -#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5) - assert(payload.get_data_length() == bytesPerBurst); -#endif - - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::WR, bank, cycle); - + DRAMPower->doCommand(MemCommand::WR, bank, cycle); // save data: - if (StoreMode == StorageMode::NoStorage) // Don't store data - {} - else if (StoreMode == StorageMode::Store) // Use Storage + if (StoreMode == StorageMode::Store) // Use Storage { unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - else // if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model - { - ememory[bank]->store(payload); - } sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); } else if (phase == BEGIN_RD) { -#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5) - assert(payload.get_data_length() == bytesPerBurst); -#endif - - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::RD, bank, cycle); - + DRAMPower->doCommand(MemCommand::RD, bank, cycle); // load data: if (StoreMode == StorageMode::Store) // use StorageMode { unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel - { - ememory[bank]->load(payload); - } sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); } else if (phase == BEGIN_WRA) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); - + DRAMPower->doCommand(MemCommand::WRA, bank, cycle); // save data: - if (StoreMode == StorageMode::NoStorage) // Don't store data - {} - else if (StoreMode == StorageMode::Store) // Use Storage + if (StoreMode == StorageMode::Store) // Use Storage { unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - else // if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model - { - ememory[bank]->store(payload); - } sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); - + DRAMPower->doCommand(MemCommand::RDA, bank, cycle); // Load data: if (StoreMode == StorageMode::Store) // use StorageMode { unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel - { - ememory[bank]->load(payload); - } sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_REFA) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - + DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->refresh(row); } else if (phase == BEGIN_REFB) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::REFB, bank, cycle); - + DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); } else if (phase == END_PDNA) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } else if (phase == BEGIN_PDNAB) { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); } else if (phase == END_PDNAB) { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); } else if (phase == BEGIN_PDNP) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); } else if (phase == END_PDNP) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } else if (phase == BEGIN_PDNPB) { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); } else if (phase == END_PDNPB) { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); } else if (phase == BEGIN_SREF) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + DRAMPower->doCommand(MemCommand::SREN, bank, cycle); } else if (phase == END_SREF) { - if (powerAnalysis) - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } else if (phase == BEGIN_SREFB) { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); } else if (phase == END_SREFB) { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); } else { - if (powerAnalysis) - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); + SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); } - return tlm::TLM_ACCEPTED; + return TLM_ACCEPTED; } unsigned int Dram::transport_dbg(tlm_generic_payload &trans) diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 2f4c15c2..372df02c 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -45,7 +45,7 @@ #include #include "../controller/Controller.h" #include "../controller/core/configuration/Configuration.h" -#include "../error/errormodel.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; using namespace tlm; @@ -59,14 +59,11 @@ private: // Power Model related bool powerAnalysis = Configuration::getInstance().PowerAnalysis; - // Error Model related: - StorageMode StoreMode = Configuration::getInstance().StoreMode; - std::vector ememory; - +protected: // Data Storage: + StorageMode StoreMode = Configuration::getInstance().StoreMode; unsigned char *memory; -protected: libDRAMPower *DRAMPower; virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, @@ -85,7 +82,7 @@ public: Dram(sc_module_name); SC_HAS_PROCESS(Dram); - ~Dram(); + virtual ~Dram(); }; #endif // DRAM_H diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 91ba5736..ebe78c90 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -34,11 +34,12 @@ */ #include "DramDDR3.h" + #include "Dram.h" +#include "../controller/core/configuration/Configuration.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { - + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramDDR3", "Error Model for DDR3 not supported"); } - -//DramDDR3::~DramDDR3() {} diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index 0bf0a8a9..0886d25a 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -45,8 +45,6 @@ class DramDDR3 : public Dram public: DramDDR3(sc_module_name); SC_HAS_PROCESS(DramDDR3); - - //~DramDDR3(); }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index b10cd313..8feeb259 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -34,11 +34,12 @@ */ #include "DramDDR4.h" + #include "Dram.h" +#include "../controller/core/configuration/Configuration.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { - + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramDDR4", "Error Model for DDR4 not supported"); } - -//DramDDR4::~DramDDR4() {} diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index 64bae19d..5cf92424 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -40,15 +40,11 @@ #include #include -using namespace tlm; - class DramDDR4 : public Dram { public: DramDDR4(sc_module_name); SC_HAS_PROCESS(DramDDR4); - - //~DramDDR4(); }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 56a3196a..cc24e5a2 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -39,6 +39,7 @@ #include "../common/TlmRecorder.h" #include "DramDDR3.h" #include "DramDDR4.h" +#include "DramWideIO.h" #include "../common/utils.h" using namespace tlm; @@ -138,4 +139,5 @@ void DramRecordable::recordPower() template class DramRecordable; template class DramRecordable; +template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index 2e4231ff..59d6873a 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -52,7 +52,7 @@ public: DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder); SC_HAS_PROCESS(DramRecordable); - ~DramRecordable(); + virtual ~DramRecordable(); protected: virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp new file mode 100644 index 00000000..038d0671 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramWideIO.h" + +#include +#include +#include "Dram.h" + +using namespace tlm; + +DramWideIO::DramWideIO(sc_module_name name) : Dram(name) +{ + // For each bank in a channel a error Model is created: + if (StoreMode == StorageMode::ErrorModel) + { + if (Configuration::getInstance().UseMalloc) + free(memory); + + for (unsigned i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; + i++) + { + errorModel *em; + std::string errorModelStr = "errorModel_bank" + std::to_string(i); + em = new errorModel(errorModelStr.c_str(), DRAMPower); + ememory.push_back(em); + } + } +} + +DramWideIO::~DramWideIO() +{ + // Clean up: + for (auto e : ememory) + delete e; +} + +tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay) +{ + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + + // This is only needed for power simulation: + unsigned long long cycle = sc_time_stamp().value() / + Configuration::getInstance().memSpec->clk.value(); + + if (phase == BEGIN_PREB) + { + DRAMPower->doCommand(MemCommand::PREB, bank, cycle); + sendToController(payload, END_PREB, delay + getExecutionTime(Command::PreB, + payload)); + } + else if (phase == BEGIN_PRE) + { + DRAMPower->doCommand(MemCommand::PRE, bank, cycle); + sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, + payload)); + } + else if (phase == BEGIN_PRE_ALL) + { + DRAMPower->doCommand(MemCommand::PREA, bank, cycle); + sendToController(payload, END_PRE_ALL, + delay + getExecutionTime(Command::PrechargeAll, payload)); + } + else if (phase == BEGIN_ACTB) + { + DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); + sendToController(payload, END_ACTB, delay + getExecutionTime(Command::ActB, + payload)); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + if (StoreMode == StorageMode::ErrorModel) + ememory[bank]->activate(row); + } + else if (phase == BEGIN_ACT) + { + DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, + payload)); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + + if (StoreMode == StorageMode::ErrorModel) + ememory[bank]->activate(row); + } + else if (phase == BEGIN_WR) + { + DRAMPower->doCommand(MemCommand::WR, bank, cycle); + // save data: + if (StoreMode == StorageMode::Store) // Use Storage + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); + } + else if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model + { + ememory[bank]->store(payload); + } + sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, + payload)); + } + else if (phase == BEGIN_RD) + { + DRAMPower->doCommand(MemCommand::RD, bank, cycle); + // load data: + if (StoreMode == StorageMode::Store) // use StorageMode + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); + } + else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel + { + ememory[bank]->load(payload); + } + sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, + payload)); + } + else if (phase == BEGIN_WRA) + { + DRAMPower->doCommand(MemCommand::WRA, bank, cycle); + // save data: + if (StoreMode == StorageMode::Store) // Use Storage + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); + } + else if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model + { + ememory[bank]->store(payload); + } + sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, + payload)); + } + else if (phase == BEGIN_RDA) + { + DRAMPower->doCommand(MemCommand::RDA, bank, cycle); + // Load data: + if (StoreMode == StorageMode::Store) // use StorageMode + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); + } + else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel + { + ememory[bank]->load(payload); + } + sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, + payload)); + } + else if (phase == BEGIN_REFA) + { + DRAMPower->doCommand(MemCommand::REF, bank, cycle); + sendToController(payload, END_REFA, + delay + getExecutionTime(Command::AutoRefresh, payload)); + unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + + if (StoreMode == StorageMode::ErrorModel) + ememory[bank]->refresh(row); + } + else if (phase == BEGIN_REFB) + { + DRAMPower->doCommand(MemCommand::REFB, bank, cycle); + sendToController(payload, END_REFB, + delay + getExecutionTime(Command::AutoRefresh, payload)); + } + // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length + else if (phase == BEGIN_PDNA) + { + DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + } + else if (phase == END_PDNA) + { + DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + } + else if (phase == BEGIN_PDNAB) + { + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == END_PDNAB) + { + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == BEGIN_PDNP) + { + DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + } + else if (phase == END_PDNP) + { + DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + } + else if (phase == BEGIN_PDNPB) + { + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == END_PDNPB) + { + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == BEGIN_SREF) + { + DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + } + else if (phase == END_SREF) + { + DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + } + else if (phase == BEGIN_SREFB) + { + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else if (phase == END_SREFB) + { + SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); + } + else + { + SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); + } + + return TLM_ACCEPTED; +} diff --git a/DRAMSys/library/src/simulation/DramWideIO.h b/DRAMSys/library/src/simulation/DramWideIO.h new file mode 100644 index 00000000..56e0b39a --- /dev/null +++ b/DRAMSys/library/src/simulation/DramWideIO.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMWIDEIO_H +#define DRAMWIDEIO_H + +#include +#include +#include "Dram.h" +#include "../error/errormodel.h" + +using namespace tlm; + +class DramWideIO : public Dram +{ +public: + DramWideIO(sc_module_name); + SC_HAS_PROCESS(DramWideIO); + + virtual ~DramWideIO(); + +protected: + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay); + +private: + std::vector ememory; +}; + +#endif // DRAMWIDEIO_H From d07a775697feefe5cb2c958a06803e0bd0cdead3 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 24 Jun 2019 13:59:57 +0200 Subject: [PATCH 30/30] Annotations for different MemSpecs. --- .../configuration/ConfigurationLoader.cpp | 134 +++++++++--------- DRAMSys/library/src/simulation/Dram.cpp | 1 - DRAMSys/library/src/simulation/DramWideIO.cpp | 2 + 3 files changed, 69 insertions(+), 68 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index def1d129..a4d3f94f 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -177,17 +177,17 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = 1; + config.memSpec->NumberOfBankGroups = 1; config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 4; + config.memSpec->nActivate = 4; config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = true; - config.memSpec->termination = true; + config.memSpec->DLL = true; + config.memSpec->termination = true; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); @@ -198,29 +198,29 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec->refreshTimings.clear(); + config.memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, config.memSpec->tREFI); @@ -229,7 +229,7 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) // Currents and Volatages: TODO Check if this is correct. XMLElement *powers = memspec->FirstChildElement("mempowerspec"); config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec->iDD02 = 0; + config.memSpec->iDD02 = 0; config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); @@ -240,9 +240,9 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec->iDD62 = 0; + config.memSpec->iDD62 = 0; config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec->vDD2 = 0; + config.memSpec->vDD2 = 0; } void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) @@ -255,14 +255,14 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) "nbrOfBankGroups"); config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 4; + config.memSpec->nActivate = 4; config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = true; - config.memSpec->termination = true; + config.memSpec->DLL = true; + config.memSpec->termination = true; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); @@ -278,7 +278,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); @@ -288,8 +288,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); config.memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); @@ -324,60 +324,60 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } -// TODO: fix this for LPDDR4 +// TODO: change timings for LPDDR4 void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec) { //MemArchitecture: XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = 1; + config.memSpec->NumberOfBankGroups = 1; config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 4; + config.memSpec->nActivate = 4; config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = false; // TODO: Correct? - config.memSpec->termination = true; // TODO: Correct? + config.memSpec->DLL = false; // TODO: Correct? + config.memSpec->termination = true; // TODO: Correct? //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); sc_time clk = config.memSpec->clk; - config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); + config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); config.memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS"); config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); - // TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); - // TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); + config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); + // TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); + config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); + // TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec->refreshTimings.clear(); + config.memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, config.memSpec->tREFI); @@ -387,11 +387,11 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec) XMLElement *powers = memspec->FirstChildElement("mempowerspec"); config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); - config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); + config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); + config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); - config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); + config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); + config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); @@ -408,17 +408,17 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = 1; - config.memSpec->NumberOfRanks = 1; + config.memSpec->NumberOfBankGroups = 1; + config.memSpec->NumberOfRanks = 1; config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 2; + config.memSpec->nActivate = 2; config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = false; - config.memSpec->termination = false; + config.memSpec->DLL = false; + config.memSpec->termination = false; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); @@ -428,29 +428,29 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tRRD_L = config.memSpec->tRRD_S; - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tCCD_L = config.memSpec->tCCD_S; + config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec->tRRD_L = config.memSpec->tRRD_S; + config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec->tCCD_L = config.memSpec->tCCD_S; config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); + config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tWTR_L = config.memSpec->tWTR_S; + config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec->tWTR_L = config.memSpec->tWTR_S; config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXPDLL = config.memSpec->tXP; - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = config.memSpec->tXSR; - config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + config.memSpec->tXPDLL = config.memSpec->tXP; + config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec->tXSRDLL = config.memSpec->tXSR; + config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec->refreshTimings.clear(); + config.memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, config.memSpec->tREFI); diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index af3a1594..cc391efc 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -56,7 +56,6 @@ #include "../common/protocol.h" #include "../common/utils.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../error/errormodel.h" using namespace std; using namespace tlm; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 038d0671..3f69ca7a 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -38,6 +38,8 @@ #include #include #include "Dram.h" +#include "../controller/core/configuration/Configuration.h" +#include "../error/errormodel.h" using namespace tlm;