diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml
index 8cf18562..3ce68d4f 100644
--- a/dram/resources/simulations/sim-batch.xml
+++ b/dram/resources/simulations/sim-batch.xml
@@ -3,21 +3,21 @@
                   <Debug value="1" />
         </simconfig>
         <memspecs>
-                <memspec src="/home/jonny/newconfigs/mems.xml"></memspec>
+                <memspec src="/home/schlemmi/newconfigs/mems.xml"></memspec>
         </memspecs>
         <addressmappings>
-                <addressmapping src="/home/jonny/newconfigs/amc.xml"></addressmapping>
+                <addressmapping src="/home/schlemmi/newconfigs/amc.xml"></addressmapping>
         </addressmappings>
         <memconfigs>
-           <memconfig src="/home/jonny/newconfigs/memc.xml">
+           <memconfig src="/home/schlemmi/newconfigs/memc.xml">
            </memconfig>
         </memconfigs>
 
         <tracesetups>
 
-<tracesetup id="voco">
+<tracesetup id="medium">
      <!--<device clkMhz="200">test.stl</device>-->
-     <device clkMhz="200">eiersalat.stl</device>
+     <device clkMhz="200">medium.stl</device>
 </tracesetup>
 
   </tracesetups>
diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h
index 88be6298..a3d35335 100644
--- a/dram/src/controller/Controller.h
+++ b/dram/src/controller/Controller.h
@@ -77,7 +77,10 @@ private:
     void payloadEntersSystem(tlm_generic_payload& payload);
     void payloadLeavesSystem(tlm_generic_payload& payload);
     unsigned int getTotalNumberOfPayloadsInSystem();
-    void scheduleNextPayload();
+    void scheduleNextFromScheduler();
+    //FIFO HACK
+    void scheduleDirectly(gp* payload);
+
 
     // --- FRONTEND ------
     tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay);
@@ -99,6 +102,7 @@ private:
     ControllerCore* controllerCore;
     Scheduler* scheduler;
     std::map<Bank, int> numberOfPayloadsInSystem;
+    std::vector<gp* > refreshCollisionRequets;
     tlm::tlm_generic_payload* backpressure = NULL;
 
     tlm_utils::peq_with_cb_and_phase<Controller> frontendPEQ;
@@ -283,7 +287,7 @@ void Controller<BUSWIDTH>::controllerCorePEQCallback(tlm_generic_payload &payloa
         sendToDram(payload, phase, SC_ZERO_TIME);
 
         if (phase == BEGIN_RD || phase == BEGIN_WR)
-            scheduleNextPayload();
+            scheduleNextFromScheduler();
         else if (phase == BEGIN_REFB)
             printDebugMessage("Entering REFB on bank " + to_string(bank.ID()));
         else if (phase == BEGIN_REFA)
@@ -337,11 +341,19 @@ void Controller<BUSWIDTH>::frontendPEQCallback(tlm_generic_payload &payload, con
         }
         payload.set_response_status(tlm::TLM_OK_RESPONSE);
         sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
-        //FIFOOOOOOOOOOO
-        //scheduler->schedule(&payload);
-        controllerCore->scheduleRequest(payload);
-        scheduleNextPayload();
-    }
+
+        //FIFO HACK
+        if(Configuration::getInstance().Scheduler == "FIFO")
+        {
+            scheduleDirectly(&payload);
+        }
+        //Original
+        else
+        {
+            scheduler->schedule(&payload);
+            scheduleNextFromScheduler();
+        }
+     }
     else if (phase == END_RESP)
     {
         if (backpressure != NULL)
@@ -349,8 +361,15 @@ void Controller<BUSWIDTH>::frontendPEQCallback(tlm_generic_payload &payload, con
             printDebugMessage("##Backpressure released");
             backpressure->set_response_status(tlm::TLM_OK_RESPONSE);
             sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME);
-            scheduler->schedule(backpressure);
-            scheduleNextPayload();
+            if(Configuration::getInstance().Scheduler == "FIFO")
+            {
+                scheduleDirectly(backpressure);
+            }
+            else
+            {
+                scheduler->schedule(backpressure);
+                scheduleNextFromScheduler();
+            }
             backpressure = NULL;
         }
 
@@ -395,8 +414,19 @@ unsigned int Controller<BUSWIDTH>::getTotalNumberOfPayloadsInSystem()
     return sum;
 }
 
+
+//FIFO HACK!
 template<unsigned int BUSWIDTH>
-void Controller<BUSWIDTH>::scheduleNextPayload()
+void Controller<BUSWIDTH>::scheduleDirectly(gp* payload)
+{
+    if(!controllerCore->scheduleRequest(*payload))
+    {
+        refreshCollisionRequets.push_back(payload);
+    }
+}
+
+template<unsigned int BUSWIDTH>
+void Controller<BUSWIDTH>::scheduleNextFromScheduler()
 {
     if(scheduler->hasPayloads())
     {
@@ -438,7 +468,7 @@ void Controller<BUSWIDTH>::dramPEQCallback(tlm_generic_payload &payload, const t
 
     if (phase == BEGIN_RD || phase == BEGIN_WR)
     {
-        scheduleNextPayload();
+        scheduleNextFromScheduler();
         sendToDram(payload, phase, SC_ZERO_TIME);
     }
     else if (phase == END_RD || phase == END_WR)
@@ -448,14 +478,28 @@ void Controller<BUSWIDTH>::dramPEQCallback(tlm_generic_payload &payload, const t
     else if (phase == END_RDA || phase == END_WRA)
     {
         sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
-        scheduleNextPayload();
+        scheduleNextFromScheduler();
     }
-    else if (phase == END_REFA || phase == END_REFB)//TODO send all to sleep for REFA cause we only send for bank 0 now???
+    else if (phase == END_REFA || phase == END_REFB)
     {
         printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID()));
+
         if(numberOfPayloadsInSystem[bank] == 0)
             controllerCore->powerDownManager->sleep(bank,sc_time_stamp());
-        scheduleNextPayload();
+        //FIFO HACK
+        if(Configuration::getInstance().Scheduler == "FIFO")
+        {
+            std::vector<gp*> collidedReq = this->refreshCollisionRequets;
+            refreshCollisionRequets.clear();
+            for(gp* payload : collidedReq)
+            {
+                scheduleDirectly(payload);
+            }
+        }
+        else
+        {
+            scheduleNextFromScheduler();
+        }
     }
     else if (containsPhase(phase, { END_PRE, END_PRE_ALL, END_ACT }))
     {