From 6c590a298f67beda7e912624ceb6d87d3bb43605 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 30 Mar 2020 15:34:28 +0200 Subject: [PATCH] Renaming and minor changes in the memspec. --- DRAMSys/library/src/common/TlmRecorder.cpp | 34 ++--- .../library/src/common/XmlAddressDecoder.cpp | 6 +- DRAMSys/library/src/common/dramExtensions.cpp | 2 +- .../src/configuration/Configuration.cpp | 16 +- .../src/configuration/ConfigurationLoader.cpp | 140 +++++++++--------- .../src/configuration/memspec/MemSpec.cpp | 12 +- .../src/configuration/memspec/MemSpec.h | 28 ++-- .../src/configuration/memspec/MemSpecDDR3.cpp | 12 +- .../src/configuration/memspec/MemSpecDDR4.cpp | 2 - .../src/configuration/memspec/MemSpecHBM2.cpp | 2 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 22 +-- .../library/src/controller/BankMachine.cpp | 4 +- DRAMSys/library/src/controller/Controller.cpp | 48 +++--- DRAMSys/library/src/controller/ControllerIF.h | 6 +- .../src/controller/checker/CheckerDDR3.cpp | 8 +- .../src/controller/checker/CheckerDDR4.cpp | 10 +- .../src/controller/checker/CheckerGDDR5.cpp | 14 +- .../src/controller/checker/CheckerGDDR5X.cpp | 14 +- .../src/controller/checker/CheckerGDDR6.cpp | 12 +- .../src/controller/checker/CheckerHBM2.cpp | 16 +- .../src/controller/checker/CheckerLPDDR4.cpp | 8 +- .../src/controller/checker/CheckerWideIO.cpp | 8 +- .../src/controller/checker/CheckerWideIO2.cpp | 6 +- .../refresh/RefreshManagerBankwise.cpp | 10 +- .../controller/scheduler/SchedulerFifo.cpp | 2 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 2 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 2 +- DRAMSys/library/src/error/errormodel.cpp | 8 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/StlPlayer.h | 2 +- .../library/src/simulation/TraceGenerator.h | 2 +- .../src/simulation/TracePlayerListener.h | 2 +- DRAMSys/library/src/simulation/TraceSetup.cpp | 10 +- DRAMSys/library/src/simulation/TraceSetup.h | 8 +- .../library/src/simulation/dram/DramDDR3.cpp | 18 +-- .../library/src/simulation/dram/DramDDR4.cpp | 18 +-- .../src/simulation/dram/DramRecordable.cpp | 6 +- .../src/simulation/dram/DramWideIO.cpp | 28 ++-- DRAMSys/simulator/main.cpp | 2 +- 39 files changed, 275 insertions(+), 277 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 8fe6b343..829836b9 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -325,9 +325,9 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 2, simulationTimeCoveredByRecording.value()); sqlite3_bind_int(insertGeneralInfoStatement, 3, - Configuration::getInstance().memSpec->NumberOfRanks); + Configuration::getInstance().memSpec->numberOfRanks); sqlite3_bind_int(insertGeneralInfoStatement, 4, - Configuration::getInstance().memSpec->NumberOfBanks); + Configuration::getInstance().memSpec->numberOfBanks); sqlite3_bind_int(insertGeneralInfoStatement, 5, Configuration::getInstance().memSpec->clk.value()); sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL); @@ -361,21 +361,21 @@ void TlmRecorder::insertCommandLengths() { MemSpec *memSpec = Configuration::getInstance().memSpec; - sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLength[Command::ACT]); - sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLength[Command::PRE]); - sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLength[Command::PREA]); - sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLength[Command::RD]); - sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLength[Command::RDA]); - sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLength[Command::WR]); - sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLength[Command::WRA]); - sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLength[Command::REFA]); - sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLength[Command::REFB]); - sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLength[Command::PDEA]); - sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLength[Command::PDXA]); - sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLength[Command::PDEP]); - sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLength[Command::PDXP]); - sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLength[Command::SREFEN]); - sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLength[Command::SREFEX]); + sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLengthInCycles[Command::ACT]); + sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLengthInCycles[Command::PRE]); + sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLengthInCycles[Command::PREA]); + sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLengthInCycles[Command::RD]); + sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLengthInCycles[Command::RDA]); + sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLengthInCycles[Command::WR]); + sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLengthInCycles[Command::WRA]); + sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLengthInCycles[Command::REFA]); + sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLengthInCycles[Command::REFB]); + sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLengthInCycles[Command::PDEA]); + sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLengthInCycles[Command::PDXA]); + sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLengthInCycles[Command::PDEP]); + sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLengthInCycles[Command::PDXP]); + sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLengthInCycles[Command::SREFEN]); + sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLengthInCycles[Command::SREFEX]); executeSqlStatement(insertCommandLengthsStatement); } diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index d6e321d5..71a54039 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -124,9 +124,9 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (config.numberOfMemChannels != amount.channel || memSpec->NumberOfRanks != amount.rank - || memSpec->NumberOfBankGroups != amount.bankgroup || memSpec->NumberOfBanks != amount.bank - || memSpec->NumberOfRows != amount.row || memSpec->NumberOfColumns != amount.column + if (config.numberOfMemChannels != amount.channel || memSpec->numberOfRanks != amount.rank + || memSpec->numberOfBankGroups != amount.bankgroup || memSpec->numberOfBanks != amount.bank + || memSpec->numberOfRows != amount.row || memSpec->numberOfColumns != amount.column || config.numberOfDevicesOnDIMM * memSpec->bitWidth != amount.bytes * 8) SC_REPORT_FATAL("XmlAddressDecoder", "Memspec and addressmapping do not match"); } diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index d49666bf..2eedddd4 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -332,7 +332,7 @@ bool operator !=(const Row &lhs, const Row &rhs) const Row Row::operator ++() { - id = (id + 1) % Configuration::getInstance().memSpec->NumberOfRows; + id = (id + 1) % Configuration::getInstance().memSpec->numberOfRows; return *this; } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index d9d2a711..67955ff0 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -191,12 +191,12 @@ void Configuration::setPathToResources(std::string path) std::uint64_t Configuration::getSimMemSizeInBytes() { // 1. Get number of banks, rows, columns and data width in bits for one die (or chip) - std::string type = memSpec->MemoryType; - std::uint64_t ranks = memSpec->NumberOfRanks; - std::uint64_t bankgroups = memSpec->NumberOfBankGroups; - std::uint64_t banks = memSpec->NumberOfBanks; - std::uint64_t rows = memSpec->NumberOfRows; - std::uint64_t columns = memSpec->NumberOfColumns; + std::string type = memSpec->memoryType; + std::uint64_t ranks = memSpec->numberOfRanks; + std::uint64_t bankgroups = memSpec->numberOfBankGroups; + std::uint64_t banks = memSpec->numberOfBanks; + std::uint64_t rows = memSpec->numberOfRows; + std::uint64_t columns = memSpec->numberOfColumns; std::uint64_t bitWidth = memSpec->bitWidth; // 2. Calculate size of one DRAM chip in bits std::uint64_t chipBitSize = banks * rows * columns * bitWidth; @@ -239,7 +239,7 @@ unsigned int Configuration::getDataBusWidth() unsigned int Configuration::getBytesPerBurst() { // First multiply to get the number of bits in a burst, then divide by 8 to get the value in bytes. The order is important. Think on a single x4 device. - unsigned int bytesPerBurst = (memSpec->BurstLength * getDataBusWidth()) / 8; + unsigned int bytesPerBurst = (memSpec->burstLength * getDataBusWidth()) / 8; assert(bytesPerBurst > 0); if (numberOfDevicesOnDIMM > 1) { @@ -248,7 +248,7 @@ unsigned int Configuration::getBytesPerBurst() // or burst element has N bytes. N = 2^(# bits for byte offset)). unsigned int burstElementSizeInBytes = AddressDecoder::getInstance().amount.bytes; - assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->BurstLength)); + assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->burstLength)); } return bytesPerBurst; diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index a1935765..df74db3e 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -209,15 +209,15 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec { MemSpec *memSpec = config.memSpec; - memSpec->MemoryId = queryStringParameter(xmlSpec, "memoryId"); - memSpec->MemoryType = queryStringParameter(xmlSpec, "memoryType"); + memSpec->memoryId = queryStringParameter(xmlSpec, "memoryId"); + memSpec->memoryType = queryStringParameter(xmlSpec, "memoryType"); // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); + memSpec->burstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->dataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->numberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->numberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); memSpec->bitWidth = queryUIntParameter(architecture, "width"); // Clock @@ -234,12 +234,12 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -291,12 +291,12 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -370,12 +370,12 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture: XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -421,12 +421,12 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -488,12 +488,12 @@ void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -535,12 +535,12 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for HBM2 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -570,14 +570,14 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tPD = memSpec->tCKE; memSpec->tRDPDE = memSpec->tRL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk; memSpec->tWRPDE = memSpec->tWL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk + memSpec->tWR; memSpec->tWRAPDE = memSpec->tWL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk + memSpec->tWR; memSpec->tCKESR = memSpec->tCKE + memSpec->clk; memSpec->tRDSRE = memSpec->tRL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk; memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRFCSB = clk * queryUIntParameter(timings, "RFCSB"); @@ -597,12 +597,12 @@ void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for GDDR5 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -639,9 +639,9 @@ void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec) memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->t32AW = clk * queryUIntParameter(timings, "32AW"); memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * clk; memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * clk; memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); memSpec->tLK = clk * queryUIntParameter(timings, "LK"); @@ -657,12 +657,12 @@ void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for GDDR5X XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -699,9 +699,9 @@ void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec) memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->t32AW = clk * queryUIntParameter(timings, "32AW"); memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * clk; memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * clk; memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); memSpec->tLK = clk * queryUIntParameter(timings, "LK"); @@ -717,12 +717,12 @@ void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for GDDR6 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -759,9 +759,9 @@ void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec) memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * clk; memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * clk; memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); memSpec->tLK = clk * queryUIntParameter(timings, "LK"); memSpec->tACTPDE = clk * queryUIntParameter(timings, "ACTPDE"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3632316b..03ac9b1b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -44,14 +44,14 @@ using namespace tlm; MemSpec::MemSpec() { - commandLength = std::vector(numberOfCommands(), 1); + commandLengthInCycles = std::vector(numberOfCommands(), 1); } const std::vector &MemSpec::getBanks() const { static std::vector banks; if (banks.size() == 0) { - for (unsigned int i = 0; i < NumberOfBanks; i++) + for (unsigned int i = 0; i < numberOfBanks; i++) banks.push_back(Bank(i)); } return banks; @@ -59,15 +59,15 @@ const std::vector &MemSpec::getBanks() const sc_time MemSpec::getReadAccessTime() const { - return clk * (BurstLength / DataRate); + return clk * (burstLength / dataRate); } sc_time MemSpec::getWriteAccessTime() const { - return clk * (BurstLength / DataRate); + return clk * (burstLength / dataRate); } -unsigned MemSpec::getCommandLength(Command command) const +sc_time MemSpec::getCommandLength(Command command) const { - return commandLength[command]; + return clk * commandLengthInCycles[command]; } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 2dc5d628..f9f4350e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -62,30 +62,30 @@ struct MemSpec virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; - unsigned getCommandLength(Command) const; + sc_time getCommandLength(Command) const; - std::string MemoryId = "not defined."; - std::string MemoryType = "not defined."; + std::string memoryId = "not defined."; + std::string memoryType = "not defined."; - unsigned int NumberOfRanks; - unsigned int NumberOfBankGroups; - unsigned int NumberOfBanks; - unsigned int NumberOfRows; - unsigned int NumberOfColumns; - unsigned int BurstLength; - unsigned int DataRate; + unsigned int numberOfRanks; + unsigned int numberOfBankGroups; + unsigned int numberOfBanks; + unsigned int numberOfRows; + unsigned int numberOfColumns; + unsigned int burstLength; + unsigned int dataRate; unsigned int bitWidth; - unsigned int BanksPerRank; - unsigned int BanksPerGroup; - unsigned int GroupsPerRank; + unsigned int banksPerRank; + unsigned int banksPerGroup; + unsigned int groupsPerRank; // Clock double clkMHz; sc_time clk; // Command lengths on bus, usually one clock cycle - std::vector commandLength; + std::vector commandLengthInCycles; }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 51b21916..26643e26 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -53,16 +53,16 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload return tRP; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD || command == Command::RDA) + else if (command == Command::RD) return tRL + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) + else if (command == Command::RDA) + return tRL + getReadAccessTime(); + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) return tWL + getWriteAccessTime(); else if (command == Command::REFA) return tRFC; - else if (command == Command::REFB) - return tRFC; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; else { SC_REPORT_FATAL("getExecutionTime", diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 0fd8bfb9..ec53fd9a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -59,8 +59,6 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload return tWL + getWriteAccessTime(); else if (command == Command::REFA) return tRFC; - else if (command == Command::REFB) - return tRFC; else { SC_REPORT_FATAL("getExecutionTime", diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 7fa61d1b..6c8065c4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -37,7 +37,7 @@ MemSpecHBM2::MemSpecHBM2() { - commandLength[Command::ACT] = 2; + commandLengthInCycles[Command::ACT] = 2; } sc_time MemSpecHBM2::getRefreshIntervalAB() const diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 106d3c13..d24a9908 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -37,17 +37,17 @@ MemSpecLPDDR4::MemSpecLPDDR4() { - commandLength[Command::ACT] = 4; - commandLength[Command::PRE] = 2; - commandLength[Command::PREA] = 2; - commandLength[Command::RD] = 4; - commandLength[Command::RDA] = 4; - commandLength[Command::WR] = 4; - commandLength[Command::WRA] = 4; - commandLength[Command::REFA] = 2; - commandLength[Command::REFB] = 2; - commandLength[Command::SREFEN] = 2; - commandLength[Command::SREFEX] = 2; + commandLengthInCycles[Command::ACT] = 4; + commandLengthInCycles[Command::PRE] = 2; + commandLengthInCycles[Command::PREA] = 2; + commandLengthInCycles[Command::RD] = 4; + commandLengthInCycles[Command::RDA] = 4; + commandLengthInCycles[Command::WR] = 4; + commandLengthInCycles[Command::WRA] = 4; + commandLengthInCycles[Command::REFA] = 2; + commandLengthInCycles[Command::REFB] = 2; + commandLengthInCycles[Command::SREFEN] = 2; + commandLengthInCycles[Command::SREFEX] = 2; } sc_time MemSpecLPDDR4::getRefreshIntervalAB() const diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 3bb27498..5061cc36 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -38,8 +38,8 @@ BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) { MemSpec *memSpec = Configuration::getInstance().memSpec; - rank = Rank(bank.ID() / memSpec->BanksPerRank); - bankgroup = BankGroup(bank.ID() / memSpec->BanksPerGroup); + rank = Rank(bank.ID() / memSpec->banksPerRank); + bankgroup = BankGroup(bank.ID() / memSpec->banksPerGroup); } std::pair BankMachine::getNextCommand() diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 2831a030..316117b2 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -68,26 +68,26 @@ Controller::Controller(sc_module_name name) : Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; - ranksNumberOfPayloads = std::vector(memSpec->NumberOfRanks); + ranksNumberOfPayloads = std::vector(memSpec->numberOfRanks); // instantiate timing checker - if (memSpec->MemoryType == "DDR3") + if (memSpec->memoryType == "DDR3") checker = new CheckerDDR3(); - else if (memSpec->MemoryType == "DDR4") + else if (memSpec->memoryType == "DDR4") checker = new CheckerDDR4(); - else if (memSpec->MemoryType == "WIDEIO_SDR") + else if (memSpec->memoryType == "WIDEIO_SDR") checker = new CheckerWideIO(); - else if (memSpec->MemoryType == "LPDDR4") + else if (memSpec->memoryType == "LPDDR4") checker = new CheckerLPDDR4(); - else if (memSpec->MemoryType == "WIDEIO2") + else if (memSpec->memoryType == "WIDEIO2") checker = new CheckerWideIO2(); - else if (memSpec->MemoryType == "HBM2") + else if (memSpec->memoryType == "HBM2") checker = new CheckerHBM2(); - else if (memSpec->MemoryType == "GDDR5") + else if (memSpec->memoryType == "GDDR5") checker = new CheckerGDDR5(); - else if (memSpec->MemoryType == "GDDR5X") + else if (memSpec->memoryType == "GDDR5X") checker = new CheckerGDDR5X(); - else if (memSpec->MemoryType == "GDDR6") + else if (memSpec->memoryType == "GDDR6") checker = new CheckerGDDR6(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type!"); @@ -119,37 +119,37 @@ Controller::Controller(sc_module_name name) : // instantiate bank machines (one per bank) if (config.pagePolicy == "Open") { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID))); } else if (config.pagePolicy == "OpenAdaptive") { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID))); } else if (config.pagePolicy == "Closed") { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID))); } else if (config.pagePolicy == "ClosedAdaptive") { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID))); } else SC_REPORT_FATAL("Controller", "Selected page policy not supported!"); - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { - bankMachinesOnRank.push_back(std::vector(bankMachines.begin() + rankID * memSpec->BanksPerRank, - bankMachines.begin() + (rankID + 1) * memSpec->BanksPerRank)); + bankMachinesOnRank.push_back(std::vector(bankMachines.begin() + rankID * memSpec->banksPerRank, + bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank)); } // instantiate power-down managers (one per rank) if (config.powerDownPolicy == "NoPowerDown") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { PowerDownManagerIF *manager = new PowerDownManagerDummy(); powerDownManagers.push_back(manager); @@ -157,7 +157,7 @@ Controller::Controller(sc_module_name name) : } else if (config.powerDownPolicy == "Staggered") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { PowerDownManagerIF *manager = new PowerDownManagerStaggered(Rank(rankID), checker); powerDownManagers.push_back(manager); @@ -171,12 +171,12 @@ Controller::Controller(sc_module_name name) : // instantiate refresh managers (one per rank) if (config.refreshPolicy == "NoRefresh") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) refreshManagers.push_back(new RefreshManagerDummy()); } else if (config.refreshPolicy == "Rankwise") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { RefreshManagerIF *manager = new RefreshManagerRankwise (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); @@ -186,7 +186,7 @@ Controller::Controller(sc_module_name name) : } else if (config.refreshPolicy == "Bankwise") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { // TODO: remove bankMachines in constructor RefreshManagerIF *manager = new RefreshManagerBankwise @@ -264,7 +264,7 @@ void Controller::controllerMethod() std::pair commandPair; std::vector> readyCommands; // (5.1) Check for power-down commands (PDEA/PDEP/SREFEN or PDXA/PDXP/SREFEX) - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { commandPair = powerDownManagers[rankID]->getNextCommand(); if (commandPair.second != nullptr) @@ -333,7 +333,7 @@ void Controller::controllerMethod() readyCmdBlocked = true; } - // (6) Restart bank machines and refresh managers to issue new requests for the future + // (6) Restart bank machines, refresh managers and power-down managers to issue new requests for the future // TODO: check if all calls are necessary sc_time timeForNextTrigger = sc_max_time(); for (auto it : bankMachines) diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index 6abe4569..e07e1780 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -22,8 +22,8 @@ public: virtual ~ControllerIF() { sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec->BurstLength - / Configuration::getInstance().memSpec->DataRate + * Configuration::getInstance().memSpec->burstLength + / Configuration::getInstance().memSpec->dataRate * Configuration::getInstance().memSpec->clk; double bandwidth = (activeTime / sc_time_stamp() * 100); @@ -33,7 +33,7 @@ public: // clk in Mhz e.g. 800 [MHz]: (1000000 / Configuration::getInstance().memSpec->clk.to_double()) // DataRate e.g. 2 - * Configuration::getInstance().memSpec->DataRate + * Configuration::getInstance().memSpec->dataRate // BusWidth e.g. 8 or 64 * Configuration::getInstance().memSpec->bitWidth // Number of devices on a DIMM e.g. 8 diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 0c7ecb6a..3b9462a9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -42,14 +42,14 @@ CheckerDDR3::CheckerDDR3() SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk; } sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index e4ca5462..6272c328 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -42,16 +42,16 @@ CheckerDDR4::CheckerDDR4() SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk; } sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 9ea840bf..a67ed71a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -42,17 +42,17 @@ CheckerGDDR5::CheckerGDDR5() SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->NumberOfRanks); - last32Activates = std::vector>(memSpec->NumberOfRanks); + last4Activates = std::vector>(memSpec->numberOfRanks); + last32Activates = std::vector>(memSpec->numberOfRanks); - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk; } sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -338,5 +338,5 @@ void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 06cbddfe..d84c715f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -42,17 +42,17 @@ CheckerGDDR5X::CheckerGDDR5X() SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->NumberOfRanks); - last32Activates = std::vector>(memSpec->NumberOfRanks); + last4Activates = std::vector>(memSpec->numberOfRanks); + last32Activates = std::vector>(memSpec->numberOfRanks); - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk; } sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -338,5 +338,5 @@ void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index b9313dd5..d93c0b71 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -42,16 +42,16 @@ CheckerGDDR6::CheckerGDDR6() SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk; } sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -327,5 +327,5 @@ void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 1b7de13f..c1b45e3d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -42,17 +42,17 @@ CheckerHBM2::CheckerHBM2() SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); - bankwiseRefreshCounter = std::vector(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); + bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); - burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; + burstClocks = (memSpec->burstLength / 2) * memSpec->clk; } sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -325,7 +325,7 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA || command == Command::WR || command == Command::WRA) + if (isCasCommand(command)) lastCommandOnCASBus = sc_time_stamp(); else if (command == Command::ACT) lastCommandOnRASBus = sc_time_stamp() + memSpec->clk; @@ -340,5 +340,5 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b } if (command == Command::REFB) - bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 5f7da450..de447df5 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -42,12 +42,12 @@ CheckerLPDDR4::CheckerLPDDR4() SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -280,7 +280,7 @@ void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - lastCommandOnBus = sc_time_stamp() + (memSpec->getCommandLength(command) - 1) * memSpec->clk; + lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->clk; if (command == Command::ACT || command == Command::REFB) { diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 7250f4bd..ee1b6552 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -42,14 +42,14 @@ CheckerWideIO::CheckerWideIO() SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); - burstClocks = memSpec->BurstLength * memSpec->clk; + burstClocks = memSpec->burstLength * memSpec->clk; } sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 5230dfa7..4ca29658 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -42,12 +42,12 @@ CheckerWideIO2::CheckerWideIO2() SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); } sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 899d93e3..7c87a9b9 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -45,23 +45,23 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM memSpec = config.memSpec; timeForNextTrigger = memSpec->getRefreshIntervalPB(); - refreshPayloads = std::vector(memSpec->BanksPerRank); - for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) + refreshPayloads = std::vector(memSpec->banksPerRank); + for (unsigned bankID = 0; bankID < memSpec->banksPerRank; bankID++) { setUpDummy(refreshPayloads[bankID], rank, bankMachines[bankID]->getBank()); allBankMachines.push_back(bankMachines[bankID]); } remainingBankMachines = allBankMachines; - maxPostponed = config.refreshMaxPostponed * memSpec->BanksPerRank; - maxPulledin = -(config.refreshMaxPulledin * memSpec->BanksPerRank); + maxPostponed = config.refreshMaxPostponed * memSpec->banksPerRank; + maxPulledin = -(config.refreshMaxPulledin * memSpec->banksPerRank); } std::pair RefreshManagerBankwise::getNextCommand() { if (sc_time_stamp() == timeToSchedule) return std::pair - (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); + (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->banksPerRank]); else return std::pair(Command::NOP, nullptr); } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 47b67b86..d90d8dd6 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -37,7 +37,7 @@ SchedulerFifo::SchedulerFifo() { buffer = std::vector> - (Configuration::getInstance().memSpec->NumberOfBanks); + (Configuration::getInstance().memSpec->numberOfBanks); requestBufferSize = Configuration::getInstance().requestBufferSize; } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 667430d7..0262e009 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -39,7 +39,7 @@ SchedulerFrFcfs::SchedulerFrFcfs() { buffer = std::vector> - (Configuration::getInstance().memSpec->NumberOfBanks); + (Configuration::getInstance().memSpec->numberOfBanks); requestBufferSize = Configuration::getInstance().requestBufferSize; } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index 109fd78d..077c6f9d 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -37,7 +37,7 @@ SchedulerFrFcfsGrp::SchedulerFrFcfsGrp() { buffer = std::vector> - (Configuration::getInstance().memSpec->NumberOfBanks); + (Configuration::getInstance().memSpec->numberOfBanks); requestBufferSize = Configuration::getInstance().requestBufferSize; } diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index 6a14a16f..5cc06fe3 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -46,15 +46,15 @@ void errorModel::init() powerAnalysis = Configuration::getInstance().powerAnalysis; thermalSim = Configuration::getInstance().thermalSimulation; // Get Configuration parameters: - burstLenght = Configuration::getInstance().memSpec->BurstLength; - numberOfColumns = Configuration::getInstance().memSpec->NumberOfColumns; + burstLenght = Configuration::getInstance().memSpec->burstLength; + numberOfColumns = Configuration::getInstance().memSpec->numberOfColumns; bytesPerColumn = AddressDecoder::getInstance().amount.bytes; // Adjust number of bytes per column dynamically to the selected ecc controller bytesPerColumn = Configuration::getInstance().adjustNumBytesAfterECC( bytesPerColumn); - numberOfRows = Configuration::getInstance().memSpec->NumberOfRows; + numberOfRows = Configuration::getInstance().memSpec->numberOfRows; numberOfBitErrorEvents = 0; @@ -253,7 +253,7 @@ void errorModel::markBitFlips() { double temp = getTemperature(); for (unsigned int row = 0; - row < Configuration::getInstance().memSpec->NumberOfRows; row++) { + row < Configuration::getInstance().memSpec->numberOfRows; row++) { // If the row has never been accessed ignore it and go to the next one if (lastRowAccess[row] != SC_ZERO_TIME) { // Get the time interval between now and the last acivate/refresh diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 1cb1719c..7eabae3e 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -246,7 +246,7 @@ void DRAMSys::instantiateModules(const std::string &traceName, arbiter = new Arbiter("arbiter"); // Create DRAM - std::string memoryType = Configuration::getInstance().memSpec->MemoryType; + std::string memoryType = Configuration::getInstance().memSpec->memoryType; for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index 94bb2fae..76ca8562 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -60,7 +60,7 @@ public: SC_REPORT_FATAL(0, (std::string("Could not open trace ") + pathToTrace).c_str()); this->playerClk = playerClk; - this->burstlength = Configuration::getInstance().memSpec->BurstLength; + this->burstlength = Configuration::getInstance().memSpec->burstLength; this->dataLength = Configuration::getInstance().getBytesPerBurst(); this->lineCnt = 0; } diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index 3b9dec6b..56a9877e 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -53,7 +53,7 @@ public: else clk = sc_time(1.0 / clkMhz, SC_US); - this->burstlenght = Configuration::getInstance().memSpec->BurstLength; + this->burstlenght = Configuration::getInstance().memSpec->burstLength; } virtual void nextPayload() override diff --git a/DRAMSys/library/src/simulation/TracePlayerListener.h b/DRAMSys/library/src/simulation/TracePlayerListener.h index 430c10a0..b05ccd74 100644 --- a/DRAMSys/library/src/simulation/TracePlayerListener.h +++ b/DRAMSys/library/src/simulation/TracePlayerListener.h @@ -43,7 +43,7 @@ class TracePlayerListener public: virtual void tracePlayerTerminates() = 0; virtual void transactionFinished() = 0; - virtual ~TracePlayerListener() {}; + virtual ~TracePlayerListener() {} }; #endif // TRACEPLAYERLISTENER_H diff --git a/DRAMSys/library/src/simulation/TraceSetup.cpp b/DRAMSys/library/src/simulation/TraceSetup.cpp index 70d4507c..778b25ac 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.cpp +++ b/DRAMSys/library/src/simulation/TraceSetup.cpp @@ -35,7 +35,7 @@ #include "TraceSetup.h" -traceSetup::traceSetup(std::string uri, +TraceSetup::TraceSetup(std::string uri, std::string pathToResources, std::vector *devices) { @@ -102,18 +102,18 @@ traceSetup::traceSetup(std::string uri, } remainingTransactions = totalTransactions; - NumberOfTracePlayers = devices->size(); + numberOfTracePlayers = devices->size(); } -void traceSetup::tracePlayerTerminates() +void TraceSetup::tracePlayerTerminates() { finishedTracePlayers++; - if (finishedTracePlayers == NumberOfTracePlayers) { + if (finishedTracePlayers == numberOfTracePlayers) { sc_stop(); } } -void traceSetup::transactionFinished() +void TraceSetup::transactionFinished() { remainingTransactions--; diff --git a/DRAMSys/library/src/simulation/TraceSetup.h b/DRAMSys/library/src/simulation/TraceSetup.h index 49f91049..a65ae1f2 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.h +++ b/DRAMSys/library/src/simulation/TraceSetup.h @@ -44,19 +44,19 @@ #include "StlPlayer.h" -class traceSetup : public TracePlayerListener +class TraceSetup : public TracePlayerListener { public: - traceSetup(std::string uri, + TraceSetup(std::string uri, std::string pathToResources, std::vector *devices); virtual void tracePlayerTerminates() override; virtual void transactionFinished() override; - virtual ~traceSetup() {}; + virtual ~TraceSetup() {} private: - unsigned int NumberOfTracePlayers; + unsigned int numberOfTracePlayers; unsigned int totalTransactions = 0; unsigned int remainingTransactions; unsigned int finishedTracePlayers = 0; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index 736dad5d..76335e4f 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -55,14 +55,14 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) sc_time clk = memSpec->clk; MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.dataRate = memSpec->dataRate; + memArchSpec.nbrOfRows = memSpec->numberOfRows; + memArchSpec.nbrOfBanks = memSpec->numberOfBanks; + memArchSpec.nbrOfColumns = memSpec->numberOfColumns; + memArchSpec.nbrOfRanks = memSpec->numberOfRanks; memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups; memArchSpec.twoVoltageDomains = false; memArchSpec.dll = true; @@ -134,8 +134,8 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memPowerSpec.vdd2 = 0; MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; + powerSpec.id = memSpec->memoryId; + powerSpec.memoryType = memSpec->memoryType; powerSpec.memTimingSpec = memTimingSpec; powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 5082b2f7..b924435a 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -55,14 +55,14 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) sc_time clk = memSpec->clk; MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.dataRate = memSpec->dataRate; + memArchSpec.nbrOfRows = memSpec->numberOfRows; + memArchSpec.nbrOfBanks = memSpec->numberOfBanks; + memArchSpec.nbrOfColumns = memSpec->numberOfColumns; + memArchSpec.nbrOfRanks = memSpec->numberOfRanks; memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups; memArchSpec.twoVoltageDomains = true; memArchSpec.dll = true; @@ -134,8 +134,8 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memPowerSpec.vdd2 = memSpec->vDD2; MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; + powerSpec.id = memSpec->memoryId; + powerSpec.memoryType = memSpec->memoryType; powerSpec.memTimingSpec = memTimingSpec; powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index e08c764b..fa14377c 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -89,11 +89,11 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); + recTime += this->memSpec->getCommandLength(Command::PDXA); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); + recTime += this->memSpec->getCommandLength(Command::PDXP); else if (phase == END_SREF || phase == END_SREFB) - recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); + recTime += this->memSpec->getCommandLength(Command::SREFEX); unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch __attribute__((unused)) = DramExtension::getExtension(payload).getChannel().ID(); diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index c6733ddb..4c8ba3c9 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -57,14 +57,14 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) sc_time clk = memSpec->clk; MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.dataRate = memSpec->dataRate; + memArchSpec.nbrOfRows = memSpec->numberOfRows; + memArchSpec.nbrOfBanks = memSpec->numberOfBanks; + memArchSpec.nbrOfColumns = memSpec->numberOfColumns; + memArchSpec.nbrOfRanks = memSpec->numberOfRanks; memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups; memArchSpec.twoVoltageDomains = true; memArchSpec.dll = false; @@ -77,9 +77,9 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = 0; - memTimingSpec.CCD = memSpec->BurstLength; - memTimingSpec.CCD_L = memSpec->BurstLength; - memTimingSpec.CCD_S = memSpec->BurstLength; + memTimingSpec.CCD = memSpec->burstLength; + memTimingSpec.CCD_L = memSpec->burstLength; + memTimingSpec.CCD_S = memSpec->burstLength; memTimingSpec.CKE = memSpec->tCKE / clk; memTimingSpec.CKESR = memSpec->tCKESR / clk; memTimingSpec.clkMhz = memSpec->clkMHz; @@ -97,7 +97,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.RRD = memSpec->tRRD / clk; memTimingSpec.RRD_L = memSpec->tRRD / clk; memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->BurstLength; + memTimingSpec.RTP = memSpec->burstLength; memTimingSpec.TAW = memSpec->tTAW / clk; memTimingSpec.WL = memSpec->tWL / clk; memTimingSpec.WR = memSpec->tWR / clk; @@ -136,8 +136,8 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memPowerSpec.vdd2 = memSpec->vDD2; MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; + powerSpec.id = memSpec->memoryId; + powerSpec.memoryType = memSpec->memoryType; powerSpec.memTimingSpec = memTimingSpec; powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; @@ -147,7 +147,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) // For each bank in a channel a error Model is created: if (storeMode == StorageMode::ErrorModel) { - for (unsigned i = 0; i < memSpec->NumberOfBanks; i++) + for (unsigned i = 0; i < memSpec->numberOfBanks; i++) { errorModel *em; std::string errorModelStr = "errorModel_bank" + std::to_string(i); diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index f782faf4..cf231c5f 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -88,7 +88,7 @@ int sc_main(int argc, char **argv) DRAMSys *dramSys = new DRAMSys("DRAMSys", SimulationXML, resources); // Instantiate STL Players: - traceSetup *ts = new traceSetup(SimulationXML, resources, &players); + TraceSetup *ts = new TraceSetup(SimulationXML, resources, &players); // Bind STL Players with DRAMSys: for (size_t i = 0; i < players.size(); i++) {