From 6c0ebb0e880ca21f919bec574c4c1c906ff1afbd Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 3 Apr 2020 15:00:51 +0200 Subject: [PATCH] Minor changes in DRAM and controller. --- DRAMSys/library/CMakeLists.txt | 1 - DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- DRAMSys/library/src/common/protocol.h | 69 ---------- .../library/src/controller/BankMachine.cpp | 28 ++-- DRAMSys/library/src/controller/Command.cpp | 23 ++++ DRAMSys/library/src/controller/Command.h | 30 ++++- DRAMSys/library/src/controller/Controller.cpp | 1 - .../src/controller/ControllerRecordable.cpp | 1 - .../powerdown/PowerDownManagerStaggered.cpp | 53 ++++---- .../powerdown/PowerDownManagerStaggered.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 22 +-- .../refresh/RefreshManagerRankwise.cpp | 32 +++-- DRAMSys/library/src/simulation/dram/Dram.cpp | 86 +++--------- DRAMSys/library/src/simulation/dram/Dram.h | 3 +- .../library/src/simulation/dram/DramDDR3.cpp | 11 +- .../library/src/simulation/dram/DramDDR4.cpp | 11 +- .../library/src/simulation/dram/DramGDDR5.cpp | 9 +- .../src/simulation/dram/DramGDDR5X.cpp | 9 +- .../library/src/simulation/dram/DramGDDR6.cpp | 9 +- .../library/src/simulation/dram/DramHBM2.cpp | 9 +- .../src/simulation/dram/DramLPDDR4.cpp | 9 +- .../src/simulation/dram/DramRecordable.cpp | 15 +-- .../src/simulation/dram/DramRecordable.h | 1 - .../src/simulation/dram/DramWideIO.cpp | 127 +++++------------- .../src/simulation/dram/DramWideIO2.cpp | 9 +- 25 files changed, 197 insertions(+), 375 deletions(-) delete mode 100644 DRAMSys/library/src/common/protocol.h diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index f0b04c92..31729d23 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -69,7 +69,6 @@ add_library(DRAMSysLibrary src/common/CongenAddressDecoder.cpp src/common/DebugManager.cpp src/common/dramExtensions.cpp - src/common/protocol.h src/common/tlm2_base_protocol_checker.h src/common/TlmRecorder.cpp src/common/utils.cpp diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 4357843a..0258da37 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -40,10 +40,10 @@ #include #include "TlmRecorder.h" -#include "protocol.h" #include "dramExtensions.h" #include "XmlAddressDecoder.h" #include "../configuration/Configuration.h" +#include "../controller/Command.h" using namespace tlm; diff --git a/DRAMSys/library/src/common/protocol.h b/DRAMSys/library/src/common/protocol.h deleted file mode 100644 index 9f7be6be..00000000 --- a/DRAMSys/library/src/common/protocol.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef PROTOCOL_H -#define PROTOCOL_H - -// DO NOT CHANGE THE ORDER! -DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5 -DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6 -DECLARE_EXTENDED_PHASE(BEGIN_RDA); // 7 -DECLARE_EXTENDED_PHASE(BEGIN_WRA); // 8 -DECLARE_EXTENDED_PHASE(BEGIN_PRE); // 9 -DECLARE_EXTENDED_PHASE(BEGIN_ACT); // 10 -DECLARE_EXTENDED_PHASE(BEGIN_REFB); // 11 -DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 12 -DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 13 -DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 14 -DECLARE_EXTENDED_PHASE(END_PDNA); // 15 -DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 16 -DECLARE_EXTENDED_PHASE(END_PDNP); // 17 -DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18 -DECLARE_EXTENDED_PHASE(END_SREF); // 19 - -DECLARE_EXTENDED_PHASE(END_RD); // 20 -DECLARE_EXTENDED_PHASE(END_WR); // 21 -DECLARE_EXTENDED_PHASE(END_RDA); // 22 -DECLARE_EXTENDED_PHASE(END_WRA); // 23 -DECLARE_EXTENDED_PHASE(END_PRE); // 24 -DECLARE_EXTENDED_PHASE(END_ACT); // 25 -DECLARE_EXTENDED_PHASE(END_REFB); // 26 -DECLARE_EXTENDED_PHASE(END_PREA); // 27 -DECLARE_EXTENDED_PHASE(END_REFA); // 28 - -#endif // PROTOCOL_H - diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 5061cc36..4c20a76a 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -52,29 +52,33 @@ std::pair BankMachine::getNextCommand() void BankMachine::updateState(Command command) { - if (command == Command::ACT) + switch (command) { + case Command::ACT: currentState = BmState::Activated; currentRow = DramExtension::getRow(currentPayload); - } - else if (command == Command::PRE || command == Command::PREA) + break; + case Command::PRE: case Command::PREA: currentState = BmState::Precharged; - else if (command == Command::RD || command == Command::WR) + break; + case Command::RD: case Command::WR: currentPayload = nullptr; - else if (command == Command::RDA || command == Command::WRA) - { + break; + case Command::RDA: case Command::WRA: currentState = BmState::Precharged; currentPayload = nullptr; - } - else if (command == Command::PDEA || command == Command::PDEP || command == Command::SREFEN) + break; + case Command::PDEA: case Command::PDEP: case Command::SREFEN: sleeping = true; - else if (command == Command::REFA || command == Command::REFB) - { + break; + case Command::REFA: case Command::REFB: sleeping = false; blocked = false; - } - else if (command == Command::PDXA || command == Command::PDXP) + break; + case Command::PDXA: case Command::PDXP: sleeping = false; + break; + } } void BankMachine::block() diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 7c15c931..9fd3e0c7 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -38,6 +38,7 @@ #include "Command.h" #include +using namespace DRAMPower; std::string commandToString(Command command) { @@ -112,6 +113,28 @@ Command phaseToCommand(tlm_phase phase) return commandOfPhase[phase - 5]; } +MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) +{ + assert(phase >= 5 && phase <= 19); + static std::array phaseOfCommand = + {MemCommand::RD, + MemCommand::WR, + MemCommand::RDA, + MemCommand::WRA, + MemCommand::PRE, + MemCommand::ACT, + MemCommand::REFB, + MemCommand::PREA, + MemCommand::REF, + MemCommand::PDN_S_ACT, + MemCommand::PUP_ACT, + MemCommand::PDN_S_PRE, + MemCommand::PUP_PRE, + MemCommand::SREN, + MemCommand::SREX}; + return phaseOfCommand[phase - 5]; +} + bool phaseNeedsEnd(tlm_phase phase) { return (phase >= 5 && phase <= 13); diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index b9be24b1..9f49ea2b 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -40,10 +40,37 @@ #include #include #include -#include "../common/protocol.h" +#include "../common/third_party/DRAMPower/src/MemCommand.h" using namespace tlm; +// DO NOT CHANGE THE ORDER! +DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5 +DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6 +DECLARE_EXTENDED_PHASE(BEGIN_RDA); // 7 +DECLARE_EXTENDED_PHASE(BEGIN_WRA); // 8 +DECLARE_EXTENDED_PHASE(BEGIN_PRE); // 9 +DECLARE_EXTENDED_PHASE(BEGIN_ACT); // 10 +DECLARE_EXTENDED_PHASE(BEGIN_REFB); // 11 +DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 12 +DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 13 +DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 14 +DECLARE_EXTENDED_PHASE(END_PDNA); // 15 +DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 16 +DECLARE_EXTENDED_PHASE(END_PDNP); // 17 +DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18 +DECLARE_EXTENDED_PHASE(END_SREF); // 19 + +DECLARE_EXTENDED_PHASE(END_RD); // 20 +DECLARE_EXTENDED_PHASE(END_WR); // 21 +DECLARE_EXTENDED_PHASE(END_RDA); // 22 +DECLARE_EXTENDED_PHASE(END_WRA); // 23 +DECLARE_EXTENDED_PHASE(END_PRE); // 24 +DECLARE_EXTENDED_PHASE(END_ACT); // 25 +DECLARE_EXTENDED_PHASE(END_REFB); // 26 +DECLARE_EXTENDED_PHASE(END_PREA); // 27 +DECLARE_EXTENDED_PHASE(END_REFA); // 28 + enum Command { NOP, @@ -67,6 +94,7 @@ enum Command std::string commandToString(Command); tlm_phase commandToPhase(Command); Command phaseToCommand(tlm_phase); +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase); bool phaseNeedsEnd(tlm_phase); tlm_phase getEndPhase(tlm_phase); unsigned numberOfCommands(); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 7d5037f3..ee32349e 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -36,7 +36,6 @@ #include "../configuration/Configuration.h" #include "../common/dramExtensions.h" -#include "../common/protocol.h" #include "Command.h" #include "checker/CheckerDDR3.h" #include "checker/CheckerDDR4.h" diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 97b1a542..c0e90278 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -34,7 +34,6 @@ #include "ControllerRecordable.h" -#include "../common/protocol.h" #include "../configuration/Configuration.h" tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index b1ca8298..098f5c51 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -112,45 +112,44 @@ sc_time PowerDownManagerStaggered::start() void PowerDownManagerStaggered::updateState(Command command) { - if (command == Command::ACT) - activatedBanks++; - else if (command == Command::PRE) - activatedBanks--; - else if (command == Command::PREA) - activatedBanks = 0; - else if (command == Command::PDEA) + switch (command) { + case Command::ACT: + activatedBanks++; + break; + case Command::PRE: + activatedBanks--; + break; + case Command::PREA: + activatedBanks = 0; + break; + case Command::PDEA: state = PdmState::ActivePdn; entryTriggered = false; - } - else if (command == Command::PDEP) - { + break; + case Command::PDEP: state = PdmState::PrechargePdn; entryTriggered = false; - } - else if (command == Command::SREFEN) - { + break; + case Command::SREFEN: state = PdmState::SelfRefresh; entryTriggered = false; enterSelfRefresh = false; - } - else if (command == Command::PDXA) - { + break; + case Command::PDXA: state = PdmState::Idle; exitTriggered = false; - } - else if (command == Command::PDXP) - { + break; + case Command::PDXP: state = PdmState::Idle; exitTriggered = false; - if (controllerIdle) enterSelfRefresh = true; - } - else if (command == Command::SREFEX) + break; + case Command::SREFEX: state = PdmState::ExtraRefresh; - else if (command == Command::REFA) - { + break; + case Command::REFA: if (state == PdmState::ExtraRefresh) { state = PdmState::Idle; @@ -158,10 +157,10 @@ void PowerDownManagerStaggered::updateState(Command command) } else if (controllerIdle) entryTriggered = true; - } - else if (command == Command::REFB) - { + break; + case Command::REFB: if (controllerIdle) entryTriggered = true; + break; } } diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h index c11f086f..83048ca8 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h @@ -60,7 +60,7 @@ private: Rank rank; CheckerIF *checker; - sc_time timeToSchedule; + sc_time timeToSchedule = sc_max_time(); Command nextCommand; bool controllerIdle = true; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 55de87b7..5e534b6b 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -156,8 +156,9 @@ sc_time RefreshManagerBankwise::start() void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *payload) { - if (command == Command::REFB) + switch (command) { + case Command::REFB: remainingBankMachines.erase(currentIterator); if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; @@ -172,21 +173,22 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalPB(); } - } - else if (command == Command::REFA) - { + break; + case Command::REFA: // Refresh command after SREFEX state = RmState::Regular; // TODO: check if this assignment is necessary timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalPB(); sleeping = false; - } - else if (command == Command::PDEA || command == Command::PDEP) + break; + case Command::PDEA: case Command::PDEP: sleeping = true; - else if (command == Command::SREFEN) - { + break; + case Command::SREFEN: sleeping = true; timeForNextTrigger = sc_max_time(); - } - else if (command == Command::PDXA || command == Command::PDXP) + break; + case Command::PDXA: case Command::PDXP: sleeping = false; + break; + } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp index c14f30fc..9af8bde4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp @@ -140,14 +140,18 @@ sc_time RefreshManagerRankwise::start() void RefreshManagerRankwise::updateState(Command command, tlm_generic_payload *) { - if (command == Command::ACT) - activatedBanks++; - else if (command == Command::PRE) - activatedBanks--; - else if (command == Command::PREA) - activatedBanks = 0; - else if (command == Command::REFA) + switch (command) { + case Command::ACT: + activatedBanks++; + break; + case Command::PRE: + activatedBanks--; + break; + case Command::PREA: + activatedBanks = 0; + break; + case Command::REFA: if (sleeping) { // Refresh command after SREFEX @@ -168,14 +172,16 @@ void RefreshManagerRankwise::updateState(Command command, tlm_generic_payload *) timeForNextTrigger += memSpec->getRefreshIntervalAB(); } } - } - else if (command == Command::PDEA || command == Command::PDEP) + break; + case Command::PDEA: case Command::PDEP: sleeping = true; - else if (command == Command::SREFEN) - { + break; + case Command::SREFEN: sleeping = true; timeForNextTrigger = sc_max_time(); - } - else if (command == Command::PDXA || command == Command::PDXP) + break; + case Command::PDXA: case Command::PDXP: sleeping = false; + break; + } } diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 5eee8b93..feaea294 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -55,10 +55,10 @@ #include "../../common/DebugManager.h" #include "../../common/dramExtensions.h" #include "../../configuration/Configuration.h" -#include "../../common/protocol.h" #include "../../common/utils.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../common/third_party/DRAMPower/src/MemCommand.h" +#include "../../controller/Command.h" using namespace tlm; using namespace DRAMPower; @@ -107,10 +107,6 @@ Dram::~Dram() { if (Configuration::getInstance().powerAnalysis) { - libDRAMPower *DRAMPower = dynamic_cast(this->DRAMPower); - if (DRAMPower == nullptr) - SC_REPORT_FATAL("Dram", "Power Analysis active but libDRAMPowerIF instantiated"); - if (!Configuration::getInstance().databaseRecording) DRAMPower->calcEnergy(); @@ -128,8 +124,9 @@ Dram::~Dram() << DRAMPower->getPower().average_power * Configuration::getInstance().numberOfDevicesOnDIMM << std::string(" mW") << std::endl; + + delete DRAMPower; } - delete DRAMPower; if (Configuration::getInstance().useMalloc) free(memory); @@ -138,75 +135,28 @@ Dram::~Dram() tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &) { - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + assert(phase >= 5 && phase <= 19); - // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp() / memSpec->tCK; - - if (phase == BEGIN_PRE) - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - else if (phase == BEGIN_PREA) - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - else if (phase == BEGIN_ACT) - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - else if (phase == BEGIN_WR) + if (Configuration::getInstance().powerAnalysis) { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); - // save data: - if (storeMode == StorageMode::Store) // Use Storage + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned long long cycle = sc_time_stamp() / memSpec->tCK; + DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); + } + + if (storeMode == StorageMode::Store) + { + if (phase == BEGIN_RD || phase == BEGIN_RDA) + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); + } + else if (phase == BEGIN_WR || phase == BEGIN_WRA) { unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } } - else if (phase == BEGIN_RD) - { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); - // load data: - if (storeMode == StorageMode::Store) // use StorageMode - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - } - else if (phase == BEGIN_WRA) - { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); - // save data: - if (storeMode == StorageMode::Store) // Use Storage - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } - } - else if (phase == BEGIN_RDA) - { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); - // Load data: - if (storeMode == StorageMode::Store) // use StorageMode - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - } - else if (phase == BEGIN_REFA) - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - else if (phase == BEGIN_REFB) - DRAMPower->doCommand(MemCommand::REFB, bank, cycle); - else if (phase == BEGIN_PDNA) - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); - else if (phase == END_PDNA) - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); - else if (phase == BEGIN_PDNP) - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); - else if (phase == END_PDNP) - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); - else if (phase == BEGIN_SREF) - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); - else if (phase == END_SREF) - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); - else - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); return TLM_ACCEPTED; } diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 2386ab35..3995ac99 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -43,7 +43,6 @@ #include #include #include -#include "../../common/protocol.h" #include "../../configuration/Configuration.h" #include "../../configuration/memspec/MemSpec.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" @@ -67,7 +66,7 @@ protected: unsigned char *memory; - libDRAMPowerDummy *DRAMPower; + libDRAMPower *DRAMPower; virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay); diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index 9b2910ab..5f30ad02 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -45,13 +45,12 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); - // Parameters for DRAMPower - MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) { + MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); + MemArchitectureSpec memArchSpec; memArchSpec.burstLength = memSpec->burstLength; memArchSpec.dataRate = memSpec->dataRate; @@ -140,6 +139,4 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) DRAMPower = new libDRAMPower(powerSpec, 0); } - else - DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 9bc518f1..39a21935 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -45,13 +45,12 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); - // Parameters for DRAMPower - MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) { + MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); + MemArchitectureSpec memArchSpec; memArchSpec.burstLength = memSpec->burstLength; memArchSpec.dataRate = memSpec->dataRate; @@ -140,6 +139,4 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) DRAMPower = new libDRAMPower(powerSpec, 0); } - else - DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp index 773aa690..3d5f2e48 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp @@ -45,13 +45,6 @@ DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5"); - // Parameters for DRAMPower - MemSpecGDDR5 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramGDDR5", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) - SC_REPORT_FATAL("DramGDDR5", "DRAMPower not supported for GDDR5"); - else - DRAMPower = new libDRAMPowerDummy(); + SC_REPORT_FATAL("DramGDDR5", "DRAMPower does not support GDDR5"); } diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp index 5342a5e5..48105864 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp @@ -45,13 +45,6 @@ DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X"); - // Parameters for DRAMPower - MemSpecGDDR5X *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramGDDR5X", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) - SC_REPORT_FATAL("DramGDDR5X", "DRAMPower not supported for GDDR5X"); - else - DRAMPower = new libDRAMPowerDummy(); + SC_REPORT_FATAL("DramGDDR5X", "DRAMPower does not support GDDR5X"); } diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp index 029d000d..9ff895ee 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp @@ -45,13 +45,6 @@ DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6"); - // Parameters for DRAMPower - MemSpecGDDR6 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramGDDR6", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) - SC_REPORT_FATAL("DramGDDR6", "DRAMPower not supported for GDDR6"); - else - DRAMPower = new libDRAMPowerDummy(); + SC_REPORT_FATAL("DramGDDR6", "DRAMPower does not support GDDR6"); } diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp index 735e5256..395ca2da 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp @@ -45,13 +45,6 @@ DramHBM2::DramHBM2(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2"); - // Parameters for DRAMPower - MemSpecHBM2 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramHBM2", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) - SC_REPORT_FATAL("DramHBM2", "DRAMPower not supported for HBM2"); - else - DRAMPower = new libDRAMPowerDummy(); + SC_REPORT_FATAL("DramHBM2", "DRAMPower does not support HBM2"); } diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp index c09c5d5b..3587606c 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp @@ -45,13 +45,6 @@ DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4"); - // Parameters for DRAMPower - MemSpecLPDDR4 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramLPDDR4", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) - SC_REPORT_FATAL("DramLPDDR4", "DRAMPower not supported for LPDDR4"); - else - DRAMPower = new libDRAMPowerDummy(); + SC_REPORT_FATAL("DramLPDDR4", "DRAMPower does not support LPDDR4"); } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 8c090b50..ecf88f5b 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -58,12 +58,7 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe // Create a thread that is triggered every $powerWindowSize // to generate a Power over Time plot in the Trace analyzer: if (Configuration::getInstance().powerAnalysis) - { - DRAMPower = dynamic_cast(Dram::DRAMPower); - if (DRAMPower == nullptr) - SC_REPORT_FATAL("DramRecordable", "Power Analysis active but libDRAMPowerIF instantiated"); SC_THREAD(powerWindow); - } } template @@ -71,9 +66,9 @@ DramRecordable::~DramRecordable() { if (Configuration::getInstance().powerAnalysis) { - DRAMPower->calcEnergy(); + this->DRAMPower->calcEnergy(); tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power + this->DRAMPower->getPower().window_average_power * Configuration::getInstance().numberOfDevicesOnDIMM); } tlmRecorder->closeConnection(); @@ -133,14 +128,14 @@ void DramRecordable::powerWindow() clkCycles = sc_time_stamp() / this->memSpec->tCK; - DRAMPower->calcWindowEnergy(clkCycles); + this->DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(this->DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power + this->DRAMPower->getPower().window_average_power * Configuration::getInstance().numberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h index 507ce270..f0091c21 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -60,7 +60,6 @@ private: TlmRecorder *tlmRecorder; - libDRAMPower *DRAMPower; sc_time powerWindowSize = Configuration::getInstance().memSpec->tCK * Configuration::getInstance().windowSize; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index e3008c27..2aff7fdd 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -47,13 +47,12 @@ using namespace tlm; DramWideIO::DramWideIO(sc_module_name name) : Dram(name) { - // Parameters for DRAMPower - MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) { + MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); + MemArchitectureSpec memArchSpec; memArchSpec.burstLength = memSpec->burstLength; memArchSpec.dataRate = memSpec->dataRate; @@ -140,7 +139,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; - libDRAMPower *DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, 0); // For each bank in a channel a error Model is created: if (storeMode == StorageMode::ErrorModel) @@ -153,13 +152,11 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) ememory.push_back(em); } } - this->DRAMPower = DRAMPower; } else { if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramWideIO", "Error modeling without power analysis is not supported"); - DRAMPower = new libDRAMPowerDummy(); } } @@ -173,101 +170,41 @@ DramWideIO::~DramWideIO() tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &) { - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + assert(phase >= 5 && phase <= 19); - // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp() / memSpec->tCK; - - if (phase == BEGIN_PRE) - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - else if (phase == BEGIN_PREA) - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - else if (phase == BEGIN_ACT) + if (Configuration::getInstance().powerAnalysis) { - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + unsigned bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned long long cycle = sc_time_stamp() / memSpec->tCK; + DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); + } - if (storeMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::Store) + { + if (phase == BEGIN_RD || phase == BEGIN_RDA) + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); + } + else if (phase == BEGIN_WR || phase == BEGIN_WRA) + { + unsigned char *phyAddr = memory + payload.get_address(); + memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); + } + } + else if (storeMode == StorageMode::ErrorModel) + { + unsigned bank = DramExtension::getExtension(payload).getBank().ID(); + + if (phase == BEGIN_ACT) ememory[bank]->activate(DramExtension::getExtension(payload).getRow().ID()); - } - else if (phase == BEGIN_WR) - { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); - // save data: - if (storeMode == StorageMode::Store) // Use Storage - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } - else if (storeMode == StorageMode::ErrorModel) // Use Storage with Error Model - { - ememory[bank]->store(payload); - } - } - else if (phase == BEGIN_RD) - { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); - // load data: - if (storeMode == StorageMode::Store) // use StorageMode - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - else if (storeMode == StorageMode::ErrorModel) // use StorageMode with errormodel - { + else if (phase == BEGIN_RD || phase == BEGIN_RDA) ememory[bank]->load(payload); - } - } - else if (phase == BEGIN_WRA) - { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); - // save data: - if (storeMode == StorageMode::Store) // Use Storage - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } - else if (storeMode == StorageMode::ErrorModel) // Use Storage with Error Model - { + else if (phase == BEGIN_WR || phase == BEGIN_WRA) ememory[bank]->store(payload); - } - } - else if (phase == BEGIN_RDA) - { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); - // Load data: - if (storeMode == StorageMode::Store) // use StorageMode - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - else if (storeMode == StorageMode::ErrorModel) // use StorageMode with errormodel - { - ememory[bank]->load(payload); - } - } - else if (phase == BEGIN_REFA) - { - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - - if (storeMode == StorageMode::ErrorModel) + else if (phase == BEGIN_REFA) ememory[bank]->refresh(DramExtension::getExtension(payload).getRow().ID()); } - else if (phase == BEGIN_REFB) - DRAMPower->doCommand(MemCommand::REFB, bank, cycle); - else if (phase == BEGIN_PDNA) - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); - else if (phase == END_PDNA) - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); - else if (phase == BEGIN_PDNP) - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); - else if (phase == END_PDNP) - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); - else if (phase == BEGIN_SREF) - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); - else if (phase == END_SREF) - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); - else - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); return TLM_ACCEPTED; } diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp index 127bee12..8d2ac226 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp @@ -45,13 +45,6 @@ DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name) if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2"); - // Parameters for DRAMPower - MemSpecWideIO2 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramWideIO2", "Wrong MemSpec chosen"); - if (Configuration::getInstance().powerAnalysis) - SC_REPORT_FATAL("DramWideIO2", "DRAMPower not supported for WideIO2"); - else - DRAMPower = new libDRAMPowerDummy(); + SC_REPORT_FATAL("DramWideIO2", "DRAMPower does not support WideIO2"); }