From 6a8ce57d088c74312e5bf85fd605c1466904ca48 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 2 Oct 2020 16:12:14 +0200 Subject: [PATCH] Add selection of fine granularity refresh mode. --- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json | 15 ++++++++++----- .../memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json | 15 ++++++++++----- .../resources/simulations/ddr5-example.json | 4 ++-- .../src/configuration/memspec/MemSpecDDR5.cpp | 17 +++++++++++++---- .../src/configuration/memspec/MemSpecDDR5.h | 1 + .../refresh/RefreshManagerGroupwise.cpp | 6 ++++-- 15 files changed, 130 insertions(+), 63 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json index 3febbed0..8bc5a428 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 16, "WTR_S": 4, - "RFC_slr": 312, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 312, + "RFC2_slr": 208, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 184, "RFCsb_dlr": 0, - "REFI": 6240, + "REFI1": 6240, + "REFI2": 3120, "REFISB": 1560, "REFSBRD_slr": 48, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json index 90e37faf..639c16a9 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 18, "WTR_S": 5, - "RFC_slr": 351, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 351, + "RFC2_slr": 234, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 207, "RFCsb_dlr": 0, - "REFI": 7020, + "REFI1": 7020, + "REFI2": 3510, "REFISB": 1755, "REFSBRD_slr": 54, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json index 687e6295..98d6a123 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 20, "WTR_S": 5, - "RFC_slr": 390, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 390, + "RFC2_slr": 260, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 230, "RFCsb_dlr": 0, - "REFI": 7800, + "REFI1": 7800, + "REFI2": 3900, "REFISB": 1950, "REFSBRD_slr": 60, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json index 19c05cbf..1455cecb 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 22, "WTR_S": 6, - "RFC_slr": 429, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC_slr": 429, + "RFC_slr": 286, + "RFC_dlr": 0, + "RFC_dlr": 0, + "RFC_dpr": 0, + "RFC_dpr": 0, "RFCsb_slr": 253, "RFCsb_dlr": 0, - "REFI": 8580, + "REFI1": 8580, + "REFI2": 4290, "REFISB": 2145, "REFSBRD_slr": 66, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json index 56d7a6b3..5fef3321 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 24, "WTR_S": 6, - "RFC_slr": 468, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 468, + "RFC2_slr": 312, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 276, "RFCsb_dlr": 0, - "REFI": 9360, + "REFI1": 9360, + "REFI2": 4680, "REFISB": 2340, "REFSBRD_slr": 72, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json index 40fe0283..358643b8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 26, "WTR_S": 7, - "RFC_slr": 507, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 507, + "RFC2_slr": 338, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 299, "RFCsb_dlr": 0, - "REFI": 10140, + "REFI1": 10140, + "REFI2": 5070, "REFISB": 2535, "REFSBRD_slr": 78, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json index 5ed3f965..766c837c 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 28, "WTR_S": 7, - "RFC_slr": 546, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 546, + "RFC2_slr": 364, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 322, "RFCsb_dlr": 0, - "REFI": 10920, + "REFI1": 10920, + "REFI2": 5460, "REFISB": 2730, "REFSBRD_slr": 84, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json index 878a99ec..9e387dc4 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 30, "WTR_S": 8, - "RFC_slr": 585, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 585, + "RFC2_slr": 390, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 345, "RFCsb_dlr": 0, - "REFI": 11700, + "REFI1": 11700, + "REFI2": 5850, "REFISB": 2925, "REFSBRD_slr": 90, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json index 6f291b49..18caa618 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json @@ -14,7 +14,8 @@ "width": 8, "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 0, "WTR_L": 32, "WTR_S": 8, - "RFC_slr": 624, - "RFC_dlr": 0, - "RFC_dpr": 0, + "RFC1_slr": 624, + "RFC2_slr": 416, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, "RFCsb_slr": 368, "RFCsb_dlr": 0, - "REFI": 12480, + "REFI1": 12480, + "REFI2": 6240, "REFISB": 3120, "REFSBRD_slr": 96, "REFSBRD_dlr": 0, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json index 3de8ce00..d4d61219 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json @@ -14,7 +14,8 @@ "width": 4, "nbrOfDevicesOnDIMM": 8, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 16, "WTR_L": 16, "WTR_S": 4, - "RFC_slr": 312, - "RFC_dlr": 104, - "RFC_dpr": 104, + "RFC1_slr": 312, + "RFC2_slr": 208, + "RFC1_dlr": 104, + "RFC2_dlr": 70, + "RFC1_dpr": 104, + "RFC2_dpr": 70, "RFCsb_slr": 184, "RFCsb_dlr": 62, - "REFI": 6240, + "REFI1": 6240, + "REFI2": 3120, "REFISB": 1560, "REFSBRD_slr": 48, "REFSBRD_dlr": 24, diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json index 95886d86..315fb976 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json @@ -14,7 +14,8 @@ "width": 4, "nbrOfDevicesOnDIMM": 8, "nbrOfChannels": 2, - "cmdMode": 1 + "cmdMode": 1, + "refMode": 1 }, "memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit", "memoryType": "DDR5", @@ -46,12 +47,16 @@ "FAW_dlr": 16, "WTR_L": 16, "WTR_S": 4, - "RFC_slr": 312, - "RFC_dlr": 104, - "RFC_dpr": 104, + "RFC1_slr": 312, + "RFC2_slr": 208, + "RFC1_dlr": 104, + "RFC2_dlr": 70, + "RFC1_dpr": 104, + "RFC2_dpr": 70, "RFCsb_slr": 184, "RFCsb_dlr": 62, - "REFI": 6240, + "REFI1": 6240, + "REFI2": 3120, "REFISB": 1560, "REFSBRD_slr": 48, "REFSBRD_dlr": 24, diff --git a/DRAMSys/library/resources/simulations/ddr5-example.json b/DRAMSys/library/resources/simulations/ddr5-example.json index e85d1b92..8b66eaa6 100644 --- a/DRAMSys/library/resources/simulations/ddr5-example.json +++ b/DRAMSys/library/resources/simulations/ddr5-example.json @@ -1,8 +1,8 @@ { "simulation": { - "addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json", + "addressmapping": "am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json", "mcconfig": "fr_fcfs.json", - "memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json", + "memspec": "JEDEC_2x4x1Gbx8_DDR5-3200A.json", "simconfig": "ddr5.json", "simulationid": "ddr5-example", "thermalconfig": "config.json", diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 19b5e65f..9a4892cf 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -58,6 +58,7 @@ MemSpecDDR5::MemSpecDDR5(json &memspec) logicalRanksPerPhysicalRank(parseUint(memspec["memarchitecturespec"]["nbrOfLogicalRanks"], "nbrOfLogicalRanks")), numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks), cmdMode(parseUint(memspec["memarchitecturespec"]["cmdMode"], "cmdMode")), + refMode(parseUint(memspec["memarchitecturespec"]["refMode"], "refMode")), tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), @@ -86,12 +87,16 @@ MemSpecDDR5::MemSpecDDR5(json &memspec) tFAW_dlr (tCK * parseUint(memspec["memtimingspec"]["FAW_dlr"], "FAW_dlr")), tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")), tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), - tRFC_slr (tCK * parseUint(memspec["memtimingspec"]["RFC_slr"], "RFC_slr")), - tRFC_dlr (tCK * parseUint(memspec["memtimingspec"]["RFC_dlr"], "RFC_dlr")), - tRFC_dpr (tCK * parseUint(memspec["memtimingspec"]["RFC_dpr"], "RFC_dpr")), + tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_slr"], "RFC1_slr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_slr"], "RFC2_slr")), + tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dlr"], "RFC1_dlr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_dlr"], "RFC2_dlr")), + tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dpr"], "RFC1_dpr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_dpr"], "RFC2_dpr")), tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_slr"], "RFCsb_slr")), tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_dlr"], "RFCsb_dlr")), - tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), + tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["REFI1"], "REFI1") + : tCK * parseUint(memspec["memtimingspec"]["REFI2"], "REFI2")), tREFIsb (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")), tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_slr"], "REFSBRD_slr")), tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_dlr"], "REFSBRD_dlr")), @@ -134,6 +139,10 @@ MemSpecDDR5::MemSpecDDR5(json &memspec) } else SC_REPORT_FATAL("MemSpecDDR5", "Invalid command mode!"); + + if (!(refMode == 1 || refMode == 2)) + SC_REPORT_FATAL("MemSpecDDR5", "Invalid refresh mode! " + "Set 1 for normal or 2 for fine granularity refresh mode."); } sc_time MemSpecDDR5::getRefreshIntervalAB() const diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index e6549d26..187fe07d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -50,6 +50,7 @@ public: const unsigned logicalRanksPerPhysicalRank; const unsigned numberOfLogicalRanks; const unsigned cmdMode; + const unsigned refMode; // Memspec Variables: const sc_time tRCD; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerGroupwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerGroupwise.cpp index 9cc326c4..305f9493 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerGroupwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerGroupwise.cpp @@ -66,8 +66,8 @@ RefreshManagerGroupwise::RefreshManagerGroupwise(std::vector &ban remainingBankMachines = allBankMachines; currentIterator = remainingBankMachines.begin(); - maxPostponed = config.refreshMaxPostponed * memSpec->banksPerGroup; - maxPulledin = -(config.refreshMaxPulledin * memSpec->banksPerGroup); + maxPostponed = static_cast(config.refreshMaxPostponed * memSpec->banksPerGroup); + maxPulledin = -static_cast(config.refreshMaxPulledin * memSpec->banksPerGroup); } std::tuple RefreshManagerGroupwise::getNextCommand() @@ -242,5 +242,7 @@ void RefreshManagerGroupwise::updateState(Command command) case Command::PDXA: case Command::PDXP: sleeping = false; break; + default: + break; } }