Implement tCCDR for HBM2 and fix bug with SID

2025-02-21 14:14:21 +01:00
parent 5ab5a70d65
commit 6861576550
9 changed files with 82 additions and 3 deletions
--- a/configs/addressmapping/am_hbm2_8Gb_pc_brc.json
+++ b/configs/addressmapping/am_hbm2_8Gb_pc_brc.json
@@ -1,5 +1,8 @@
 {
    "addressmapping": {
+        "STACK_BIT":[
+            30
+        ],
        "PSEUDOCHANNEL_BIT":[
            29
        ],
--- a/configs/memspec/HBM2.json
+++ b/configs/memspec/HBM2.json
@@ -6,6 +6,7 @@
            "nbrOfBankGroups": 4,
            "nbrOfBanks": 16,
            "nbrOfColumns": 128,
+            "nbrOfStacks": 2,
            "nbrOfPseudoChannels": 2,
            "nbrOfRows": 32768,
            "width": 64,
@@ -17,6 +18,7 @@
        "memtimingspec": {
            "CCDL": 3,
            "CCDS": 2,
+            "CCDR": 2,
            "CKE": 8,
            "DQSCK": 1,
            "FAW": 16,