diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index e7f47677..bdb70e99 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -19,37 +19,90 @@ #include "../common/protocol.h" #include "../common/Utils.h" #include "../common/TlmRecorder.h" -//#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -//#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" -//#include "../common/third_party/DRAMPower/src/MemorySpecification.h" -//#include "../common/third_party/DRAMPower/src/MemCommand.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" +#include "../common/third_party/DRAMPower/src/MemorySpecification.h" +#include "../common/third_party/DRAMPower/src/MemCommand.h" using namespace std; using namespace tlm; using namespace core; -//using namespace Data; +using namespace Data; + + +#define POWER + +#ifdef POWER + #define IFPOW(x) x +#else + #define IFPOW(x) +#endif + + +class column +{ + private: + + unsigned char * data; + unsigned int bytes; + + public: + + column() + { + bytes = 0; + data = NULL; + } + + column(int bytes) + { + bytes = bytes; + data = new unsigned char[bytes]; + } + + ~column() + { + //delete data; + } + + void set(unsigned char * payloadDataPtr) + { + printf("Dest: %p Source: %p\n",data,payloadDataPtr); + cout << "mem" ; + memcpy(data, payloadDataPtr, bytes); // XXX hier knallts + cout << "copy" << endl; + } + + void get(unsigned char * payloadDataPtr) + { + memcpy(payloadDataPtr, data, bytes); + } +}; template struct Dram: sc_module { tlm_utils::simple_target_socket tSocket; - //libDRAMPower *DRAMPower; + IFPOW(libDRAMPower *DRAMPower); + + map< unsigned long int, column * > memory; SC_CTOR(Dram) : tSocket("socket") { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - //MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - //DRAMPower = new libDRAMPower( memSpec, 0 ); + IFPOW( MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)) ); + IFPOW( DRAMPower = new libDRAMPower( memSpec, 0 ) ); } ~Dram() { -// DRAMPower->updateCounters(true); -// DRAMPower->getEnergy(); -// cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl; -// cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl; + IFPOW( DRAMPower->updateCounters(true)); + IFPOW( DRAMPower->getEnergy() ); + IFPOW( cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl); + IFPOW( cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl ); + std::cout << "Simulated Memory Size: " << memory.size() << endl; } virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay) @@ -62,103 +115,119 @@ struct Dram: sc_module if (phase == BEGIN_PRE) { - //DRAMPower->doCommand(MemCommand::PRE, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PRE, bank, cycle)); sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { - //DRAMPower->doCommand(MemCommand::PREA, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PREA, bank, cycle)); sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACT) { - //DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::ACT, bank, cycle)); sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); } else if (phase == BEGIN_WR) { - //DRAMPower->doCommand(MemCommand::WR, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle)); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); + + // Save: + column * c = new column(16); + c->set(payload.get_data_ptr()); // <-- hier drin knallts + memory[payload.get_address()] = c; } else if (phase == BEGIN_RD) { - //DRAMPower->doCommand(MemCommand::RD, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle)); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); + + // Load: + //if(memory.count(payload.get_address()) == 1) + //{ + // column * c = memory[payload.get_address()]; + // c->get(payload.get_data_ptr()); + //} + //else + //{ + // SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location"); + //} } else if (phase == BEGIN_WRA) { - //DRAMPower->doCommand(MemCommand::WRA, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::WRA, bank, cycle)); sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) { - //DRAMPower->doCommand(MemCommand::RDA, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::RDA, bank, cycle)); sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_REFA) { - //DRAMPower->doCommand(MemCommand::REF, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::REF, bank, cycle)); sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload)); } else if (phase == BEGIN_REFB) { - //DRAMPower->doCommand(MemCommand::REF, bank, cycle); + IFPOW( SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported") ); sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload)); } //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) { - //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle)); } else if (phase == END_PDNA) { - //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle)); } else if (phase == BEGIN_PDNAB) { - //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == END_PDNAB) { - //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == BEGIN_PDNP) { - //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle)); } else if (phase == END_PDNP) { - //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle)); } else if (phase == BEGIN_PDNPB) { - //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == END_PDNPB) { - //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == BEGIN_SREF) { - //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::SREN, bank, cycle)); } else if (phase == END_SREF) { - //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::SREX, bank, cycle)); } else if (phase == BEGIN_SREFB) { - //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == END_SREFB) { - //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else { - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); + IFPOW(SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase")); } return tlm::TLM_ACCEPTED; } diff --git a/dram/src/simulation/TracePlayer.h b/dram/src/simulation/TracePlayer.h index 42b589da..5581ed6c 100644 --- a/dram/src/simulation/TracePlayer.h +++ b/dram/src/simulation/TracePlayer.h @@ -87,11 +87,11 @@ void TracePlayer::generateNextPayload() { if (file) { - string time, command, address; + string time, command, address, data; file >> time >> command >> address; //if there is a newline at the end of the .stl - if (time.empty() || command.empty() || address.empty()) + if (time.empty() || command.empty() || address.empty() ) return; long parsedAdress = std::stoi(address.c_str(), 0, 16); @@ -99,6 +99,13 @@ void TracePlayer::generateNextPayload() gp* payload = memoryManager.allocate(); payload->set_address(parsedAdress); + // Set data pointer + unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite + payload->set_data_length(16); // TODO: column / burst breite + payload->set_data_ptr(dataElement); + for(int i = 0; i < 16; i++) // TODO: column / burst breite + dataElement[i] = 0; + if (command == "read") { payload->set_command(TLM_READ_COMMAND); @@ -106,6 +113,17 @@ void TracePlayer::generateNextPayload() else if (command == "write") { payload->set_command(TLM_WRITE_COMMAND); + + // Parse and set data + file >> data; + unsigned int counter = 0; + for(int i = 0; i < 16*2-2; i=i+2) // TODO column / burst breite + { + std::string byteString = "0x"; + byteString.append(data.substr(i+2, 2)); + //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; + dataElement[counter++] = std::stoi(byteString.c_str(), 0, 16); + } } else { @@ -113,7 +131,6 @@ void TracePlayer::generateNextPayload() (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str()); } - payload->set_data_length(BUSWIDTH / 8); payload->set_response_status(TLM_INCOMPLETE_RESPONSE); payload->set_dmi_allowed(false); payload->set_byte_enable_length(0);