diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index cec4544e..d656f3a0 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -3,10 +3,11 @@ CONFIG += console CONFIG -= app_bundle CONFIG -= qt -system(cd ../src/common/third_party/DRAMPower; make parserlib; make lib;) +system(cd ../src/common/third_party/DRAMPower; make lib;) LIBS += -L/opt/systemc/lib-linux64 -lsystemc LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system +LIBS += -lsqlite3 LIBS += -lpthread LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower @@ -15,18 +16,14 @@ INCLUDEPATH += /opt/boost/include INCLUDEPATH += ../src/common/third_party/DRAMPower/src INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower + DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES -DEFINES += USE_XERCES=1 release { DEFINES += NDEBUG } - QMAKE_CXXFLAGS += -std=c++11 -QMAKE_CXXFLAGS += -isystem /opt/systemc/include -QMAKE_CXXFLAGS += -isystem /opt/boost/include -QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/ SOURCES += \ ../src/common/third_party/tinyxml2/tinyxml2.cpp \ diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index f28d961a..43e20eed 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -1,29 +1,3 @@ - - @@ -37,12 +11,12 @@ - + - voco2.stl + chstone-adpcm_32.stl diff --git a/dram/src/controller/core/configuration/Configuration.h b/dram/src/controller/core/configuration/Configuration.h index 7023dfed..7cdab17c 100644 --- a/dram/src/controller/core/configuration/Configuration.h +++ b/dram/src/controller/core/configuration/Configuration.h @@ -89,5 +89,4 @@ private: unsigned int powerDownTimeoutInClk = 3; }; - #endif /* CONFIGURATION_H_ */ diff --git a/dram/src/controller/core/configuration/ConfigurationLoader.cpp b/dram/src/controller/core/configuration/ConfigurationLoader.cpp index 9a394ee4..a69063fb 100644 --- a/dram/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/dram/src/controller/core/configuration/ConfigurationLoader.cpp @@ -143,6 +143,8 @@ void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.DLL = true; + config.memSpec.termination = true; //MemTimings XMLElement* timings = memspec->FirstChildElement("memtimingspec"); @@ -173,12 +175,31 @@ void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.memSpec.tAL = clk * queryUIntParameter(timings, "AL"); config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC"); config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI"); + config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); config.memSpec.refreshTimings.clear(); for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) { config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, config.memSpec.tREFI); } + + // Currents and Volatages: + XMLElement* powers = memspec->FirstChildElement("mempowerspec"); + config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02"); + config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62"); + config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2"); } void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec) @@ -195,6 +216,8 @@ void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec) config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.DLL = false; + config.memSpec.termination = false; //MemTimings XMLElement* timings = memspec->FirstChildElement("memtimingspec"); @@ -233,5 +256,31 @@ void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec) config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, config.memSpec.tREFI); } + // Currents and Volatages: + XMLElement* powers = memspec->FirstChildElement("mempowerspec"); + config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec.iDD02 = queryDoubleParameter(powers, "idd02"); + config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + config.memSpec.iDD2P02 = queryDoubleParameter(powers, "idd2p02"); + config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + config.memSpec.iDD2P12 = queryDoubleParameter(powers, "idd2p12"); + config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec.iDD2N2 = queryDoubleParameter(powers, "idd2n2"); + config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + config.memSpec.iDD3P02 = queryDoubleParameter(powers, "idd3p02"); + config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + config.memSpec.iDD3P12 = queryDoubleParameter(powers, "idd3p12"); + config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec.iDD3N2 = queryDoubleParameter(powers, "idd3n2"); + config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec.iDD4R2 = queryDoubleParameter(powers, "idd4r2"); + config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec.iDD4W2 = queryDoubleParameter(powers, "idd4w2"); + config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec.iDD52 = queryDoubleParameter(powers, "idd52"); + config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec.iDD62 = queryDoubleParameter(powers, "idd62"); + config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd2"); } diff --git a/dram/src/controller/core/configuration/MemSpec.h b/dram/src/controller/core/configuration/MemSpec.h index 47c7700d..95b41ed1 100644 --- a/dram/src/controller/core/configuration/MemSpec.h +++ b/dram/src/controller/core/configuration/MemSpec.h @@ -83,7 +83,10 @@ struct MemSpec unsigned int NumberOfRows; unsigned int NumberOfColumns; unsigned int BusWidth; + bool DLL; + bool termination; + // Memspec Variables: sc_time clk; sc_time tRP; //precharge-time (pre -> act same bank) sc_time tRAS; //active-time (act -> pre same bank) @@ -107,10 +110,38 @@ struct MemSpec sc_time tXSR; //min delay to row access command after srefx sc_time tXSRDLL; //min delay to row access command after srefx for dll commands sc_time tAL; //additive delay (delayed execution in dram) + sc_time tDQSCK; sc_time tRFC; //min ref->act delay sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI + // Currents and Voltages: + double iDD0; + double iDD02; + double iDD2P0; + double iDD2P02; + double iDD2P1; + double iDD2P12; + double iDD2N; + double iDD2N2; + double iDD3P0; + double iDD3P02; + double iDD3P1; + double iDD3P12; + double iDD3N; + double iDD3N2; + double iDD4R; + double iDD4R2; + double iDD4W; + double iDD4W2; + double iDD5; + double iDD52; + double iDD6; + double iDD62; + double vDD; + double vDD2; + + std::map refreshTimings;//ensure that map is populated completely in memspecloader //act and read/write commands remain for this timespan in history diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 4ea9f459..87fdd72c 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -49,22 +49,12 @@ #include "../common/Utils.h" #include "../common/TlmRecorder.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" - #include "../error/flip_memory.h" - using namespace std; using namespace tlm; using namespace Data; - -//#define POWER -//not better to define in simulation xml? also flag for storage simulation -//configuration->PowerAnalysis -//configuration->ModelStorage -//configuration->ModelErrotInjection - template struct Dram: sc_module @@ -90,9 +80,87 @@ struct Dram: sc_module if(powerAnalysis == true) { - MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); + sc_time clk = Configuration::getInstance().memSpec.clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = Configuration::getInstance().memSpec.BurstLength; + memArchSpec.dataRate = Configuration::getInstance().memSpec.DataRate; + memArchSpec.nbrOfRows = Configuration::getInstance().memSpec.NumberOfRows; + memArchSpec.nbrOfBanks = Configuration::getInstance().memSpec.NumberOfBanks; + memArchSpec.nbrOfColumns = Configuration::getInstance().memSpec.NumberOfColumns; + memArchSpec.nbrOfRanks = Configuration::getInstance().memSpec.NumberOfRanks; + memArchSpec.width = Configuration::getInstance().memSpec.BusWidth; + memArchSpec.nbrOfBankGroups = Configuration::getInstance().memSpec.NumberOfBankGroups; + memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 ? false : true); + memArchSpec.dll = Configuration::getInstance().memSpec.DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.AL = Configuration::getInstance().memSpec.tAL/clk; + memTimingSpec.CCD = Configuration::getInstance().memSpec.tCCD_S/clk; + memTimingSpec.CCD_L = Configuration::getInstance().memSpec.tCCD_L/clk; + memTimingSpec.CCD_S = Configuration::getInstance().memSpec.tCCD_S/clk; + memTimingSpec.CKE = Configuration::getInstance().memSpec.tCKE/clk; + memTimingSpec.CKESR = Configuration::getInstance().memSpec.tCKESR/clk; + memTimingSpec.clkMhz = int(1 / (clk.value() / 1000000.0)); + memTimingSpec.clkPeriod = clk.value() / 1000.0; + memTimingSpec.DQSCK = Configuration::getInstance().memSpec.tDQSCK/clk; + memTimingSpec.FAW = Configuration::getInstance().memSpec.tNAW/clk; + memTimingSpec.RAS = Configuration::getInstance().memSpec.tRAS/clk; + memTimingSpec.RC = Configuration::getInstance().memSpec.tRC/clk; + memTimingSpec.RCD = Configuration::getInstance().memSpec.tRCD/clk; + memTimingSpec.REFI = Configuration::getInstance().memSpec.tREFI/clk; + memTimingSpec.RFC = Configuration::getInstance().memSpec.tRFC/clk; + memTimingSpec.RL = Configuration::getInstance().memSpec.tRL/clk; + memTimingSpec.RP = Configuration::getInstance().memSpec.tRP/clk; + memTimingSpec.RRD = Configuration::getInstance().memSpec.tRRD_S/clk; + memTimingSpec.RRD_L = Configuration::getInstance().memSpec.tRRD_L/clk; + memTimingSpec.RRD_S = Configuration::getInstance().memSpec.tRRD_S/clk; + memTimingSpec.RTP = Configuration::getInstance().memSpec.tRTP/clk; + memTimingSpec.TAW = Configuration::getInstance().memSpec.tNAW/clk; + memTimingSpec.WL = Configuration::getInstance().memSpec.tWL/clk; + memTimingSpec.WR = Configuration::getInstance().memSpec.tWR/clk; + memTimingSpec.WTR = Configuration::getInstance().memSpec.tWTR_S/clk; + memTimingSpec.WTR_L = Configuration::getInstance().memSpec.tWTR_L/clk; + memTimingSpec.WTR_S = Configuration::getInstance().memSpec.tWTR_S/clk; + memTimingSpec.XP = Configuration::getInstance().memSpec.tXP/clk; + memTimingSpec.XPDLL = Configuration::getInstance().memSpec.tXPDLL/clk; + memTimingSpec.XS = Configuration::getInstance().memSpec.tXSR/clk; + memTimingSpec.XSDLL = Configuration::getInstance().memSpec.tXSRDLL/clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = Configuration::getInstance().memSpec.iDD0; + memPowerSpec.idd02 = Configuration::getInstance().memSpec.iDD02; + memPowerSpec.idd2p0 = Configuration::getInstance().memSpec.iDD2P0; + memPowerSpec.idd2p02 = Configuration::getInstance().memSpec.iDD2P02; + memPowerSpec.idd2p1 = Configuration::getInstance().memSpec.iDD2P1; + memPowerSpec.idd2p12 = Configuration::getInstance().memSpec.iDD2P12; + memPowerSpec.idd2n = Configuration::getInstance().memSpec.iDD2N; + memPowerSpec.idd2n2 = Configuration::getInstance().memSpec.iDD2N2; + memPowerSpec.idd3p0 = Configuration::getInstance().memSpec.iDD3P0; + memPowerSpec.idd3p02 = Configuration::getInstance().memSpec.iDD3P02; + memPowerSpec.idd3p1 = Configuration::getInstance().memSpec.iDD3P1; + memPowerSpec.idd3p12 = Configuration::getInstance().memSpec.iDD3P12; + memPowerSpec.idd3n = Configuration::getInstance().memSpec.iDD3N; + memPowerSpec.idd3n2 = Configuration::getInstance().memSpec.iDD3N2; + memPowerSpec.idd4r = Configuration::getInstance().memSpec.iDD4R; + memPowerSpec.idd4r2 = Configuration::getInstance().memSpec.iDD4R2; + memPowerSpec.idd4w = Configuration::getInstance().memSpec.iDD4W; + memPowerSpec.idd4w2 = Configuration::getInstance().memSpec.iDD4W2; + memPowerSpec.idd5 = Configuration::getInstance().memSpec.iDD5; + memPowerSpec.idd52 = Configuration::getInstance().memSpec.iDD52; + memPowerSpec.idd6 = Configuration::getInstance().memSpec.iDD6; + memPowerSpec.idd62 = Configuration::getInstance().memSpec.iDD62; + memPowerSpec.vdd = Configuration::getInstance().memSpec.vDD; + memPowerSpec.vdd2 = Configuration::getInstance().memSpec.vDD2; + + MemorySpecification memSpec; + memSpec.memTimingSpec = memTimingSpec; + memSpec.memPowerSpec = memPowerSpec; + memSpec.memArchSpec = memArchSpec; + DRAMPower = new libDRAMPower( memSpec, 0 ); } + cout << "ErrorStorageMode: " << EnumToString(ErrorStoreMode) << endl; if(ErrorStoreMode == ErrorStorageMode::ErrorModel)