diff --git a/DRAMSys/simulator/src/controller/Controller.cpp b/DRAMSys/simulator/src/controller/Controller.cpp
index 8e307173..bf68d7d4 100644
--- a/DRAMSys/simulator/src/controller/Controller.cpp
+++ b/DRAMSys/simulator/src/controller/Controller.cpp
@@ -300,6 +300,11 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, const tlm_pha
         scheduler->schedule(&payload);
         scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank());
     }
+    else if (phase == PendingRequest)
+    {
+      // Schedule a pending request.
+      scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank());
+    }
     else if (phase == END_RESP)
     {
         if (backpressure != NULL)
@@ -365,6 +370,7 @@ void Controller::scheduleNextFromScheduler(Bank bank)
         return;
     }
 
+    bool rescheduled = true;
     pair<Command, tlm::tlm_generic_payload*> nextRequest = scheduler->getNextRequest(bank);
     if(nextRequest.second != NULL)
     {
@@ -372,7 +378,17 @@ void Controller::scheduleNextFromScheduler(Bank bank)
         controllerCore->scheduleRequest(nextRequest.first, *nextRequest.second);
         printDebugMessage("\t-> Next payload was scheduled by core [" + commandToString(nextRequest.first) + "]");
     }
+    else
+    {
+      gp* pendingRequest = scheduler->getPendingRequest(bank);
+      if (pendingRequest != NULL)
+      {
+        rescheduled = true;
+        frontendPEQ.notify(*(pendingRequest), PendingRequest, Configuration::getInstance().memSpec.clk);
+      }
+    }
 
+    queue<Bank> blocked;
     while (!blockedRequests.empty()) {
         bank = blockedRequests.front();
         blockedRequests.pop();
@@ -383,7 +399,23 @@ void Controller::scheduleNextFromScheduler(Bank bank)
             controllerCore->scheduleRequest(nextRequest.first, *nextRequest.second);
             printDebugMessage("\t-> Next payload was scheduled by core [" + commandToString(nextRequest.first) + "] (unblocked)");
         }
+        else
+        {
+            gp* pendingRequest = scheduler->getPendingRequest(bank);
+            if(pendingRequest != NULL)
+            {
+                //Pending request
+                if(!rescheduled)
+                {
+                    rescheduled = true;
+                    frontendPEQ.notify(*(pendingRequest), PendingRequest, Configuration::getInstance().memSpec.clk);
+                }
+                else
+                    blocked.push(bank);
+            }
+        }
     }
+    blockedRequests = blocked;
 }
 
 void Controller::sendToFrontend(tlm_generic_payload &payload, const tlm_phase &phase, const sc_time &delay)
diff --git a/DRAMSys/simulator/src/controller/Controller.h b/DRAMSys/simulator/src/controller/Controller.h
index 682a29b0..b5f67ff7 100644
--- a/DRAMSys/simulator/src/controller/Controller.h
+++ b/DRAMSys/simulator/src/controller/Controller.h
@@ -73,6 +73,8 @@
 using namespace std;
 using namespace tlm;
 
+DECLARE_EXTENDED_PHASE(PendingRequest);
+
 struct Controller: public sc_module, public IController
 {
 public:
diff --git a/DRAMSys/simulator/src/controller/scheduler/Fifo.cpp b/DRAMSys/simulator/src/controller/scheduler/Fifo.cpp
index beb57612..7d7a90e1 100644
--- a/DRAMSys/simulator/src/controller/scheduler/Fifo.cpp
+++ b/DRAMSys/simulator/src/controller/scheduler/Fifo.cpp
@@ -60,4 +60,9 @@ pair<Command, tlm::tlm_generic_payload*> Fifo::getNextRequest(Bank bank)
     return pair<Command, tlm::tlm_generic_payload*>(Command::NOP, NULL);
 }
 
+gp* Fifo::getPendingRequest(Bank bank)
+{
+  return NULL;
+}
+
 
diff --git a/DRAMSys/simulator/src/controller/scheduler/Fifo.h b/DRAMSys/simulator/src/controller/scheduler/Fifo.h
index 0576bb32..1b060b12 100644
--- a/DRAMSys/simulator/src/controller/scheduler/Fifo.h
+++ b/DRAMSys/simulator/src/controller/scheduler/Fifo.h
@@ -52,6 +52,7 @@ public:
 
     void schedule(gp* payload) override;
     std::pair<Command, tlm::tlm_generic_payload*> getNextRequest(Bank bank) override;
+    virtual gp* getPendingRequest(Bank bank) override;
 
 private:
     std::map<Bank, std::deque<gp*>> buffer;
diff --git a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp
index f9881fee..6e8bd292 100644
--- a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp
+++ b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp
@@ -128,3 +128,7 @@ std::pair<Command, tlm::tlm_generic_payload *> FifoStrict::getNextRequest(Bank b
     return pair<Command, tlm::tlm_generic_payload*>(Command::NOP, NULL);
 }
 
+gp* FifoStrict::getPendingRequest(Bank bank)
+{
+  return NULL;
+}
diff --git a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h
index 1cc9ece0..855f7ff3 100644
--- a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h
+++ b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h
@@ -56,6 +56,7 @@ public:
 
     void schedule(gp* payload) override;
     std::pair<Command, tlm::tlm_generic_payload*> getNextRequest(Bank bank) override;
+    virtual gp* getPendingRequest(Bank bank) override;
 
 private:
     std::deque<std::pair<Bank, tlm::tlm_generic_payload *>> buffer;
diff --git a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.cpp b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.cpp
index 30750c7f..5b022ca6 100644
--- a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.cpp
+++ b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.cpp
@@ -121,3 +121,8 @@ deque<gp*>::iterator FR_FCFS::FindRowHit(Bank bank)
 
     return queue.end();
 }
+
+gp* FR_FCFS::getPendingRequest(Bank bank)
+{
+  return NULL;
+}
diff --git a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.h b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.h
index 187b81ab..9347c21f 100644
--- a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.h
+++ b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs.h
@@ -53,6 +53,7 @@ public:
 
     void schedule(gp* payload) override;
     std::pair<Command, tlm::tlm_generic_payload*> getNextRequest(Bank bank) override;
+    virtual gp* getPendingRequest(Bank bank) override;
 
 private:
     std::map<Bank, std::deque<gp*>> buffer;
diff --git a/DRAMSys/simulator/src/controller/scheduler/IScheduler.h b/DRAMSys/simulator/src/controller/scheduler/IScheduler.h
index a951d015..efeebdc4 100644
--- a/DRAMSys/simulator/src/controller/scheduler/IScheduler.h
+++ b/DRAMSys/simulator/src/controller/scheduler/IScheduler.h
@@ -54,6 +54,7 @@ public:
 
     virtual void schedule(gp* payload) = 0;
     virtual std::pair<Command, gp*> getNextRequest(Bank bank) = 0;
+    virtual gp* getPendingRequest(Bank bank) = 0;
     static std::string sendername;
 
 protected:
diff --git a/DRAMSys/simulator/src/controller/scheduler/SMS.cpp b/DRAMSys/simulator/src/controller/scheduler/SMS.cpp
index 7b89d885..64882dc3 100644
--- a/DRAMSys/simulator/src/controller/scheduler/SMS.cpp
+++ b/DRAMSys/simulator/src/controller/scheduler/SMS.cpp
@@ -343,3 +343,15 @@ void SMS::multiBatchFormation(sc_time memClk)
     } while (formed);
   }
 }
+
+gp* SMS::getPendingRequest(Bank bank)
+{
+  for (auto& requestBuffer : requestBuffers) {
+    for (auto& request : requestBuffer.second) {
+      if (DramExtension::getBank(request) == bank) {
+        return request;
+      }
+    }
+  }
+  return NULL;
+}
diff --git a/DRAMSys/simulator/src/controller/scheduler/SMS.h b/DRAMSys/simulator/src/controller/scheduler/SMS.h
index 3d4282aa..2843b990 100644
--- a/DRAMSys/simulator/src/controller/scheduler/SMS.h
+++ b/DRAMSys/simulator/src/controller/scheduler/SMS.h
@@ -46,6 +46,7 @@ public:
 
     virtual void schedule(gp *payload) override;
     virtual std::pair<Command, gp*> getNextRequest(Bank bank) override;
+    virtual gp* getPendingRequest(Bank bank) override;
 
     void batchScheduler();