From 5d8d7c197ef02a606e189955363ce040a900179f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 11:30:55 +0200 Subject: [PATCH] Apply clang-tidy readability-* fixes --- .../DRAMSys/config/DRAMSysConfiguration.cpp | 3 +- src/libdramsys/DRAMSys/common/DebugManager.h | 1 - src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 2 +- .../DRAMSys/common/dramExtensions.cpp | 11 +--- src/libdramsys/DRAMSys/common/utils.cpp | 6 +- .../DRAMSys/configuration/Configuration.cpp | 24 ++++---- .../DRAMSys/configuration/Configuration.h | 1 - .../configuration/memspec/MemSpecDDR3.cpp | 40 +++++++------ .../configuration/memspec/MemSpecDDR4.cpp | 39 +++++++------ .../configuration/memspec/MemSpecGDDR5.cpp | 46 ++++++++------- .../configuration/memspec/MemSpecGDDR5X.cpp | 46 ++++++++------- .../configuration/memspec/MemSpecGDDR6.cpp | 46 ++++++++------- .../configuration/memspec/MemSpecHBM2.cpp | 36 ++++++------ .../configuration/memspec/MemSpecLPDDR4.cpp | 45 ++++++++------- .../configuration/memspec/MemSpecSTTMRAM.cpp | 36 ++++++------ .../configuration/memspec/MemSpecWideIO.cpp | 39 +++++++------ .../configuration/memspec/MemSpecWideIO2.cpp | 45 ++++++++------- .../DRAMSys/controller/BankMachine.cpp | 56 +++++++------------ .../DRAMSys/controller/Controller.cpp | 14 ++--- .../DRAMSys/controller/ControllerRecordable.h | 3 +- .../controller/cmdmux/CmdMuxOldest.cpp | 6 +- .../controller/cmdmux/CmdMuxStrict.cpp | 6 +- .../powerdown/PowerDownManagerStaggered.cpp | 2 +- .../refresh/RefreshManagerPer2Bank.cpp | 40 ++++++------- .../refresh/RefreshManagerPerBank.cpp | 36 ++++++------ .../refresh/RefreshManagerSameBank.cpp | 4 +- .../controller/scheduler/SchedulerFifo.cpp | 8 +-- .../controller/scheduler/SchedulerFrFcfs.cpp | 4 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 9 +-- .../scheduler/SchedulerGrpFrFcfs.cpp | 36 +++++------- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 29 ++++------ .../DRAMSys/simulation/AddressDecoder.cpp | 4 +- src/libdramsys/DRAMSys/simulation/Arbiter.h | 4 +- .../DRAMSys/simulation/ReorderBuffer.h | 5 +- .../DRAMSys/simulation/dram/Dram.cpp | 2 +- src/simulator/simulator/Cache.cpp | 31 ++++++---- src/simulator/simulator/Cache.h | 2 +- src/simulator/simulator/MemoryManager.cpp | 10 ++-- src/simulator/simulator/util.cpp | 16 +++--- 39 files changed, 392 insertions(+), 401 deletions(-) diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp index 8e90dec4..7909bf61 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp @@ -124,9 +124,8 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector if (file.is_open()) { json_t simulation = json_t::parse(file, parser_callback, true, true).at(Configuration::KEY); return simulation.get(); - } else { - throw std::runtime_error("Failed to open file " + std::string(path)); } + throw std::runtime_error("Failed to open file " + std::string(path)); } } // namespace DRAMSys::Config diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index 2d6c0d99..cee92445 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -65,7 +65,6 @@ public: DebugManager(const DebugManager&) = delete; DebugManager& operator=(const DebugManager&) = delete; -public: void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile); void printDebugMessage(const std::string &sender, const std::string &message); diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index 4f70fe59..b60c14ee 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -78,7 +78,7 @@ TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, c void TlmRecorder::finalize() { - if (db) + if (db != nullptr) closeConnection(); sqlite3_finalize(insertTransactionStatement); sqlite3_finalize(insertRangeStatement); diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.cpp b/src/libdramsys/DRAMSys/common/dramExtensions.cpp index 25b608a1..edbb1fb1 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.cpp +++ b/src/libdramsys/DRAMSys/common/dramExtensions.cpp @@ -403,10 +403,7 @@ void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm bool ChildExtension::isChildTrans(const tlm::tlm_generic_payload& trans) { - if (trans.get_extension() != nullptr) - return true; - else - return false; + return trans.get_extension() != nullptr; } tlm_extension_base* ParentExtension::clone() const @@ -451,10 +448,8 @@ bool ParentExtension::notifyChildTransCompletion() childTranses.clear(); return true; } - else - { - return false; - } + + return false; } bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans) diff --git a/src/libdramsys/DRAMSys/common/utils.cpp b/src/libdramsys/DRAMSys/common/utils.cpp index ab919c30..eb00e417 100644 --- a/src/libdramsys/DRAMSys/common/utils.cpp +++ b/src/libdramsys/DRAMSys/common/utils.cpp @@ -60,10 +60,10 @@ bool TimeInterval::intersects(const TimeInterval &other) const sc_time TimeInterval::getLength() const { - if (end > start) - return end - start; - else + if (start > end) return start - end; + + return end - start; } std::string getPhaseName(const tlm_phase &phase) diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.cpp b/src/libdramsys/DRAMSys/configuration/Configuration.cpp index 41ea3f69..061b0188 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.cpp +++ b/src/libdramsys/DRAMSys/configuration/Configuration.cpp @@ -71,21 +71,25 @@ enum sc_time_unit string2TimeUnit(const std::string &s) { if (s == "s") return SC_SEC; - else if (s == "ms") + + if (s == "ms") return SC_MS; - else if (s == "us") + + if (s == "us") return SC_US; - else if (s == "ns") + + if (s == "ns") return SC_NS; - else if (s == "ps") + + if (s == "ps") return SC_PS; - else if (s == "fs") + + if (s == "fs") return SC_FS; - else { - SC_REPORT_FATAL("Configuration", - ("Could not convert to enum sc_time_unit: " + s).c_str()); - throw; - } + + SC_REPORT_FATAL("Configuration", + ("Could not convert to enum sc_time_unit: " + s).c_str()); + throw; } void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index 017ef610..5cdfb938 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -59,7 +59,6 @@ public: Configuration(const Configuration&) = delete; Configuration& operator=(const Configuration &) = delete; -public: // MCConfig: enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open; enum class Scheduler {Fifo, FrFcfs, FrFcfsGrp, GrpFrFcfs, GrpFrFcfsWm} scheduler = Scheduler::FrFcfs; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 4e9150f4..2c28e968 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -131,37 +131,41 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 10d7a37d..8aff4dde 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -150,37 +150,40 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 9dd86741..c490252d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -130,44 +130,48 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD; - else - return tRCDWR; + + return tRCDWR; } - else if (command == Command::RD) + + if (command == Command::RD) return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 2ff265aa..b06fd83a 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -130,44 +130,48 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD; - else - return tRCDWR; + + return tRCDWR; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 818f251e..d2fb4307 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -143,44 +143,48 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD + tCK; - else - return tRCDWR + tCK; + + return tRCDWR + tCK; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab; - else if (command == Command::REFPB || command == Command::REFP2B) + + if (command == Command::REFPB || command == Command::REFP2B) return tRFCpb; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 79b8c801..6ab9994d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -131,38 +131,42 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD + tCK; - else - return tRCDWR + tCK; + + return tRCDWR + tCK; } - else if (command == Command::RD) + if (command == Command::RD) return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCSB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; else { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index a90e67de..35c3dd6f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -136,41 +136,46 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB) return tRPpb + tCK; - else if (command == Command::PREAB) + + if (command == Command::PREAB) return tRPab + tCK; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD + 3 * tCK; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration + 3 * tCK; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration + tRTP - 5 * tCK + tRPpb; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + 4 * tCK + burstDuration + tWR + tRPpb; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab + tCK; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCpb + tCK; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK}; - else - { - SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index 76ea4cbd..ef16b158 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -108,35 +108,37 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; } TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index a72f8d72..b22157ad 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -137,37 +137,40 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tAC + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration - tCK + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index b1a1a683..f610d8bf 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -121,41 +121,46 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl { if (command == Command::PREPB) return tRPpb; - else if (command == Command::PREAB) + + if (command == Command::PREAB) return tRPab; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration - 2 * tCK + tRTP + tRPpb; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tDQSS + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tCK + tWR + tRPpb; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCpb; - else - { - SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tDQSS, tWL + tDQSS + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 09b7ceec..3774430c 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -173,16 +173,13 @@ void BankMachineOpen::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -204,7 +201,6 @@ void BankMachineOpen::evaluate() else // row miss nextCommand = Command::PREPB; } - } } } @@ -219,16 +215,13 @@ void BankMachineClosed::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -245,7 +238,6 @@ void BankMachineClosed::evaluate() else nextCommand = Command::WRA; } - } } } @@ -260,16 +252,13 @@ void BankMachineOpenAdaptive::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -303,7 +292,6 @@ void BankMachineOpenAdaptive::evaluate() else // row miss nextCommand = Command::PREPB; } - } } } @@ -319,16 +307,13 @@ void BankMachineClosedAdaptive::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -361,7 +346,6 @@ void BankMachineClosedAdaptive::evaluate() else // row miss, can happen when RD/WR mode is switched nextCommand = Command::PREPB; } - } } } diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 9bd58985..b7a5af8c 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -291,7 +291,7 @@ void Controller::controllerMethod() readyCommands.emplace_back(commandTuple); // (4.3) Check for bank commands (PREPB, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachinesOnRank[rankID]) + for (auto *it : bankMachinesOnRank[rankID]) { commandTuple = it->getNextCommand(); if (std::get(commandTuple) != Command::NOP) @@ -320,7 +320,7 @@ void Controller::controllerMethod() if (command.isRankCommand()) { - for (auto it : bankMachinesOnRank[rank.ID()]) + for (auto *it : bankMachinesOnRank[rank.ID()]) it->update(command); } else if (command.isGroupCommand()) @@ -621,12 +621,10 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate() { return *new tlm_generic_payload(this); } - else - { - tlm_generic_payload* result = freePayloads.top(); - freePayloads.pop(); - return *result; - } + + tlm_generic_payload *result = freePayloads.top(); + freePayloads.pop(); + return *result; } void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans) diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 727cadb6..91fd3832 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -57,7 +57,8 @@ protected: tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; + void sendToFrontend(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; void controllerMethod() override; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index 89487f9d..cd508345 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -73,8 +73,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) return *result; - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } @@ -179,8 +178,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) return *result; - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index ec288a90..36e5200a 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -83,8 +83,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand nextPayloadID++; return *result; } - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } @@ -181,8 +180,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC if (std::get(*result).isCasCommand()) nextPayloadID++; return *result; - } - else + } return {Command::NOP, nullptr, scMaxTime}; } diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index e0bad06d..63bbc485 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -98,7 +98,7 @@ void PowerDownManagerStaggered::evaluate() else if (entryTriggered) { nextCommand = Command::PDEP; - for (auto it : bankMachinesOnRank) + for (auto *it : bankMachinesOnRank) { if (it->isActivated()) { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index a544c1f6..3ba3a454 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -127,18 +127,17 @@ void RefreshManagerPer2Bank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalP2B(); return; } - else + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) { - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto* it : *currentIterator) + if (it->isActivated()) { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } } // TODO: banks should already be blocked for precharge and selection should be skipped @@ -149,7 +148,6 @@ void RefreshManagerPer2Bank::evaluate() skipSelection = true; } return; - } } else // if (state == RmState::Pulledin) { @@ -181,21 +179,19 @@ void RefreshManagerPer2Bank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalP2B(); return; } - else + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) { - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto* it : *currentIterator) + if (it->isActivated()) { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } } return; - } } } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 5fb5bac9..3320bcac 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -108,23 +108,21 @@ void RefreshManagerPerBank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalPB(); return; } + + // TODO: bank should already be blocked for precharge and selection should be skipped + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; else { - // TODO: bank should already be blocked for precharge and selection should be skipped - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - { - nextCommand = Command::REFPB; + nextCommand = Command::REFPB; - if (forcedRefresh) - { - (*currentIterator)->block(); - skipSelection = true; - } + if (forcedRefresh) + { + (*currentIterator)->block(); + skipSelection = true; + } } return; - } } else // if (state == RmState::Pulledin) { @@ -146,15 +144,13 @@ void RefreshManagerPerBank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalPB(); return; } - else - { - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - nextCommand = Command::REFPB; - return; - } + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; + else + nextCommand = Command::REFPB; + + return; } } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 75ecb124..802103c0 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -216,7 +216,7 @@ void RefreshManagerSameBank::evaluate() currentIterator = bankIt; break; } - else if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT()) + if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT()) { imtCandidates.emplace_back(bankIt); } @@ -234,7 +234,7 @@ void RefreshManagerSameBank::evaluate() } return; } - else if (!imtCandidates.empty()) + if (!imtCandidates.empty()) { // search for IMT candidates and check if all banks idle bool allGroupsBusy = true; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 7744ccc4..10df01b8 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -77,8 +77,7 @@ tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachin unsigned bankID = bankMachine.getBank().ID(); if (!buffer[bankID].empty()) return buffer[bankID].front(); - else - return nullptr; + return nullptr; } bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const @@ -94,10 +93,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const { - if (buffer[bank.ID()].size() >= 2) - return true; - else - return false; + return buffer[bank.ID()].size() >= 2; } const std::vector& SchedulerFifo::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index 8298d362..f71f0f68 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -89,7 +89,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach { // Search for row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : buffer[bankID]) + for (auto *it : buffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -104,7 +104,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank.ID()]) + for (auto *it : buffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index 0cd7dc3b..6017dc28 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -91,7 +91,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM // Filter all row hits Row openRow = bankMachine.getOpenRow(); std::list rowHits; - for (auto it : buffer[bankID]) + for (auto *it : buffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) rowHits.push_back(it); @@ -129,7 +129,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank.ID()]) + for (auto *it : buffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { @@ -143,10 +143,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const { - if (buffer[bank.ID()].size() >= 2) - return true; - else - return false; + return buffer[bank.ID()].size() >= 2; } const std::vector& SchedulerFrFcfsGrp::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 0d9075c9..560470e2 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -98,7 +98,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bankID]) + for (auto *it : readBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -107,7 +107,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No read row hit found or bank precharged return readBuffer[bankID].front(); } - else if (!writeBuffer[bankID].empty()) + if (!writeBuffer[bankID].empty()) { if (bankMachine.isActivated()) { @@ -133,7 +133,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bankID]) + for (auto *it : writeBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -142,7 +142,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No write row hit found or bank precharged return writeBuffer[bankID].front(); } - else if (!readBuffer[bankID].empty()) + if (!readBuffer[bankID].empty()) { if (bankMachine.isActivated()) { @@ -168,7 +168,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; if (command == tlm::TLM_READ_COMMAND) { - for (auto it : readBuffer[bank.ID()]) + for (auto *it : readBuffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { @@ -179,36 +179,28 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman } return false; } - else + + for (auto it : writeBuffer[bank.ID()]) { - for (auto it : writeBuffer[bank.ID()]) + if (ControllerExtension::getRow(*it) == row) { - if (ControllerExtension::getRow(*it) == row) - { - rowHitCounter++; - if (rowHitCounter == 2) - return true; - } + rowHitCounter++; + if (rowHitCounter == 2) + return true; + } } return false; - } } bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const { if (command == tlm::TLM_READ_COMMAND) { - if (readBuffer[bank.ID()].size() >= 2) - return true; - else - return false; + return readBuffer[bank.ID()].size() >= 2; } else { - if (writeBuffer[bank.ID()].size() >= 2) - return true; - else - return false; + return writeBuffer[bank.ID()].size() >= 2; } } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index f6f2c95c..eb207104 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -102,7 +102,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bankID]) + for (auto *it : readBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -111,8 +111,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban // No read row hit found or bank precharged return readBuffer[bankID].front(); } - else - return nullptr; + return nullptr; } else { @@ -122,7 +121,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bankID]) + for (auto *it : writeBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -131,8 +130,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban // No row hit found or bank precharged return writeBuffer[bankID].front(); } - else - return nullptr; + return nullptr; } } @@ -152,27 +150,24 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command } return false; } - else + + for (auto it : writeBuffer[bank.ID()]) { - for (auto it : writeBuffer[bank.ID()]) + if (ControllerExtension::getRow(*it) == row) { - if (ControllerExtension::getRow(*it) == row) - { - rowHitCounter++; - if (rowHitCounter == 2) - return true; - } + rowHitCounter++; + if (rowHitCounter == 2) + return true; + } } return false; - } } bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const { if (!writeMode) return (readBuffer[bank.ID()].size() >= 2); - else - return (writeBuffer[bank.ID()].size() >= 2); + return (writeBuffer[bank.ID()].size() >= 2); } const std::vector& SchedulerGrpFrFcfsWm::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index 0571c120..fed6a3c8 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -160,7 +160,7 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto& it : vXor) + for (const auto &it : vXor) { uint64_t xoredBit; xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); @@ -205,7 +205,7 @@ unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto& it : vXor) + for (const auto &it : vXor) { uint64_t xoredBit; xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index 70e69c0d..2de50c7b 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -87,8 +87,8 @@ protected: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload& trans, - tlm::tlm_phase& phase, sc_core::sc_time& bwDelay); + tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); void b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index dac5e389..8a588d2d 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -147,8 +147,9 @@ private: { //only send the next response when there response for the oldest pending request (requestsInOrder.front()) //has been received - if (!responseIsPendingInInitator - && receivedResponses.count(pendingRequestsInOrder.front())) { + if (!responseIsPendingInInitator && + (receivedResponses.count(pendingRequestsInOrder.front()) != 0)) + { tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, sc_core::SC_ZERO_TIME); diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index ff65b291..c0a988eb 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -77,7 +77,7 @@ Dram::Dram(const sc_module_name& name, const Configuration& config) if (useMalloc) { memory = (unsigned char *)malloc(channelSize); - if (!memory) + if (memory == nullptr) SC_REPORT_FATAL(this->name(), "Memory allocation failed"); } else diff --git a/src/simulator/simulator/Cache.cpp b/src/simulator/simulator/Cache.cpp index 06739cfe..9aaf98ae 100644 --- a/src/simulator/simulator/Cache.cpp +++ b/src/simulator/simulator/Cache.cpp @@ -93,30 +93,35 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) fetchLineAndSendEndRequest(trans); return; } - else if (phase == END_REQ) // <--- DRAM side + + if (phase == END_REQ) // <--- DRAM side { lastEndReq = sc_time_stamp(); clearInitiatorBackpressureAndProcessBuffers(); return; } - else if (phase == BEGIN_RESP && &trans == requestInProgress) // <--- DRAM side + + if (phase == BEGIN_RESP && &trans == requestInProgress) // <--- DRAM side { // Shortcut, 2 phases in one clearInitiatorBackpressureAndProcessBuffers(); sendEndResponseAndFillLine(trans); return; } - else if (phase == BEGIN_RESP) // <--- DRAM side + + if (phase == BEGIN_RESP) // <--- DRAM side { sendEndResponseAndFillLine(trans); return; } - else if (phase == END_RESP) // core side ---> + + if (phase == END_RESP) // core side ---> { clearTargetBackpressureAndProcessLines(trans); return; } - else if (phase == HIT_HANDLING) // direct hit, account for the hit delay + + if (phase == HIT_HANDLING) // direct hit, account for the hit delay { index_t index; tag_t tag; @@ -201,8 +206,8 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) // Cache miss and no fetch in progress. // So evict line and allocate empty line. - auto evictedLine = evictLine(index); - if (!evictedLine) + auto *evictedLine = evictLine(index); + if (evictedLine == nullptr) { // Line eviction not possible. endRequestPending = &trans; @@ -345,9 +350,11 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // oldestline is allocated but not yet valid -> fetch in progress return nullptr; } - else if (std::find_if(mshrQueue.begin(), mshrQueue.end(), - [index, oldestLine](const Mshr &entry) - { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != mshrQueue.end()) + if (std::find_if(mshrQueue.begin(), + mshrQueue.end(), + [index, oldestLine](const Mshr &entry) { + return (index == entry.index) && (oldestLine.tag == entry.tag); + }) != mshrQueue.end()) { // TODO: solve this in a more clever way // There are still entries in mshrQueue to the oldest line -> do not evict it @@ -395,7 +402,7 @@ uint64_t Cache::getAlignedAddress(uint64_t address) const /// Issue read requests for entries in the MshrQueue to the target void Cache::processMshrQueue() { - if (!requestInProgress && !mshrQueue.empty()) + if ((requestInProgress == nullptr) && !mshrQueue.empty()) { // Get the first entry that wasn't already issued to the target auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), [](const Mshr &entry) { return !entry.issued; }); @@ -474,7 +481,7 @@ void Cache::processMshrQueue() /// Processes writeBuffer (dirty cache line evictions) void Cache::processWriteBuffer() { - if (!requestInProgress && !writeBuffer.empty()) + if ((requestInProgress == nullptr) && !writeBuffer.empty()) { tlm_generic_payload &wbTrans = *writeBuffer.front().trans; diff --git a/src/simulator/simulator/Cache.h b/src/simulator/simulator/Cache.h index dc9ff74e..3236d54f 100644 --- a/src/simulator/simulator/Cache.h +++ b/src/simulator/simulator/Cache.h @@ -204,7 +204,7 @@ private: void fillLine(tlm::tlm_generic_payload &trans); void accessCacheAndSendResponse(tlm::tlm_generic_payload &trans); - void allocateLine(CacheLine *line, tag_t tag); + static void allocateLine(CacheLine *line, tag_t tag); bool isAllocated(index_t index, tag_t tag) const; bool hasBufferSpace() const; diff --git a/src/simulator/simulator/MemoryManager.cpp b/src/simulator/simulator/MemoryManager.cpp index 9a62e11d..38f17100 100644 --- a/src/simulator/simulator/MemoryManager.cpp +++ b/src/simulator/simulator/MemoryManager.cpp @@ -82,12 +82,10 @@ tlm_generic_payload& MemoryManager::allocate(unsigned dataLength) return *payload; } - else - { - tlm_generic_payload* result = freePayloads[dataLength].top(); - freePayloads[dataLength].pop(); - return *result; - } + + tlm_generic_payload *result = freePayloads[dataLength].top(); + freePayloads[dataLength].pop(); + return *result; } void MemoryManager::free(tlm_generic_payload* payload) diff --git a/src/simulator/simulator/util.cpp b/src/simulator/simulator/util.cpp index 77266721..4ee1de74 100644 --- a/src/simulator/simulator/util.cpp +++ b/src/simulator/simulator/util.cpp @@ -52,21 +52,21 @@ void loadBar(uint64_t x, uint64_t n, unsigned int w, unsigned int granularity) for (unsigned int x = 0; x < c; x++) std::cout << "█"; - if (rest >= 0 && rest < 0.125f && c != w) + if (rest >= 0 && rest < 0.125F && c != w) std::cout << " "; - if (rest >= 0.125f && rest < 2 * 0.125f) + if (rest >= 0.125F && rest < 2 * 0.125F) std::cout << "▏"; - if (rest >= 2 * 0.125f && rest < 3 * 0.125f) + if (rest >= 2 * 0.125F && rest < 3 * 0.125F) std::cout << "▎"; - if (rest >= 3 * 0.125f && rest < 4 * 0.125f) + if (rest >= 3 * 0.125F && rest < 4 * 0.125F) std::cout << "▍"; - if (rest >= 4 * 0.125f && rest < 5 * 0.125f) + if (rest >= 4 * 0.125F && rest < 5 * 0.125F) std::cout << "▌"; - if (rest >= 5 * 0.125f && rest < 6 * 0.125f) + if (rest >= 5 * 0.125F && rest < 6 * 0.125F) std::cout << "▋"; - if (rest >= 6 * 0.125f && rest < 7 * 0.125f) + if (rest >= 6 * 0.125F && rest < 7 * 0.125F) std::cout << "▊"; - if (rest >= 7 * 0.125f && rest < 8 * 0.125f) + if (rest >= 7 * 0.125F && rest < 8 * 0.125F) std::cout << "▉"; for (unsigned int x = c; x < (w - 1); x++)