derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'work/hbm_rfm_fixes' into 'develop'

Browse Source 
HBM and RFM fixes

See merge request ems/astdm/modeling.dram/dram.sys.5!17
This commit is contained in:
Lukas Steiner
2023-04-26 08:36:08 +00:00
parent 7c0198cf21 fa88b34052
commit 58d486fb82
35 changed files with 79 additions and 125 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
configs/addressmapping/am_hbm3_8Gb_pc_brc.json
View File

@@ -1,15 +1,15 @@
{
"addressmapping": {
"PSEUDOCHANNEL_BIT":[
28
29
],
"BANKGROUP_BIT":[
26,
27
27,
28
],
"BANK_BIT": [
24,
25
25,
26
],
"BYTE_BIT": [
0,
@@ -39,7 +39,8 @@
20,
21,
22,
23
23,
24
]
}
}

4
configs/memspec/HBM3.json
View File

@@ -7,13 +7,13 @@
"nbrOfBanks": 16,
"nbrOfColumns": 128,
"nbrOfPseudoChannels": 2,
"nbrOfRows": 32768,
"nbrOfRows": 65536,
"width": 32,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "",
"memoryType": "HBM3",

2
configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 32,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4000A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4400A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4800A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5200A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5600A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6000A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6400A",
"memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit",
"memoryType": "DDR5",

6
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -66,7 +66,7 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
refMode(memSpec.memarchitecturespec.entries.at("refMode")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAACDR(memSpec.memarchitecturespec.entries.at("RAACDR")),
RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
@@ -196,9 +196,9 @@ sc_time MemSpecDDR5::getRefreshIntervalSB() const
return tREFIsb;
}
unsigned MemSpecDDR5::getRAACDR() const
unsigned MemSpecDDR5::getRAADEC() const
{
return RAACDR;
return RAADEC;
}
unsigned MemSpecDDR5::getRAAIMT() const

4
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
View File

@@ -54,7 +54,7 @@ public:
const unsigned refMode;
const unsigned RAAIMT;
const unsigned RAAMMT;
const unsigned RAACDR;
const unsigned RAADEC;
// Memspec Variables:
const sc_core::sc_time tRCD;
@@ -119,7 +119,7 @@ public:
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalSB() const override;
unsigned getRAACDR() const override;
unsigned getRAADEC() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;

6
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
View File

@@ -58,7 +58,7 @@ MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec)
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAACDR(memSpec.memarchitecturespec.entries.at("RAACDR")),
RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
@@ -179,9 +179,9 @@ TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_gen
}
}
unsigned MemSpecHBM3::getRAACDR() const
unsigned MemSpecHBM3::getRAADEC() const
{
return RAACDR;
return RAADEC;
}
unsigned MemSpecHBM3::getRAAIMT() const

4
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
View File

@@ -47,7 +47,7 @@ public:
const unsigned RAAIMT;
const unsigned RAAMMT;
const unsigned RAACDR;
const unsigned RAADEC;
// Memspec Variables:
const sc_core::sc_time tDQSCK;
@@ -89,7 +89,7 @@ public:
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
unsigned getRAACDR() const override;
unsigned getRAADEC() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;

73
src/configuration/DRAMSys/config/McConfig.cpp
View File

@@ -1,73 +0,0 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Derek Christ
*/
#include "McConfig.h"
namespace DRAMSys::Config
{
void to_json(json_t &j, const RefreshPolicyType &r)
{
if (r == RefreshPolicyType::NoRefresh)
j = "NoRefresh";
else if (r == RefreshPolicyType::AllBank)
j = "AllBank";
else if (r == RefreshPolicyType::PerBank)
j = "PerBank";
else if (r == RefreshPolicyType::Per2Bank)
j = "Per2Bank";
else if (r == RefreshPolicyType::SameBank)
j = "SameBank";
else
j = nullptr;
}
void from_json(const json_t &j, RefreshPolicyType &r)
{
if (j == "NoRefresh")
r = RefreshPolicyType::NoRefresh;
else if (j == "AllBank" || j == "Rankwise")
r = RefreshPolicyType::AllBank;
else if (j == "PerBank" || j == "Bankwise")
r = RefreshPolicyType::PerBank;
else if (j == "SameBank" || j == "Groupwise")
r = RefreshPolicyType::SameBank;
else if (j == "Per2Bank")
r = RefreshPolicyType::Per2Bank;
else
r = RefreshPolicyType::Invalid;
}
} // namespace DRAMSys::Config

19
src/configuration/DRAMSys/config/McConfig.h
View File

@@ -123,6 +123,19 @@ enum class RefreshPolicyType
Invalid = -1
};
NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicyType, {{RefreshPolicyType::Invalid, nullptr},
{RefreshPolicyType::NoRefresh, "NoRefresh"},
{RefreshPolicyType::AllBank, "AllBank"},
{RefreshPolicyType::PerBank, "PerBank"},
{RefreshPolicyType::Per2Bank, "Per2Bank"},
{RefreshPolicyType::SameBank, "SameBank"},
// Alternative conversions to provide backwards-compatibility
// when deserializing. Will not be used for serializing.
{RefreshPolicyType::AllBank, "Rankwise"},
{RefreshPolicyType::PerBank, "Bankwise"},
{RefreshPolicyType::SameBank, "Groupwise"}})
enum class PowerDownPolicyType
{
NoPowerDown,
@@ -202,12 +215,6 @@ NLOHMANN_JSONIFY_ALL_THINGS(McConfig,
BlockingReadDelay,
BlockingWriteDelay)
void to_json(json_t &j, const RefreshPolicyType &r);
void from_json(const json_t &j, RefreshPolicyType &r);
// void from_dump(const std::string &dump, McConfig &c);
// std::string dump(const McConfig &c, unsigned int indentation = -1);
} // namespace Configuration
#endif // DRAMSYSCONFIGURATION_MCCONFIG_H

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
View File

@@ -122,7 +122,7 @@ unsigned MemSpec::getPer2BankOffset() const
return 0;
}
unsigned MemSpec::getRAACDR() const
unsigned MemSpec::getRAADEC() const
{
SC_REPORT_FATAL("MemSpec", "Refresh Management not supported");
return 0;

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
View File

@@ -92,7 +92,7 @@ public:
virtual unsigned getRAAIMT() const;
virtual unsigned getRAAMMT() const;
virtual unsigned getRAACDR() const;
virtual unsigned getRAADEC() const;
virtual bool hasRasAndCasBus() const;

4
src/libdramsys/DRAMSys/controller/BankMachine.cpp
View File

@@ -85,8 +85,8 @@ void BankMachine::update(Command command)
if (refreshManagement)
{
if (refreshManagementCounter > memSpec.getRAACDR())
refreshManagementCounter -= memSpec.getRAACDR();
if (refreshManagementCounter > memSpec.getRAADEC())
refreshManagementCounter -= memSpec.getRAADEC();
else
refreshManagementCounter = 0;
}

6
src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
View File

@@ -56,6 +56,12 @@ AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMap
std::copy(rankBits->begin(), rankBits->end(), std::back_inserter(vRankBits));
}
// HBM pseudo channels are internally modelled as ranks
if (const auto &pseudoChannelBits = addressMapping.PSEUDOCHANNEL_BIT)
{
std::copy(pseudoChannelBits->begin(), pseudoChannelBits->end(), std::back_inserter(vRankBits));
}
if (const auto& bankGroupBits = addressMapping.BANKGROUP_BIT)
{
std::copy(bankGroupBits->begin(), bankGroupBits->end(), std::back_inserter(vBankGroupBits));

2
tests/tests_configuration/reference.json
View File

@@ -66,7 +66,7 @@
},
"memspec": {
"memarchitecturespec": {
"RAACDR": 1,
"RAADEC": 1,
"RAAIMT": 32,
"RAAMMT": 96,
"burstLength": 16,

2
tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 32,
"RAAMMT" : 96,
"RAACDR" : 16
"RAADEC" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",

17
tests/tests_configuration/test_configuration.cpp
View File

@@ -141,7 +141,7 @@ DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
{"refMode", 1},
{"RAAIMT", 32},
{"RAAMMT", 96},
{"RAACDR", 1}}};
{"RAADEC", 1}}};
MemTimingSpecType memTimingSpec{{{
{"RCD", 22}, {"PPD", 2}, {"RP", 22}, {"RAS", 52},
@@ -286,6 +286,19 @@ TEST(Configuration, FromPath)
Configuration config = from_path("reference.json");
}
TEST(RefreshPolicyType, BackwardsCompatibility)
{
// Deserializing
EXPECT_EQ(json_t("Rankwise").get<RefreshPolicyType>(), RefreshPolicyType::AllBank);
EXPECT_EQ(json_t("Bankwise").get<RefreshPolicyType>(), RefreshPolicyType::PerBank);
EXPECT_EQ(json_t("Groupwise").get<RefreshPolicyType>(), RefreshPolicyType::SameBank);
// Serializing
EXPECT_EQ(json_t(RefreshPolicyType::AllBank).get<std::string>(), "AllBank");
EXPECT_EQ(json_t(RefreshPolicyType::PerBank).get<std::string>(), "PerBank");
EXPECT_EQ(json_t(RefreshPolicyType::SameBank).get<std::string>(), "SameBank");
}
TEST_F(ConfigurationTest, SimConfig)
{
std::string_view simconfig_string = R"(
@@ -352,7 +365,7 @@ TEST_F(ConfigurationTest, MemSpec)
{
"memspec": {
"memarchitecturespec": {
"RAACDR": 1,
"RAADEC": 1,
"RAAIMT": 32,
"RAAMMT": 96,
"burstLength": 16,