diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 9e29b936..daff5160 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -297,7 +297,7 @@ void TlmRecorder::prepareSqlStatements() insertCommandLengthsString = "INSERT INTO CommandLengths VALUES" - "(:NOP, :RD, :WR, :RDA, :WRA, :ACT, :PRE, :REFB, :PRESB, :REFSB, :PREA, :REFA, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)"; + "(:NOP, :RD, :WR, :RDA, :WRA, :ACT, :PRE, :REFB, :PRESB, :REFSB, :RFMSB, :PREA, :REFA, :RFMAB, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)"; insertDebugMessageString = "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; @@ -378,14 +378,16 @@ void TlmRecorder::insertCommandLengths() sqlite3_bind_int(insertCommandLengthsStatement, 8, static_cast(lround(memSpec->getCommandLength(Command::REFB) / memSpec->tCK))); sqlite3_bind_int(insertCommandLengthsStatement, 9, static_cast(lround(memSpec->getCommandLength(Command::PRESB) / memSpec->tCK))); sqlite3_bind_int(insertCommandLengthsStatement, 10, static_cast(lround(memSpec->getCommandLength(Command::REFSB) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 11, static_cast(lround(memSpec->getCommandLength(Command::PREA) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 12, static_cast(lround(memSpec->getCommandLength(Command::REFA) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 13, static_cast(lround(memSpec->getCommandLength(Command::PDEA) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 14, static_cast(lround(memSpec->getCommandLength(Command::PDXA) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 15, static_cast(lround(memSpec->getCommandLength(Command::PDEP) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 16, static_cast(lround(memSpec->getCommandLength(Command::PDXP) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 17, static_cast(lround(memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK))); - sqlite3_bind_int(insertCommandLengthsStatement, 18, static_cast(lround(memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 11, static_cast(lround(memSpec->getCommandLength(Command::RFMSB) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 12, static_cast(lround(memSpec->getCommandLength(Command::PREA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 13, static_cast(lround(memSpec->getCommandLength(Command::REFA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 14, static_cast(lround(memSpec->getCommandLength(Command::RFMAB) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 15, static_cast(lround(memSpec->getCommandLength(Command::PDEA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 16, static_cast(lround(memSpec->getCommandLength(Command::PDXA) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 17, static_cast(lround(memSpec->getCommandLength(Command::PDEP) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 18, static_cast(lround(memSpec->getCommandLength(Command::PDXP) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 19, static_cast(lround(memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK))); + sqlite3_bind_int(insertCommandLengthsStatement, 20, static_cast(lround(memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK))); executeSqlStatement(insertCommandLengthsStatement); } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 553f35de..648c9fdd 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -196,8 +196,10 @@ private: " REFB INTEGER, \n" " PRESB INTEGER, \n" " REFSB INTEGER, \n" + " RFMSB INTEGER, \n" " PREA INTEGER, \n" " REFA INTEGER, \n" + " RFMAB INTEGER, \n" " PDEA INTEGER, \n" " PDXA INTEGER, \n" " PDEP INTEGER, \n" diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 4729f338..ede62a21 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -138,7 +138,9 @@ MemSpecDDR5::MemSpecDDR5(json &memspec) commandLengthInCycles[Command::WR] = 4; commandLengthInCycles[Command::WRA] = 4; commandLengthInCycles[Command::REFA] = 2; + commandLengthInCycles[Command::RFMAB] = 2; commandLengthInCycles[Command::REFSB] = 2; + commandLengthInCycles[Command::RFMSB] = 2; commandLengthInCycles[Command::PDEA] = 2; commandLengthInCycles[Command::PDXA] = 2; commandLengthInCycles[Command::PDEP] = 2; diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 0f6664df..b7813666 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -46,49 +46,57 @@ Command::Command(Command::Type type) : type(type) {} Command::Command(tlm_phase phase) { assert(phase >= BEGIN_RD && phase <= END_SREF); - static constexpr std::array commandOfPhase = - {Command::RD, - Command::WR, - Command::RDA, - Command::WRA, - Command::ACT, - Command::PRE, - Command::REFB, - Command::PRESB, - Command::REFSB, - Command::PREA, - Command::REFA, - Command::PDEA, - Command::PDEP, - Command::SREFEN, - Command::PDXA, - Command::PDXP, - Command::SREFEX}; + static constexpr std::array commandOfPhase = + { + Command::RD, // 1 + Command::WR, // 2 + Command::RDA, // 3 + Command::WRA, // 4 + Command::ACT, // 5 + Command::PRE, // 6 + Command::REFB, // 7 + Command::PRESB, // 8 + Command::REFSB, // 9 + Command::RFMSB, // 10 + Command::PREA, // 11 + Command::REFA, // 12 + Command::RFMAB, // 13 + Command::PDEA, // 14 + Command::PDEP, // 15 + Command::SREFEN,// 16 + Command::PDXA, // 17 + Command::PDXP, // 18 + Command::SREFEX // 19 + }; type = commandOfPhase[phase - BEGIN_RD]; } std::string Command::toString() const { assert(type >= Command::NOP && type <= Command::SREFEX); - static std::array stringOfCommand = - {"NOP", - "RD", - "WR", - "RDA", - "WRA", - "ACT", - "PRE", - "REFB", - "PRESB", - "REFSB", - "PREA", - "REFA", - "PDEA", - "PDEP", - "SREFEN", - "PDXA", - "PDXP", - "SREFEX"}; + static std::array stringOfCommand = + { + "NOP", // 0 + "RD", // 1 + "WR", // 2 + "RDA", // 3 + "WRA", // 4 + "ACT", // 5 + "PRE", // 6 + "REFB", // 7 + "PRESB", // 8 + "REFSB", // 9 + "RFMSB", // 10 + "PREA", // 11 + "REFA", // 12 + "RFMA", // 13 + "PDEA", // 14 + "PDEP", // 15 + "SREFEN", // 16 + "PDXA", // 17 + "PDXP", // 18 + "SREFEX" // 19 + }; return stringOfCommand[type]; } @@ -100,25 +108,29 @@ unsigned Command::numberOfCommands() tlm_phase Command::toPhase() const { assert(type >= Command::NOP && type <= Command::SREFEX); - static std::array phaseOfCommand = - {UNINITIALIZED_PHASE, - BEGIN_RD, - BEGIN_WR, - BEGIN_RDA, - BEGIN_WRA, - BEGIN_ACT, - BEGIN_PRE, - BEGIN_REFB, - BEGIN_PRESB, - BEGIN_REFSB, - BEGIN_PREA, - BEGIN_REFA, - BEGIN_PDNA, - BEGIN_PDNP, - BEGIN_SREF, - END_PDNA, - END_PDNP, - END_SREF}; + static std::array phaseOfCommand = + { + UNINITIALIZED_PHASE, // 0 + BEGIN_RD, // 1 + BEGIN_WR, // 2 + BEGIN_RDA, // 3 + BEGIN_WRA, // 4 + BEGIN_ACT, // 5 + BEGIN_PRE, // 6 + BEGIN_REFB, // 7 + BEGIN_PRESB, // 8 + BEGIN_REFSB, // 9 + BEGIN_RFMSB, // 10 + BEGIN_PREA, // 11 + BEGIN_REFA, // 12 + BEGIN_RFMAB, // 13 + BEGIN_PDNA, // 14 + BEGIN_PDNP, // 15 + BEGIN_SREF, // 16 + END_PDNA, // 17 + END_PDNP, // 18 + END_SREF // 19 + }; return phaseOfCommand[type]; } @@ -126,24 +138,28 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) { // TODO: add correct phases when DRAMPower supports DDR5 same bank refresh assert(phase >= BEGIN_RD && phase <= END_SREF); - static std::array phaseOfCommand = - {MemCommand::RD, - MemCommand::WR, - MemCommand::RDA, - MemCommand::WRA, - MemCommand::ACT, - MemCommand::PRE, - MemCommand::REFB, - MemCommand::NOP, - MemCommand::NOP, - MemCommand::PREA, - MemCommand::REF, - MemCommand::PDN_S_ACT, - MemCommand::PDN_S_PRE, - MemCommand::SREN, - MemCommand::PUP_ACT, - MemCommand::PUP_PRE, - MemCommand::SREX}; + static std::array phaseOfCommand = + { + MemCommand::RD, // 1 + MemCommand::WR, // 2 + MemCommand::RDA, // 3 + MemCommand::WRA, // 4 + MemCommand::ACT, // 5 + MemCommand::PRE, // 6 + MemCommand::REFB, // 7 + MemCommand::NOP, // 8 + MemCommand::NOP, // 9 + MemCommand::NOP, // 10 + MemCommand::PREA, // 11 + MemCommand::REF, // 12 + MemCommand::NOP, // 13 + MemCommand::PDN_S_ACT, // 14 + MemCommand::PDN_S_PRE, // 15 + MemCommand::SREN, // 16 + MemCommand::PUP_ACT, // 17 + MemCommand::PUP_PRE, // 18 + MemCommand::SREX // 19 + }; return phaseOfCommand[phase - BEGIN_RD]; } @@ -155,7 +171,7 @@ bool phaseNeedsEnd(tlm_phase phase) tlm_phase getEndPhase(tlm_phase phase) { assert(phase >= BEGIN_RD && phase <= BEGIN_REFA); - return (phase + 17); + return (phase + Command::Type::END_ENUM - 1); } bool Command::isBankCommand() const diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index bb5af1da..62bcb3d2 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -60,51 +60,58 @@ DECLARE_EXTENDED_PHASE(BEGIN_PRE); // 10 DECLARE_EXTENDED_PHASE(BEGIN_REFB); // 11 DECLARE_EXTENDED_PHASE(BEGIN_PRESB); // 12 DECLARE_EXTENDED_PHASE(BEGIN_REFSB); // 13 -DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 14 -DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 15 -DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 16 -DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 17 -DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18 +DECLARE_EXTENDED_PHASE(BEGIN_RFMSB); // 14 +DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 15 +DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 16 +DECLARE_EXTENDED_PHASE(BEGIN_RFMAB); // 17 +DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 18 +DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 19 +DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 20 -DECLARE_EXTENDED_PHASE(END_PDNA); // 19 -DECLARE_EXTENDED_PHASE(END_PDNP); // 20 -DECLARE_EXTENDED_PHASE(END_SREF); // 21 +DECLARE_EXTENDED_PHASE(END_PDNA); // 21 +DECLARE_EXTENDED_PHASE(END_PDNP); // 22 +DECLARE_EXTENDED_PHASE(END_SREF); // 23 -DECLARE_EXTENDED_PHASE(END_RD); // 22 -DECLARE_EXTENDED_PHASE(END_WR); // 23 -DECLARE_EXTENDED_PHASE(END_RDA); // 24 -DECLARE_EXTENDED_PHASE(END_WRA); // 25 -DECLARE_EXTENDED_PHASE(END_ACT); // 26 -DECLARE_EXTENDED_PHASE(END_PRE); // 27 -DECLARE_EXTENDED_PHASE(END_REFB); // 28 -DECLARE_EXTENDED_PHASE(END_PRESB); // 29 -DECLARE_EXTENDED_PHASE(END_REFSB); // 30 -DECLARE_EXTENDED_PHASE(END_PREA); // 31 -DECLARE_EXTENDED_PHASE(END_REFA); // 32 +DECLARE_EXTENDED_PHASE(END_RD); // 24 +DECLARE_EXTENDED_PHASE(END_WR); // 25 +DECLARE_EXTENDED_PHASE(END_RDA); // 26 +DECLARE_EXTENDED_PHASE(END_WRA); // 27 +DECLARE_EXTENDED_PHASE(END_ACT); // 28 +DECLARE_EXTENDED_PHASE(END_PRE); // 29 +DECLARE_EXTENDED_PHASE(END_REFB); // 30 +DECLARE_EXTENDED_PHASE(END_PRESB); // 31 +DECLARE_EXTENDED_PHASE(END_REFSB); // 32 +DECLARE_EXTENDED_PHASE(END_RFMSB); // 33 +DECLARE_EXTENDED_PHASE(END_PREA); // 34 +DECLARE_EXTENDED_PHASE(END_REFA); // 35 +DECLARE_EXTENDED_PHASE(END_RFMAB); // 36 class Command { public: enum Type : uint8_t { - NOP, // 0 - RD, // 1 - WR, // 2 - RDA, // 3 - WRA, // 4 - ACT, // 5 - PRE, // 6 - REFB, // 7 - PRESB, // 8 - REFSB, // 9 - PREA, // 10 - REFA, // 11 - PDEA, // 12 - PDEP, // 13 - SREFEN, // 14 - PDXA, // 15 - PDXP, // 16 - SREFEX // 17 + NOP, // 0 + RD, // 1 + WR, // 2 + RDA, // 3 + WRA, // 4 + ACT, // 5 + PRE, // 6 + REFB, // 7 + PRESB, // 8 + REFSB, // 9 + RFMSB, // 10 + PREA, // 11 + REFA, // 12 + RFMAB, // 13 + PDEA, // 14 + PDEP, // 15 + SREFEN, // 16 + PDXA, // 17 + PDXP, // 18 + SREFEX, // 19 + END_ENUM // To mark the end of this enumeration }; private: