From 4d936892d9550d2a31a305394e963aa131b59314 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 18 Aug 2019 19:23:53 +0200 Subject: [PATCH] Included DRAMPower dummy, it can now be switched on and off again. --- DRAMSys/library/src/simulation/Dram.cpp | 41 ++-- DRAMSys/library/src/simulation/Dram.h | 11 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 176 +++++++------- DRAMSys/library/src/simulation/DramDDR4.cpp | 177 +++++++------- .../library/src/simulation/DramRecordable.cpp | 48 ++-- .../library/src/simulation/DramRecordable.h | 4 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 217 +++++++++--------- 7 files changed, 351 insertions(+), 323 deletions(-) diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index bc5ae253..36f1fa5c 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -56,7 +56,6 @@ #include "../common/utils.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -using namespace std; using namespace tlm; using namespace Data; @@ -71,23 +70,31 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") Dram::~Dram() { - if (!Configuration::getInstance().DatabaseRecording) - DRAMPower->calcEnergy(); + if (Configuration::getInstance().PowerAnalysis) + { + libDRAMPower *DRAMPower = dynamic_cast(this->DRAMPower); + if (DRAMPower == nullptr) + SC_REPORT_FATAL("Dram", "Power Analysis active but libDRAMPowerIF instantiated"); - // Print the final total energy and the average power for - // the simulation: - cout << name() << string(" Total Energy: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" pJ") - << endl; + if (!Configuration::getInstance().DatabaseRecording) + DRAMPower->calcEnergy(); - cout << name() << string(" Average Power: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getPower().average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" mW") << endl; + // Print the final total energy and the average power for + // the simulation: + std::cout << name() << std::string(" Total Energy: ") + << std::fixed << std::setprecision( 2 ) + << DRAMPower->getEnergy().total_energy + * Configuration::getInstance().NumberOfDevicesOnDIMM + << std::string(" pJ") + << std::endl; + + std::cout << name() << std::string(" Average Power: ") + << std::fixed << std::setprecision( 2 ) + << DRAMPower->getPower().average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM + << std::string(" mW") << std::endl; + } + delete DRAMPower; if (Configuration::getInstance().UseMalloc) free(memory); @@ -96,8 +103,6 @@ Dram::~Dram() tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - MemSpec *memSpec = Configuration::getInstance().memSpec; - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 4ae01c33..48208e92 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -45,6 +45,7 @@ #include #include "../common/protocol.h" #include "../controller/core/configuration/Configuration.h" +#include "../controller/core/configuration/MemSpec.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; @@ -60,11 +61,16 @@ private: bool powerAnalysis = Configuration::getInstance().PowerAnalysis; protected: + Dram(sc_module_name); + SC_HAS_PROCESS(Dram); + + MemSpec *memSpec = Configuration::getInstance().memSpec; + // Data Storage: StorageMode StoreMode = Configuration::getInstance().StoreMode; unsigned char *memory; - libDRAMPower *DRAMPower; + libDRAMPowerIF *DRAMPower; virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay); @@ -77,9 +83,6 @@ protected: public: tlm_utils::simple_target_socket tSocket; - Dram(sc_module_name); - SC_HAS_PROCESS(Dram); - virtual ~Dram(); }; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 7b91109d..7655a1dd 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -38,6 +38,7 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../controller/core/configuration/MemSpec.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { @@ -45,97 +46,102 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); // Parameters for DRAMPower - MemSpecDDR3 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; + if (Configuration::getInstance().PowerAnalysis) + { + sc_time clk = memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD / clk; - memTimingSpec.CCD_L = memSpec->tCCD / clk; - memTimingSpec.CCD_S = memSpec->tCCD / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tFAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD / clk; - memTimingSpec.RRD_L = memSpec->tRRD / clk; - memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tFAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR / clk; - memTimingSpec.WTR_L = memSpec->tWTR / clk; - memTimingSpec.WTR_S = memSpec->tWTR / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD / clk; + memTimingSpec.CCD_L = memSpec->tCCD / clk; + memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tFAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD / clk; + memTimingSpec.RRD_L = memSpec->tRRD / clk; + memTimingSpec.RRD_S = memSpec->tRRD / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tFAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR / clk; + memTimingSpec.WTR_L = memSpec->tWTR / clk; + memTimingSpec.WTR_S = memSpec->tWTR / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, 0); + } + else + DRAMPower = new libDRAMPowerIF(); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 9f8e85d6..282225c5 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -38,6 +38,7 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../controller/core/configuration/MemSpec.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { @@ -45,98 +46,102 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); // Parameters for DRAMPower - MemSpecDDR4 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; + if (Configuration::getInstance().PowerAnalysis) + { + sc_time clk = memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tFAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tFAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tFAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tFAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + DRAMPower = new libDRAMPower(powerSpec, 0); + } + else + DRAMPower = new libDRAMPowerIF(); } diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index c54e255d..fa131a8e 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -50,14 +50,25 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe { // Create a thread that is triggered every $powerWindowSize // to generate a Power over Time plot in the Trace analyzer: - SC_THREAD(powerWindow); + if (Configuration::getInstance().PowerAnalysis) + { + DRAMPower = dynamic_cast(Dram::DRAMPower); + if (DRAMPower == nullptr) + SC_REPORT_FATAL("DramRecordable", "Power Analysis active but libDRAMPowerIF instantiated"); + SC_THREAD(powerWindow); + } } template DramRecordable::~DramRecordable() { - this->DRAMPower->calcEnergy(); - recordPower(); + if (Configuration::getInstance().PowerAnalysis) + { + DRAMPower->calcEnergy(); + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + DRAMPower->getPower().window_average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM); + } tlmRecorder->closeConnection(); } @@ -65,18 +76,17 @@ template tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - MemSpec *memSpec = Configuration::getInstance().memSpec; // Recording time used by the traceAnalyzer sc_time recTime = sc_time_stamp() + delay; // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += memSpec->getExecutionTime(Command::PDXA, payload); + recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += memSpec->getExecutionTime(Command::PDXP, payload); + recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); else if (phase == END_SREF || phase == END_SREFB) - recTime += memSpec->getExecutionTime(Command::SREFEX, payload); + recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); @@ -106,37 +116,29 @@ void DramRecordable::powerWindow() // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clkCycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); + clkCycles = sc_time_stamp().value() / this->memSpec->clk.value(); - this->DRAMPower->calcWindowEnergy(clkCycles); + DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(this->DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database - recordPower(); + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + DRAMPower->getPower().window_average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW PRINTDEBUGMESSAGE(this->name(), string("\tWindow Energy: \t") + to_string( - this->DRAMPower->getEnergy().window_energy * + DRAMPower->getEnergy().window_energy * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); PRINTDEBUGMESSAGE(this->name(), string("\tWindow Average Power: \t") + to_string( - this->DRAMPower->getPower().window_average_power * + DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); } while (true); } -template -void DramRecordable::recordPower() -{ - tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM); -} - - template class DramRecordable; template class DramRecordable; template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index aa09e778..df518bdc 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -57,6 +57,8 @@ private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay); TlmRecorder *tlmRecorder; + + libDRAMPower *DRAMPower; sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * Configuration::getInstance().WindowSize; @@ -71,8 +73,6 @@ private: // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for visualization purposes. void powerWindow(); - - void recordPower(); }; #endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 65cdeacb..dbc5b8fa 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -41,121 +41,131 @@ #include "../controller/core/configuration/Configuration.h" #include "../error/errormodel.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../controller/core/configuration/MemSpec.h" using namespace tlm; DramWideIO::DramWideIO(sc_module_name name) : Dram(name) { - // For each bank in a channel a error Model is created: - if (StoreMode == StorageMode::ErrorModel) - { - if (Configuration::getInstance().UseMalloc) - free(memory); - - for (unsigned i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; - i++) - { - errorModel *em; - std::string errorModelStr = "errorModel_bank" + std::to_string(i); - em = new errorModel(errorModelStr.c_str(), DRAMPower); - ememory.push_back(em); - } - } - // Parameters for DRAMPower - MemSpecWideIO *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; + if (Configuration::getInstance().PowerAnalysis) + { + sc_time clk = memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD / clk; - memTimingSpec.CCD_L = memSpec->tCCD / clk; - memTimingSpec.CCD_S = memSpec->tCCD / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tTAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD / clk; - memTimingSpec.RRD_L = memSpec->tRRD / clk; - memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tTAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR / clk; - memTimingSpec.WTR_L = memSpec->tWTR / clk; - memTimingSpec.WTR_S = memSpec->tWTR / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXP / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXS / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD / clk; + memTimingSpec.CCD_L = memSpec->tCCD / clk; + memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tTAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD / clk; + memTimingSpec.RRD_L = memSpec->tRRD / clk; + memTimingSpec.RRD_S = memSpec->tRRD / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tTAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR / clk; + memTimingSpec.WTR_L = memSpec->tWTR / clk; + memTimingSpec.WTR_S = memSpec->tWTR / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXP / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXS / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + libDRAMPower *DRAMPower = new libDRAMPower(powerSpec, 0); + + // For each bank in a channel a error Model is created: + if (StoreMode == StorageMode::ErrorModel) + { + if (Configuration::getInstance().UseMalloc) + free(memory); + + for (unsigned i = 0; i < memSpec->NumberOfBanks; i++) + { + errorModel *em; + std::string errorModelStr = "errorModel_bank" + std::to_string(i); + em = new errorModel(errorModelStr.c_str(), DRAMPower); + ememory.push_back(em); + } + } + this->DRAMPower = DRAMPower; + } + else + { + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramWideIO", "Error modeling without power analysis is not supported"); + DRAMPower = new libDRAMPowerIF(); + } } DramWideIO::~DramWideIO() @@ -168,13 +178,10 @@ DramWideIO::~DramWideIO() tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - MemSpec *memSpec = Configuration::getInstance().memSpec; - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); + unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); if (phase == BEGIN_PREB) {