derek/DRAMSys
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This commit is contained in:
robert
2014-04-02 23:13:02 +02:00
parent e930002e5c
commit 4d3de95225
21 changed files with 652 additions and 256 deletions
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10
dram/src/core/ControllerState.cpp
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@@ -66,10 +66,9 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand)
break;
case Command::Activate:
bankStates.openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow());
nActivateWindow.put(scheduledCommand.getStart());
activates.blockSlots(scheduledCommand.getStart() - config->Timings.tRRD,
scheduledCommand.getStart() + config->Timings.tRRD, true);
lastActivates.emplace(scheduledCommand.getStart());
break;
case Command::Precharge:
bankStates.closeRowBuffer(scheduledCommand.getBank());
break;
@@ -85,9 +84,8 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand)
void ControllerState::cleanUp(sc_time time)
{
bus.cleanUpSlots(time);
activates.cleanUpSlots(time);
lastDataStrobeCommands.remove_if([&](ScheduledCommand command){return command.getEnd() < time;});
lastDataStrobeCommands.remove_if([&](ScheduledCommand command){return command.getEnd() < time - config->Timings.tStrobeHistory;});
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory));
}
} /* namespace controller */