From 4950a2587e63f901d57881fc7d21c8bdeca839a4 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 26 Sep 2019 16:55:20 +0200 Subject: [PATCH] Included LPDDR4 memspec and Dram, changed structure of MemSpec.h, removed ScheduledCommand. --- DRAMSys/library/library.pro | 11 +- .../src/configuration/ConfigurationLoader.cpp | 88 ++++++++--- .../src/configuration/memspec/MemSpec.cpp | 69 ++------- .../src/configuration/memspec/MemSpec.h | 31 +--- .../src/configuration/memspec/MemSpecDDR3.cpp | 88 +++++++++++ .../src/configuration/memspec/MemSpecDDR3.h | 22 +++ .../src/configuration/memspec/MemSpecDDR4.cpp | 88 +++++++++++ .../src/configuration/memspec/MemSpecDDR4.h | 22 +++ .../configuration/memspec/MemSpecLPDDR4.cpp | 53 +++++-- .../src/configuration/memspec/MemSpecLPDDR4.h | 40 ++++- .../configuration/memspec/MemSpecWideIO.cpp | 88 +++++++++++ .../src/configuration/memspec/MemSpecWideIO.h | 22 +++ .../core/scheduling/ScheduledCommand.cpp | 145 ------------------ .../core/scheduling/ScheduledCommand.h | 95 ------------ .../src/controller/refresh/RefreshManager.cpp | 4 +- .../refresh/RefreshManagerBankwise.cpp | 6 +- DRAMSys/library/src/simulation/DramLPDDR4.cpp | 56 +++++++ DRAMSys/library/src/simulation/DramLPDDR4.h | 51 ++++++ 18 files changed, 603 insertions(+), 376 deletions(-) create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h create mode 100644 DRAMSys/library/src/simulation/DramLPDDR4.cpp create mode 100644 DRAMSys/library/src/simulation/DramLPDDR4.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 5c0df5d3..095f0c77 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -93,7 +93,6 @@ SOURCES += \ src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ src/controller/core/powerdown/PowerDownManagerBankwise.cpp \ src/controller/core/powerdown/PowerDownManager.cpp \ - src/controller/core/scheduling/ScheduledCommand.cpp \ src/simulation/MemoryManager.cpp \ src/simulation/TemperatureController.cpp \ src/configuration/ConfigurationLoader.cpp \ @@ -135,8 +134,12 @@ SOURCES += \ src/controller/refresh/RefreshManagerDummy.cpp \ src/controller/refresh/RefreshManagerBankwise.cpp \ src/controller/checker/CheckerWideIO.cpp \ + src/configuration/memspec/MemSpecDDR3.cpp \ + src/configuration/memspec/MemSpecDDR4.cpp \ + src/configuration/memspec/MemSpecWideIO.cpp \ src/configuration/memspec/MemSpecLPDDR4.cpp \ - src/controller/checker/CheckerDDR4.cpp + src/controller/checker/CheckerDDR4.cpp \ + src/simulation/DramLPDDR4.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -148,7 +151,6 @@ HEADERS += \ src/controller/core/powerdown/PowerDownManagerTimeout.h \ src/controller/core/powerdown/PowerDownManagerBankwise.h \ src/controller/core/powerdown/PowerDownManager.h \ - src/controller/core/scheduling/ScheduledCommand.h \ src/simulation/TracePlayer.h \ src/simulation/MemoryManager.h \ src/simulation/Dram.h \ @@ -209,7 +211,8 @@ HEADERS += \ src/configuration/memspec/MemSpecWideIO.h \ src/configuration/memspec/MemSpecDDR4.h \ src/configuration/memspec/MemSpecLPDDR4.h \ - src/controller/checker/CheckerDDR4.h + src/controller/checker/CheckerDDR4.h \ + src/simulation/DramLPDDR4.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 91967821..e21b9552 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -187,23 +187,10 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); memSpec->bitWidth = queryUIntParameter(architecture, "width"); - // MemTimings + // Clock XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); memSpec->clk = FrequencyToClk(memSpec->clkMHz); - sc_time clk = memSpec->clk; - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -232,6 +219,18 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); @@ -266,6 +265,18 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); @@ -323,19 +334,34 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCDMW = clk * queryUIntParameter(timings, "CCDMW"); - memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB"); + memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB"); memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); - memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); - memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRPST = clk * queryUIntParameter(timings, "RPST"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS"); + memSpec->tDQS2DQ = clk * queryUIntParameter(timings, "DQS2DQ"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWPRE = clk * queryUIntParameter(timings, "WPRE"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tSR = clk * queryUIntParameter(timings, "SR"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XSR"); + memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE"); // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -363,6 +389,18 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 83b32a7f..1dd1c790 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -62,59 +62,16 @@ sc_time MemSpec::getWriteAccessTime() const return clk * (BurstLength / DataRate); } -sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const -{ - if (command == Command::PDEA || command == Command::PDEP) - return tCKE; - else if (command == Command::SREFEN) - return tCKESR; - else - { - SC_REPORT_FATAL("getMinimalExecutionTime", - "command is not know or command has a fixed execution time"); - return SC_ZERO_TIME; - } -} - -TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - -// Returns the execution time for commands that have a fixed execution time -sc_time MemSpec::getExecutionTime(Command command) const -{ - if (command == Command::PRE || command == Command::PREA) - return tRP; - else if (command == Command::ACT) - return tRCD; - else if (command == Command::RD) - return tRL + getReadAccessTime(); - else if (command == Command::RDA) - // this time is wrong (controller internally waits for tRAS) - return tRTP + tRP; - else if (command == Command::WR) - return tWL + getWriteAccessTime(); - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; - else if (command == Command::REFA) - return tRFC; - else if (command == Command::REFB) - return tRFC; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } -} +//sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const +//{ +// if (command == Command::PDEA || command == Command::PDEP) +// return tCKE; +// else if (command == Command::SREFEN) +// return tCKESR; +// else +// { +// SC_REPORT_FATAL("getMinimalExecutionTime", +// "command is not know or command has a fixed execution time"); +// return SC_ZERO_TIME; +// } +//} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index f053be72..687eedb9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -51,15 +51,16 @@ struct MemSpec const std::vector &getBanks() const; sc_time getWriteAccessTime() const; - sc_time getReadAccessTime() const; + virtual sc_time getRefreshIntervalAB() const = 0; + virtual sc_time getRefreshIntervalSB() const = 0; + + virtual sc_time getExecutionTime(Command) const = 0; + virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; + // Returns the minimum execution time for commands that have a variable execution time - sc_time getMinExecutionTimeForPowerDownCmd(Command command) const; - - virtual sc_time getExecutionTime(Command) const; - - virtual TimeInterval getIntervalOnDataStrobe(Command) const; + //virtual sc_time getMinExecutionTimeForPowerDownCmd(Command command) const = 0; std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; @@ -73,25 +74,9 @@ struct MemSpec unsigned int bitWidth; unsigned int NumberOfBankGroups; - // Memspec Variables: + // Clock double clkMHz; sc_time clk; - sc_time tCKE; // min time in pdna or pdnp - sc_time tCKESR; // min time in sref - sc_time tRAS; // active-time (act -> pre same bank) - sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) - sc_time tRCD; // act -> read/write - sc_time tRL; // read latency (read command start to data strobe) - sc_time tRTP; // read to precharge - sc_time tWL; // write latency - sc_time tWR; // write recovery (write to precharge) - sc_time tXP; // min delay to row access command after pdnpx pdnax - sc_time tXS; // min delay to row access command after srefx - sc_time tREFI; - sc_time tRFC; - sc_time tRP; - // only used in DRAMPower - sc_time tDQSCK; // Currents and Voltages: double iDD0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp new file mode 100644 index 00000000..211dff12 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecDDR3.h" + +sc_time MemSpecDDR3::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecDDR3::getRefreshIntervalSB() const +{ + SC_REPORT_FATAL("MemSpecDDR3", "Per bank refresh not supported"); + return SC_ZERO_TIME; +} + +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecDDR3::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD || command == Command::RDA) + return tRL + getReadAccessTime(); +// else if (command == Command::RDA) +// // TODO: this time is wrong (controller internally waits for tRAS) +// return tRTP + tRP; + else if (command == Command::WR || command == Command::WRA) + return tWL + getWriteAccessTime(); +// else if (command == Command::WRA) +// return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFC; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 4589288a..dab0eb87 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -40,6 +40,22 @@ struct MemSpecDDR3 : public MemSpec { + // Memspec Variables: + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; sc_time tCCD; sc_time tFAW; sc_time tRRD; @@ -52,6 +68,12 @@ struct MemSpecDDR3 : public MemSpec double iDD2P1; double iDD3P0; double iDD3P1; + + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalSB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp new file mode 100644 index 00000000..892983cb --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecDDR4.h" + +sc_time MemSpecDDR4::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecDDR4::getRefreshIntervalSB() const +{ + SC_REPORT_FATAL("MemSpecDDR4", "Per bank refresh not supported"); + return SC_ZERO_TIME; +} + +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecDDR4::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD) + return tRL + getReadAccessTime(); + else if (command == Command::RDA) + // this time is wrong (controller internally waits for tRAS) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFC; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 5df15101..f7056339 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -40,6 +40,22 @@ struct MemSpecDDR4 : public MemSpec { + // Memspec Variables: + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; sc_time tCCD_S; sc_time tCCD_L; sc_time tFAW; @@ -58,6 +74,12 @@ struct MemSpecDDR4 : public MemSpec double iDD3P1; double iDD62; double vDD2; + + sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index c6a37e7e..12566856 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -35,28 +35,51 @@ #include "MemSpecLPDDR4.h" +MemSpecLPDDR4::MemSpecLPDDR4() +{ + clACT = 4; + clPRE = 2; + clPREA = 2; + clRD = 4; + clRDA = 4; + clWR = 4; + clWRA = 4; + clREFA = 2; + clREFB = 2; + clSREFEN = 2; + clSREFEX = 2; +} + +sc_time MemSpecLPDDR4::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecLPDDR4::getRefreshIntervalSB() const +{ + return tREFIpb; +} + sc_time MemSpecLPDDR4::getExecutionTime(Command command) const { if (command == Command::PRE) - return tRP; + return tRPpb + clk; else if (command == Command::PREA) - return tRPAB; + return tRPab + clk; else if (command == Command::ACT) - return tRCD; + return tRCD + 3 * clk; else if (command == Command::RD) - return tRL + getReadAccessTime(); + return tRL + tDQSCK + getReadAccessTime() + 3 * clk; else if (command == Command::RDA) - return tRTP + tRP; + return getReadAccessTime() - 5 * clk + tRTP + tRPpb; else if (command == Command::WR) - return tWL + getWriteAccessTime(); + return tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk; else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; + return tWL + getWriteAccessTime() + 4 * clk + tWR + tRPpb; else if (command == Command::REFA) - return tRFC; + return tRFCab + clk; else if (command == Command::REFB) - return tRFCPB; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; + return tRFCpb + clk; else { SC_REPORT_FATAL("getExecutionTime", @@ -68,11 +91,11 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command) const TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK /*+ DQSQ*/, - sc_time_stamp() + tRL + tDQSCK /*+ DQSQ*/ + getReadAccessTime()); + return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * clk, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime() + 3 * clk); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL /*+ tDQSS + tDQS2DQ*/, - sc_time_stamp() + tWL /*+ tDQSS + tDQS2DQ*/ + getWriteAccessTime()); + return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * clk, + sc_time_stamp() + tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk); else { SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 65b857c2..17edc1a0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -40,16 +40,35 @@ struct MemSpecLPDDR4 : public MemSpec { - sc_time tCCD; - sc_time tCCDMW; - sc_time tESCKE; - sc_time tFAW; - sc_time tWTR; + // Memspec Variables: + sc_time tREFI; + sc_time tREFIpb; + sc_time tRFCab; + sc_time tRFCpb; + sc_time tRPab; + sc_time tRPpb; sc_time tPPD; - sc_time tREFIPB; - sc_time tRFCPB; - sc_time tRPAB; + sc_time tRAS; + sc_time tRCD; + sc_time tFAW; sc_time tRRD; + sc_time tCCD; + sc_time tRL; + sc_time tRPST; + sc_time tDQSCK; + sc_time tRTP; + sc_time tWL; + sc_time tDQSS; + sc_time tDQS2DQ; + sc_time tWR; + sc_time tWPRE; + sc_time tWTR; + sc_time tXP; + sc_time tSR; + sc_time tXSR; + sc_time tESCKE; + sc_time tCKE; + sc_time tCMDCKE; double iDD02; double iDD2P0; @@ -59,6 +78,11 @@ struct MemSpecLPDDR4 : public MemSpec double iDD62; double vDD2; + MemSpecLPDDR4(); + + sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getExecutionTime(Command) const override; TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp new file mode 100644 index 00000000..406b2c0a --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecWideIO.h" + +sc_time MemSpecWideIO::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecWideIO::getRefreshIntervalSB() const +{ + SC_REPORT_FATAL("MemSpecWideIO", "Per bank refresh not supported"); + return SC_ZERO_TIME; +} + +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecWideIO::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD) + return tRL + getReadAccessTime(); + else if (command == Command::RDA) + // this time is wrong (controller internally waits for tRAS) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFC; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index fd9f1cc5..35fc6b2b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -40,6 +40,22 @@ struct MemSpecWideIO : public MemSpec { + // Memspec Variables: + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; sc_time tCCD; sc_time tRRD; sc_time tTAW; @@ -61,6 +77,12 @@ struct MemSpecWideIO : public MemSpec double iDD52; double iDD62; double vDD2; + + sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp deleted file mode 100644 index c9950e9a..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#include "ScheduledCommand.h" -#include "../../../common/timingCalculations.h" -#include "../../../common/utils.h" -#include "../../../configuration/Configuration.h" - -bool ScheduledCommand::isNoCommand() const -{ - return (command == Command::NOP && start == SC_ZERO_TIME - && executionTime == SC_ZERO_TIME && end == SC_ZERO_TIME); -} - -bool ScheduledCommand::isValidCommand() const -{ - return !isNoCommand(); -} - -const sc_time ScheduledCommand::getStart() const -{ - return start; -} - -void ScheduledCommand::setStart(sc_time newStart) -{ - start = newStart; - end = newStart + executionTime; -} - -void ScheduledCommand::delayStart(sc_time delay) -{ - setStart(start + delay); -} - -// Delays the command so that its start is at least value(constraint) from timepoint previous apart. -// If passed a constraint of 0ns, method will make sure that command starts no earlier than at timepoint previous -void ScheduledCommand::establishMinDistanceFromStart(sc_time previous, - sc_time constraint) -{ - delayStart(getDelayToMeetConstraint(previous, start, constraint)); -} - -sc_time ScheduledCommand::getEnd() const -{ - return end; -} - -Command ScheduledCommand::getCommand() const -{ - return command; -} - -sc_time ScheduledCommand::getExecutionTime() const -{ - return executionTime; -} - -Rank ScheduledCommand::getRank() const -{ - return extension.getRank(); -} - -Bank ScheduledCommand::getBank() const -{ - return extension.getBank(); -} - -BankGroup ScheduledCommand::getBankGroup() const -{ - return extension.getBankGroup(); -} - -Row ScheduledCommand::getRow() const -{ - return extension.getRow(); -} - -unsigned int ScheduledCommand::getBurstLength() const -{ - return extension.getBurstlength(); -} - -bool ScheduledCommand::operator ==(const ScheduledCommand &b) const -{ - return b.command == command && b.start == start - && b.executionTime == executionTime && b.end == end; -} - -bool ScheduledCommand::commandIsIn(const std::vector &commandSet) const -{ - return isIn(command, commandSet); -} - -TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const -{ - //only read and write commands have an assoicated time on the data strobe - sc_assert(getCommand() == Command::RD || getCommand() == Command::RDA - || getCommand() == Command::WR - || getCommand() == Command::WRA); - - MemSpec *timings = Configuration::getInstance().memSpec; - - if (getCommand() == Command::RD || getCommand() == Command::RDA) { - return TimeInterval(getStart() + timings->tRL, - getStart() + timings->tRL + timings->getReadAccessTime()); - } else { - return TimeInterval(getStart() + timings->tWL - timings->clk / 2, - getStart() + timings->tWL + timings->getWriteAccessTime() - - timings->clk / 2); - } -} diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h deleted file mode 100644 index 9dde8bfb..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef SCHEDULEDCOMMAND_H -#define SCHEDULEDCOMMAND_H - -#include -#include -#include "../../Command.h" -#include "../../../common/dramExtensions.h" -#include "../../../common/utils.h" - -class ScheduledCommand -{ -public: - ScheduledCommand(Command command, sc_time start, sc_time executionTime, - const DramExtension &extension) : - command(command), start(start), executionTime(executionTime), - end(start + executionTime), extension(extension) {} - - ScheduledCommand(Command command, sc_time start, sc_time executionTime, - const tlm::tlm_generic_payload &payload) : - ScheduledCommand(command, start, executionTime, - DramExtension::getExtension(payload)) {} - - ScheduledCommand() : - command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), - end(SC_ZERO_TIME), extension() {} - - bool isNoCommand() const; - bool isValidCommand() const; - - const sc_time getStart() const; - void setStart(sc_time newStart); - void delayStart(sc_time delay); - void establishMinDistanceFromStart(sc_time previous, sc_time constraint); - - sc_time getEnd() const; - Command getCommand() const; - sc_time getExecutionTime() const; - - Rank getRank() const; - Bank getBank() const; - BankGroup getBankGroup() const; - Row getRow() const; - - unsigned int getBurstLength() const; - bool operator ==(const ScheduledCommand &b) const; - bool commandIsIn(const std::vector &commandSet) const; - - TimeInterval getIntervalOnDataStrobe() const; - -private: - Command command; - sc_time start; - sc_time executionTime; - sc_time end; - DramExtension extension; -}; - -#endif // SCHEDULEDCOMMAND_H - diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index ce63d093..1dad68de 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -41,7 +41,7 @@ RefreshManager::RefreshManager(std::vector &bankMachines) : bankM { memSpec = Configuration::getInstance().memSpec; setUpDummy(refreshPayload); - timeForNextTrigger = memSpec->tREFI - memSpec->getExecutionTime(Command::PREA); + timeForNextTrigger = memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA); } std::pair RefreshManager::getNextCommand() @@ -63,7 +63,7 @@ std::pair RefreshManager::getNextCommand() else { state = RmState::IDLE; - timeForNextTrigger += (memSpec->tREFI - memSpec->getExecutionTime(Command::PREA)); + timeForNextTrigger += (memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA)); return std::pair(Command::REFA, &refreshPayload); } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 59a45813..6ebd7d16 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -42,8 +42,8 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM { memSpec = Configuration::getInstance().memSpec; // TODO: implement for multiple ranks - sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + sc_time currentREFB = memSpec->getRefreshIntervalSB() - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->getExecutionTime(Command::PRE)); timeForNextTrigger = currentPRE; refreshPayloads = std::vector(memSpec->NumberOfBanks); @@ -65,7 +65,7 @@ std::pair RefreshManagerBankwise::getNextCommand auto it = triggerTimes.begin(); Bank bank = it->second; triggerTimes.erase(it); - triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->tREFI, bank)); + triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->getRefreshIntervalSB(), bank)); timeForNextTrigger = triggerTimes.begin()->first; if (states[bank.ID()] == RmState::IDLE) { diff --git a/DRAMSys/library/src/simulation/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/DramLPDDR4.cpp new file mode 100644 index 00000000..3041d406 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramLPDDR4.cpp @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramLPDDR4.h" + +#include "../configuration/memspec/MemSpecLPDDR4.h" + +DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4"); + + // Parameters for DRAMPower + MemSpecLPDDR4 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramLPDDR4", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + { + SC_REPORT_FATAL("DramLPDDR4", "DRAMPower not supported for LPDDR4"); + } + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/DramLPDDR4.h b/DRAMSys/library/src/simulation/DramLPDDR4.h new file mode 100644 index 00000000..4377ec56 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramLPDDR4.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMLPDDR4_H +#define DRAMLPDDR4_H + +#include +#include +#include "Dram.h" + +class DramLPDDR4 : public Dram +{ +public: + DramLPDDR4(sc_module_name); + SC_HAS_PROCESS(DramLPDDR4); + virtual ~DramLPDDR4() {} +}; + +#endif // DRAMLPDDR4_H