diff --git a/dram/resources/configs/memconfigs/memconfig.xml b/dram/resources/configs/memconfigs/memconfig.xml index b708be0d..ba84ec9e 100644 --- a/dram/resources/configs/memconfigs/memconfig.xml +++ b/dram/resources/configs/memconfigs/memconfig.xml @@ -1,12 +1,11 @@ - + - - + + - - + diff --git a/dram/resources/configs/memspecs/MatzesWideIO.xml b/dram/resources/configs/memspecs/MatzesWideIO.xml index 12f75921..57599053 100644 --- a/dram/resources/configs/memspecs/MatzesWideIO.xml +++ b/dram/resources/configs/memspecs/MatzesWideIO.xml @@ -28,7 +28,7 @@ - + diff --git a/dram/src/common/dramExtension.cpp b/dram/src/common/dramExtension.cpp index 61d24fb4..591ec8ab 100644 --- a/dram/src/common/dramExtension.cpp +++ b/dram/src/common/dramExtension.cpp @@ -6,7 +6,7 @@ using namespace tlm; /* Static methods * */ -const DramExtension& DramExtension::getExtension(const tlm_generic_payload *payload) +DramExtension& DramExtension::getExtension(const tlm_generic_payload *payload) { DramExtension *result = NULL; payload->get_extension(result); @@ -14,7 +14,7 @@ const DramExtension& DramExtension::getExtension(const tlm_generic_payload *payl return *result; } -const DramExtension& DramExtension::getExtension(const tlm_generic_payload &payload) +DramExtension& DramExtension::getExtension(const tlm_generic_payload &payload) { return DramExtension::getExtension(&payload); } diff --git a/dram/src/common/dramExtension.h b/dram/src/common/dramExtension.h index d515be44..9bbf4b04 100644 --- a/dram/src/common/dramExtension.h +++ b/dram/src/common/dramExtension.h @@ -135,9 +135,10 @@ public: const Column& getColumn() const{return column;} const unsigned int getBurstlength() const{return burstlength;} + void setRow(const Row& row){this->row = row;} - static const DramExtension& getExtension(const tlm::tlm_generic_payload *payload); - static const DramExtension& getExtension(const tlm::tlm_generic_payload &payload); + static DramExtension& getExtension(const tlm::tlm_generic_payload *payload); + static DramExtension& getExtension(const tlm::tlm_generic_payload &payload); }; #endif /* DRAMEXTENSION_H_ */ diff --git a/dram/src/core/BankStates.cpp b/dram/src/core/BankStates.cpp index b89136f1..d125bbe5 100644 --- a/dram/src/core/BankStates.cpp +++ b/dram/src/core/BankStates.cpp @@ -8,14 +8,14 @@ #include "BankStates.h" #include "ControllerCore.h" #include "../common/DebugManager.h" +#include "../common/Utils.h" using namespace std; namespace core { -BankStates::BankStates(unsigned int numberOfBanks) : - rowsInRowBuffers(numberOfBanks) +BankStates::BankStates() { closeAllRowBuffers(); } @@ -26,31 +26,31 @@ BankStates::~BankStates() bool BankStates::rowBufferIsOpen(const Bank &bank) const { - return rowsInRowBuffers.at(bank.ID()) != Row::NO_ROW; + return rowsInRowBuffers.at(bank) != Row::NO_ROW; } Row BankStates::getRowInRowBuffer(const Bank &bank) const { - return rowsInRowBuffers.at(bank.ID()); + return rowsInRowBuffers.at(bank); } void BankStates::openRowInRowBuffer(const Bank &bank, const Row &row) { DebugManager::getInstance().printDebugMessage(ControllerCore::senderName, "Row buffer for bank " + to_string(bank.ID()) + " is now open"); - rowsInRowBuffers.at(bank.ID()) = row; + rowsInRowBuffers[bank] = row; } void BankStates::closeRowBuffer(const Bank &bank) { DebugManager::getInstance().printDebugMessage(ControllerCore::senderName, "Row buffer for bank " + to_string(bank.ID()) + " is now closed"); - rowsInRowBuffers.at(bank.ID()) = Row::NO_ROW; + rowsInRowBuffers[bank] = Row::NO_ROW; } bool BankStates::allRowBuffersAreClosed() const { - for(auto row : rowsInRowBuffers) + for(unsigned int i=0; i +#include #include "../common/dramExtension.h" namespace core @@ -15,7 +15,7 @@ namespace core class BankStates { public: - BankStates(unsigned int numberOfBanks); + BankStates(); virtual ~BankStates(); bool rowBufferIsOpen(const Bank &bank) const; @@ -27,7 +27,7 @@ public: void closeAllRowBuffers(); private: - std::vector rowsInRowBuffers; + std::map rowsInRowBuffers; }; } diff --git a/dram/src/core/ControllerState.h b/dram/src/core/ControllerState.h index 4a896cad..63eebea2 100644 --- a/dram/src/core/ControllerState.h +++ b/dram/src/core/ControllerState.h @@ -24,7 +24,7 @@ class ControllerState { public: ControllerState(Configuration* config) : - bankStates(config->NumberOfBanks), bus(config->Timings.clk), config(config) + bankStates(), bus(config->Timings.clk), config(config) { } virtual ~ControllerState() diff --git a/dram/src/core/refresh/RefreshManager.cpp b/dram/src/core/refresh/RefreshManager.cpp index e88891af..837a808e 100644 --- a/dram/src/core/refresh/RefreshManager.cpp +++ b/dram/src/core/refresh/RefreshManager.cpp @@ -58,10 +58,13 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time } for (tlm::tlm_generic_payload& payload : refreshPayloads) { + Row currentrow = DramExtension::getExtension(payload).getRow(); + DramExtension::getExtension(payload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks)); ScheduledCommand refreshToSend(Command::AutoRefresh, nextRefresh.getStart(), timing.tRFC, DramExtension::getExtension(payload)); controller.state.change(refreshToSend); controller.wrapper.send(refreshToSend, payload); + } planNextRefresh(); diff --git a/dram/src/core/refresh/RefreshManagerBankwise.cpp b/dram/src/core/refresh/RefreshManagerBankwise.cpp index fae2c8eb..563a628e 100644 --- a/dram/src/core/refresh/RefreshManagerBankwise.cpp +++ b/dram/src/core/refresh/RefreshManagerBankwise.cpp @@ -88,6 +88,8 @@ void RefreshManagerBankwise::RefreshManagerForBank::scheduleRefresh(sc_time time } controller.state.bus.moveCommandToNextFreeSlot(nextRefresh); controller.state.change(nextRefresh); + Row currentrow = DramExtension::getExtension(refreshPayload).getRow(); + DramExtension::getExtension(refreshPayload).setRow(Row((currentrow.ID()+1)%Configuration::getInstance().NumberOfBanks)); controller.wrapper.send(nextRefresh, refreshPayload); planNextRefresh(); diff --git a/dram/src/core/utils/Utils.cpp b/dram/src/core/utils/Utils.cpp index aa49010b..2b19f0e1 100644 --- a/dram/src/core/utils/Utils.cpp +++ b/dram/src/core/utils/Utils.cpp @@ -49,8 +49,7 @@ TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command) } else { - //centered data strobe for write - return TimeInterval(command.getStart() + timings.tWL, command.getStart() + timings.tWL + timings.clk * (command.getBurstLength()-1)); + return TimeInterval(command.getStart() + timings.tWL, command.getStart() + timings.tWL + timings.clk * command.getBurstLength()); } } diff --git a/dram/src/scheduler/Fifo.h b/dram/src/scheduler/Fifo.h index 94689c96..c1f17689 100644 --- a/dram/src/scheduler/Fifo.h +++ b/dram/src/scheduler/Fifo.h @@ -19,7 +19,7 @@ namespace scheduler { class Fifo : public Scheduler { public: - Fifo(const core::ControllerCore& controller) + Fifo() {} virtual ~Fifo() {} diff --git a/dram/src/scheduler/Fr_Fcfs.cpp b/dram/src/scheduler/Fr_Fcfs.cpp index 39af487b..4bdfd740 100644 --- a/dram/src/scheduler/Fr_Fcfs.cpp +++ b/dram/src/scheduler/Fr_Fcfs.cpp @@ -8,6 +8,16 @@ using namespace core; namespace scheduler { +FR_FCFS::FR_FCFS(core::ControllerCore& controller, bool refreshAware, bool adaptiveOpenPage) : + controllerBankstates(controller.state.bankStates), refreshAware(refreshAware), adaptiveOpenPage( + adaptiveOpenPage) +{ +} + +FR_FCFS::~FR_FCFS() +{ +} + bool FR_FCFS::hasTransactionForBank(Bank bank) { return !buffer[bank].empty(); @@ -22,16 +32,19 @@ gp* FR_FCFS::getTransactionForBank(Bank bank) { sc_assert(hasTransactionForBank(bank)); - auto rowHits = findRowHits(bank, bankstates.getRowInRowBuffer(bank)); + Row openRowOnBank = (refreshAware) ? controllerBankstates.getRowInRowBuffer(bank) : internalBankstates.getRowInRowBuffer(bank); + auto rowHits = findRowHits(bank, openRowOnBank); gp* result = rowHits.empty() ? buffer[bank].front() : rowHits.front(); - rowHits = findRowHits(bank, DramExtension::getExtension(result).getRow()); - if (!core::Configuration::getInstance().AdaptiveOpenPagePolicy) + if (!adaptiveOpenPage) + { return result; - + } else { - if(rowHits.size() > 1) + rowHits = findRowHits(bank, DramExtension::getExtension(result).getRow()); + //other row hits are still in buffer, leave page open + if (rowHits.size() > 1) Configuration::getInstance().OpenPagePolicy = true; else Configuration::getInstance().OpenPagePolicy = false; @@ -42,7 +55,7 @@ gp* FR_FCFS::getTransactionForBank(Bank bank) // else // Configuration::getInstance().OpenPagePolicy = false; - //no other hit in buffer, but row miss is waiting +//no other hit in buffer, but row miss is waiting // if(findRowHits(bank,DramExtension::getExtension(result).getRow()).size() == 1 && buffer[bank].size() > 2 ) // Configuration::getInstance().OpenPagePolicy = false; // else @@ -65,9 +78,14 @@ std::vector FR_FCFS::findRowHits(Bank bank, Row row) void FR_FCFS::popTransactionForBank(Bank bank, gp* payload) { - sc_assert(hasTransactionForBank(bank)); - + sc_assert( + hasTransactionForBank(bank) && bank == DramExtension::getExtension(payload).getBank()); buffer[bank].remove(payload); + + if (!refreshAware) + { + internalBankstates.openRowInRowBuffer(bank, DramExtension::getExtension(payload).getRow()); + } } } diff --git a/dram/src/scheduler/Fr_Fcfs.h b/dram/src/scheduler/Fr_Fcfs.h index b6e25790..f8473ee1 100644 --- a/dram/src/scheduler/Fr_Fcfs.h +++ b/dram/src/scheduler/Fr_Fcfs.h @@ -11,10 +11,8 @@ namespace scheduler { class FR_FCFS : public Scheduler { public: - FR_FCFS(core::ControllerCore& controller) : bankstates(controller.getBankStates()) - {} - virtual ~FR_FCFS() - {} + FR_FCFS(core::ControllerCore& controller,bool refreshAware, bool adaptiveOpenPage); + virtual ~FR_FCFS(); virtual bool hasTransactionForBank(Bank bank) override; virtual void schedule(gp* payload) override; @@ -24,7 +22,10 @@ public: private: std::vector findRowHits(Bank bank, Row row); std::map> buffer; - const core::BankStates& bankstates; + const core::BankStates& controllerBankstates; + core::BankStates internalBankstates; + bool refreshAware; + bool adaptiveOpenPage; }; } /* namespace scheduler */ diff --git a/dram/src/simulation/Controller.h b/dram/src/simulation/Controller.h index 41aa6536..d342a4ef 100644 --- a/dram/src/simulation/Controller.h +++ b/dram/src/simulation/Controller.h @@ -46,7 +46,7 @@ public: &Controller::controllerPEQCallback), debugManager(DebugManager::getInstance()) { controller = new ControllerCore(*this, numberOfPayloadsInSystem); - scheduler = new FR_FCFS(*controller); + buildScheduler(); inputBufferDelay = controller->config.Timings.clk; iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw); tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw); @@ -58,6 +58,17 @@ public: delete scheduler; } + void buildScheduler() + { + string selectedScheduler = Configuration::getInstance().Scheduler; + if(selectedScheduler == "FR_FCFS") + scheduler = new FR_FCFS(*controller,Configuration::getInstance().RefreshAwareScheduling,Configuration::getInstance().AdaptiveOpenPagePolicy); + else if(selectedScheduler == "FIFO") + scheduler = new Fifo(); + else + reportFatal(name(),"unsupporeted scheduler: " + selectedScheduler); + } + void terminateSimulation() { for (Bank bank : controller->getBanks()) diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index 06c32480..9c9dd974 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -17,16 +17,21 @@ using namespace std; namespace simulation { -SimulationManager::SimulationManager(sc_module_name name, std::string stl1, - unsigned int burstlength1, std::string stl2, unsigned int burstlenght2, - std::string traceName, std::string pathToResources, bool silent) : +SimulationManager::SimulationManager(sc_module_name name, string memconfig, string memspec, + string stl1, unsigned int burstlength1, string stl2, + unsigned int burstlenght2, string traceName, string pathToResources, + bool silent) : dram("dram"), arbiter("arbiter"), controller("controller"), player1("player1", pathToResources + string("traces/") + stl1,burstlength1, this), player2("player2", pathToResources + string("traces/") + stl2,burstlenght2, this), traceName(traceName) { - SC_THREAD(terminationThread); + + cout << pathToResources + string("configs/memconfigs/") + memconfig << endl; + cout << pathToResources + string("configs/memspecs/") + memspec << endl; + + xmlAddressDecoder::addressConfigURI = pathToResources + string("configs/addressConfig.xml"); TlmRecorder::dbName = traceName; TlmRecorder::sqlScriptURI = pathToResources + string("scripts/createTraceDB.sql"); @@ -89,4 +94,6 @@ void SimulationManager::terminationThread() sc_stop(); } + + } /* namespace simulation */ diff --git a/dram/src/simulation/SimulationManager.h b/dram/src/simulation/SimulationManager.h index ddfee8f2..c1bb1a3f 100644 --- a/dram/src/simulation/SimulationManager.h +++ b/dram/src/simulation/SimulationManager.h @@ -18,13 +18,14 @@ namespace simulation { -class SimulationManager : public ISimulationManager, public sc_module +class SimulationManager: public ISimulationManager, public sc_module { public: SC_HAS_PROCESS(SimulationManager); - SimulationManager(sc_module_name name, std::string stl1, - unsigned int burstlength1, std::string stl2, unsigned int burstlenght2, - std::string traceName, std::string pathToResources, bool silent=false); + SimulationManager(sc_module_name name, std::string memconfig, std::string memspec, + std::string stl1, unsigned int burstlength1, std::string stl2, + unsigned int burstlenght2, std::string traceName, std::string pathToResources, + bool silent = false); void startSimulation(); void tracePlayerFinishedCallback(string name) override; @@ -34,7 +35,7 @@ private: constexpr static unsigned int numberOfTracePlayers = 2; std::string traceName; Dram<> dram; - Arbiter arbiter; + Arbiter arbiter; Controller<> controller; TracePlayer<> player1; TracePlayer<> player2; diff --git a/dram/src/simulation/main.cpp b/dram/src/simulation/main.cpp index c2ff4eda..e7036cdd 100644 --- a/dram/src/simulation/main.cpp +++ b/dram/src/simulation/main.cpp @@ -30,16 +30,24 @@ int sc_main(int argc, char **argv) sc_set_time_resolution(1, SC_PS); - Configuration::memspecUri = "/home/jonny/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml"; - Configuration::memconfigUri = "/home/jonny/git/dram/dram/resources/configs/memconfigs/memconfig.xml"; string resources = pathOfFile(argv[0]) + string("/../resources/"); + + string memconfig = "memconfig.xml"; + string memspec = "MatzesWideIO.xml"; string stl1 = "chstone-sha_32.stl"; unsigned int burstlength1 = 4; - string stl2 = "empty.stl"; - unsigned int burstlength2 = 2; - string traceName = "tpr.tdb"; - SimulationManager simulationManager("sim", stl1,burstlength1, stl2,burstlength2, traceName, resources,false); + string stl2 = "mediabench-h263decode_32.stl"; + unsigned int burstlength2 = 4; + string traceName = "unaware_long.tdb"; + + Configuration::memspecUri = "/home/robert/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml"; + Configuration::memconfigUri = "/home/robert/git/dram/dram/resources/configs/memconfigs/memconfig.xml"; + +// Configuration::memconfigUri = resources + string("configs/memconfigs/") + memconfig; +// Configuration::memconfigUri = resources + string("configs/memspecs/") + memspec; + + SimulationManager simulationManager("sim",memconfig,memspec,stl1,burstlength1, stl2,burstlength2, traceName, resources,false); simulationManager.startSimulation(); startTraceAnalyzer(traceName); return 0;