diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index e43b84a8..31729d23 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -47,90 +47,122 @@ set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") include_directories( - src/simulation - src/simulation/dram - src/controller - src/controller/checker - src/controller/cmdmux - src/controller/powerdown - src/controller/refresh - src/controller/scheduler - src/common - src/common/third_party/DRAMPower/src - src/configuration - src/configuration/memspec - src/error - src/error/ECC + src/common + src/common/third_party/DRAMPower/src + src/configuration + src/configuration/memspec + src/controller + src/controller/checker + src/controller/cmdmux + src/controller/powerdown + src/controller/refresh + src/controller/respqueue + src/controller/scheduler + src/error + src/error/ECC + src/simulation + src/simulation/dram ) add_library(DRAMSysLibrary - src/common/third_party/tinyxml2/tinyxml2.cpp - src/common/TlmRecorder.cpp - src/common/DebugManager.cpp - src/configuration/Configuration.cpp - src/simulation/MemoryManager.cpp - src/simulation/TemperatureController.cpp - src/configuration/ConfigurationLoader.cpp - src/controller/Command.cpp - src/error/errormodel.cpp - src/simulation/TracePlayer.cpp - src/simulation/TraceSetup.cpp - src/simulation/DRAMSys.cpp - src/simulation/Setup.cpp - src/error/ECC/Bit.cpp - src/error/ECC/ECC.cpp - src/error/ECC/Word.cpp - src/error/eccbaseclass.cpp - src/error/ecchamming.cpp - src/common/AddressDecoder.cpp - src/simulation/dram/Dram.cpp - src/simulation/Arbiter.cpp - src/common/CongenAddressDecoder.cpp - src/common/XmlAddressDecoder.cpp - src/common/timingCalculations.cpp - src/common/dramExtensions.cpp - src/common/utils.cpp - src/simulation/dram/DramDDR3.cpp - src/simulation/dram/DramDDR4.cpp - src/simulation/dram/DramRecordable.cpp - src/simulation/dram/DramWideIO.cpp - src/configuration/memspec/MemSpec.cpp - src/controller/BankMachine.cpp - src/controller/Controller.cpp - src/controller/scheduler/SchedulerFifo.cpp - src/controller/scheduler/SchedulerFrFcfs.cpp - src/controller/cmdmux/CmdMuxStrict.cpp - src/controller/cmdmux/CmdMuxOldest.cpp - src/controller/ControllerRecordable.cpp - src/controller/checker/CheckerDDR3.cpp - src/controller/refresh/RefreshManager.cpp - src/controller/refresh/RefreshManagerDummy.cpp - src/controller/refresh/RefreshManagerBankwise.cpp - src/controller/checker/CheckerWideIO.cpp - src/configuration/memspec/MemSpecDDR3.cpp - src/configuration/memspec/MemSpecDDR4.cpp - src/configuration/memspec/MemSpecWideIO.cpp - src/configuration/memspec/MemSpecLPDDR4.cpp - src/controller/checker/CheckerDDR4.cpp - src/simulation/dram/DramLPDDR4.cpp - src/controller/checker/CheckerLPDDR4.cpp - src/configuration/memspec/MemSpecWideIO2.cpp - src/simulation/dram/DramWideIO2.cpp - src/controller/checker/CheckerWideIO2.cpp - src/configuration/memspec/MemSpecHBM2.cpp - src/simulation/dram/DramHBM2.cpp - src/controller/checker/CheckerHBM2.cpp - src/configuration/memspec/MemSpecGDDR5.cpp - src/configuration/memspec/MemSpecGDDR5X.cpp - src/configuration/memspec/MemSpecGDDR6.cpp - src/controller/checker/CheckerGDDR5.cpp - src/controller/checker/CheckerGDDR5X.cpp - src/controller/checker/CheckerGDDR6.cpp - src/simulation/dram/DramGDDR5.cpp - src/simulation/dram/DramGDDR5X.cpp - src/simulation/dram/DramGDDR6.cpp - src/controller/powerdown/PowerDownManagerStaggered.cpp - src/controller/powerdown/PowerDownManagerDummy.cpp + src/common/AddressDecoder.cpp + src/common/CongenAddressDecoder.cpp + src/common/DebugManager.cpp + src/common/dramExtensions.cpp + src/common/tlm2_base_protocol_checker.h + src/common/TlmRecorder.cpp + src/common/utils.cpp + src/common/XmlAddressDecoder.cpp + src/common/third_party/tinyxml2/tinyxml2.cpp + + src/configuration/Configuration.cpp + src/configuration/ConfigurationLoader.cpp + src/configuration/TemperatureSimConfig.h + + src/configuration/memspec/MemSpec.cpp + src/configuration/memspec/MemSpecDDR3.cpp + src/configuration/memspec/MemSpecDDR4.cpp + src/configuration/memspec/MemSpecLPDDR4.cpp + src/configuration/memspec/MemSpecWideIO.cpp + src/configuration/memspec/MemSpecWideIO2.cpp + src/configuration/memspec/MemSpecGDDR5.cpp + src/configuration/memspec/MemSpecGDDR5X.cpp + src/configuration/memspec/MemSpecGDDR6.cpp + src/configuration/memspec/MemSpecHBM2.cpp + + src/controller/BankMachine.cpp + src/controller/Command.cpp + src/controller/ControllerIF.h + src/controller/Controller.cpp + src/controller/ControllerRecordable.cpp + + src/controller/checker/CheckerIF.h + src/controller/checker/CheckerDDR3.cpp + src/controller/checker/CheckerDDR4.cpp + src/controller/checker/CheckerLPDDR4.cpp + src/controller/checker/CheckerWideIO.cpp + src/controller/checker/CheckerWideIO2.cpp + src/controller/checker/CheckerGDDR5.cpp + src/controller/checker/CheckerGDDR5X.cpp + src/controller/checker/CheckerGDDR6.cpp + src/controller/checker/CheckerHBM2.cpp + + src/controller/cmdmux/CmdMuxIF.h + src/controller/cmdmux/CmdMuxOldest.cpp + src/controller/cmdmux/CmdMuxStrict.cpp + + src/controller/powerdown/PowerDownManagerIF.h + src/controller/powerdown/PowerDownManagerDummy.cpp + src/controller/powerdown/PowerDownManagerStaggered.cpp + + src/controller/refresh/RefreshManagerIF.h + src/controller/refresh/RefreshManagerDummy.cpp + src/controller/refresh/RefreshManagerRankwise.cpp + src/controller/refresh/RefreshManagerBankwise.cpp + + src/controller/respqueue/RespQueueIF.h + src/controller/respqueue/RespQueueFifo.cpp + src/controller/respqueue/RespQueueReorder.cpp + + src/controller/scheduler/SchedulerIF.h + src/controller/scheduler/SchedulerFifo.cpp + src/controller/scheduler/SchedulerFrFcfs.cpp + src/controller/scheduler/SchedulerFrFcfsGrp.cpp + + src/error/eccbaseclass.cpp + src/error/ecchamming.cpp + src/error/errormodel.cpp + + src/error/ECC/Bit.cpp + src/error/ECC/ECC.cpp + src/error/ECC/Word.cpp + + src/simulation/Arbiter.cpp + src/simulation/DRAMSys.cpp + src/simulation/ExampleInitiator.h + src/simulation/IArbiter.h + src/simulation/MemoryManager.cpp + src/simulation/ReorderBuffer.h + src/simulation/Setup.cpp + src/simulation/SimpleArbiter.h + src/simulation/StlPlayer.h + src/simulation/TemperatureController.cpp + src/simulation/TraceGenerator.h + src/simulation/TracePlayer.cpp + src/simulation/TracePlayerListener.h + src/simulation/TraceSetup.cpp + + src/simulation/dram/Dram.cpp + src/simulation/dram/DramRecordable.cpp + src/simulation/dram/DramDDR3.cpp + src/simulation/dram/DramDDR4.cpp + src/simulation/dram/DramLPDDR4.cpp + src/simulation/dram/DramWideIO.cpp + src/simulation/dram/DramWideIO2.cpp + src/simulation/dram/DramGDDR5.cpp + src/simulation/dram/DramGDDR5X.cpp + src/simulation/dram/DramGDDR6.cpp + src/simulation/dram/DramHBM2.cpp ) # Build: diff --git a/DRAMSys/library/resources/configs/mcconfigs/.gitignore b/DRAMSys/library/resources/configs/mcconfigs/.gitignore deleted file mode 100644 index c5a87587..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/.gitignore +++ /dev/null @@ -1 +0,0 @@ -memconfig.xml \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml index fc05a577..629ad725 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml @@ -1,43 +1,20 @@ - - + + + - - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index 1226d09a..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,44 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml deleted file mode 100644 index fc05a577..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml index 35e118dc..dada4e70 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml @@ -1,44 +1,20 @@ - - - + + + - - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml deleted file mode 100644 index d92d32da..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml deleted file mode 100644 index d4aa4a4c..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml index 042cc5fb..06104618 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml @@ -1,43 +1,20 @@ - - + + + - - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml deleted file mode 100644 index 7cb5befd..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml +++ /dev/null @@ -1,38 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml deleted file mode 100644 index aa65b3ff..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml deleted file mode 100644 index 4c0b43c6..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/grp.xml b/DRAMSys/library/resources/configs/mcconfigs/grp.xml deleted file mode 100644 index 8b34759d..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/grp.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml deleted file mode 100644 index aaec39ca..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml deleted file mode 100644 index 2f8fb337..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/sms.xml b/DRAMSys/library/resources/configs/mcconfigs/sms.xml deleted file mode 100644 index 3d9433da..00000000 --- a/DRAMSys/library/resources/configs/mcconfigs/sms.xml +++ /dev/null @@ -1,43 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/library/resources/simulations/ddr3-example.xml b/DRAMSys/library/resources/simulations/ddr3-example.xml index c6140385..2c948758 100644 --- a/DRAMSys/library/resources/simulations/ddr3-example.xml +++ b/DRAMSys/library/resources/simulations/ddr3-example.xml @@ -8,9 +8,9 @@ - + - + - ddr3_example.stl + ddr3_example.stl diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.cpp b/DRAMSys/library/src/common/CongenAddressDecoder.cpp index fca1ea3b..46613007 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.cpp +++ b/DRAMSys/library/src/common/CongenAddressDecoder.cpp @@ -37,14 +37,15 @@ #include "utils.h" #include +#include using std::ifstream; using std::cout; using std::endl; - -#include - using std::set; +using std::pair; +using std::map; +using std::deque; tinyxml2::XMLElement *CongenAddressDecoder::GetXMLNode(tinyxml2::XMLElement *pRoot, std::string strName) diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.h b/DRAMSys/library/src/common/CongenAddressDecoder.h index ed523d9d..85829d9d 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.h +++ b/DRAMSys/library/src/common/CongenAddressDecoder.h @@ -43,10 +43,6 @@ #include #include -using std::vector; -using std::pair; -using std::map; - class CongenAddressDecoder : private AddressDecoder { // Friendship needed so that the AddressDecoder can access the @@ -80,13 +76,13 @@ private: m_nByteBits; // Number of Byte bits used by this mapping - vector + std::vector m_vXor; // This container stores for each used xor gate a pair which consists of "First/Number of an address bit which corresponds to a bank" and "Second/Number of an address bit which corresponds to a row" - vector> + std::vector> m_vBankBits; // This container stores for each bank bit a pair which consists of "First/Number of the bank bit" and "Second/Number of the address bit" - vector> + std::vector> m_vRowBits; // This container stores for each row bit a pair which consists of "First/Number of the row bit" and "Second/Number of the address bit" - vector> + std::vector> m_vColumnBits; // This container stores for each column bit a pair which consists of "First/Number of the column bit" and "Second/Number of the address bit" //Methods diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp index ec50b87e..19d6d6df 100644 --- a/DRAMSys/library/src/common/DebugManager.cpp +++ b/DRAMSys/library/src/common/DebugManager.cpp @@ -36,17 +36,16 @@ #include "DebugManager.h" -#ifdef DEBUGGING +#ifndef NDEBUG #include "../configuration/Configuration.h" -using namespace std; -void DebugManager::printDebugMessage(string sender, string message) +void DebugManager::printDebugMessage(std::string sender, std::string message) { - if (Configuration::getInstance().Debug) { + if (Configuration::getInstance().debug) { if (writeToConsole) - cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << - endl; + std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << + std::endl; if (writeToFile && debugFile) debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message @@ -54,13 +53,13 @@ void DebugManager::printDebugMessage(string sender, string message) } } -void DebugManager::printMessage(string sender, string message) +void DebugManager::printMessage(std::string sender, std::string message) { - cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << - endl; + std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << + std::endl; } -void DebugManager::openDebugFile(string filename) +void DebugManager::openDebugFile(std::string filename) { if (debugFile) debugFile.close(); diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index ca3b1fec..83219115 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -37,9 +37,7 @@ #ifndef DEBUGMANAGER_H #define DEBUGMANAGER_H -//#define DEBUGGING - -#ifndef DEBUGGING +#ifdef NDEBUG #define PRINTDEBUGMESSAGE(sender, message) {} #else #define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index d917d47c..0571eb98 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -40,10 +40,10 @@ #include #include "TlmRecorder.h" -#include "protocol.h" #include "dramExtensions.h" #include "XmlAddressDecoder.h" #include "../configuration/Configuration.h" +#include "../controller/Command.h" using namespace tlm; @@ -100,7 +100,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, std::string phaseBeginPrefix = "BEGIN_"; std::string phaseEndPrefix = "END_"; - if (phaseName.find(phaseBeginPrefix) != string::npos) { + if (phaseName.find(phaseBeginPrefix) != std::string::npos) { phaseName.erase(0, phaseBeginPrefix.length()); assert(currentTransactionsInSystem.count(&trans) != 0); currentTransactionsInSystem[&trans].insertPhase(phaseName, time); @@ -153,12 +153,12 @@ void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getExtension(&trans).TimeOfGeneration(); - PRINTDEBUGMESSAGE(name, "New transaction #" + to_string(id) + " generation time " + + PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(id) + " generation time " + currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); if (id % transactionCommitRate == 0) { PRINTDEBUGMESSAGE(name, "Committing transactions " + - to_string(id - transactionCommitRate + 1) + " - " + to_string(id)); + std::to_string(id - transactionCommitRate + 1) + " - " + std::to_string(id)); commitRecordedDataToDB(); } } @@ -168,7 +168,7 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) assert(currentTransactionsInSystem.count(&trans) != 0); PRINTDEBUGMESSAGE(name, "Removing transaction #" + - to_string(currentTransactionsInSystem[&trans].id)); + std::to_string(currentTransactionsInSystem[&trans].id)); Transaction &recordingData = currentTransactionsInSystem[&trans]; recordedData.push_back(recordingData); @@ -259,14 +259,6 @@ void TlmRecorder::setUpTransactionTerminatingPhases() (END_PDNP)); transactionTerminatingPhases.push_back(static_cast (END_SREF)); - - // Phases for Power Down Bankwise - transactionTerminatingPhases.push_back(static_cast - (END_PDNAB)); - transactionTerminatingPhases.push_back(static_cast - (END_PDNPB)); - transactionTerminatingPhases.push_back(static_cast - (END_SREFB)); } void TlmRecorder::prepareSqlStatements() @@ -325,11 +317,11 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 2, simulationTimeCoveredByRecording.value()); sqlite3_bind_int(insertGeneralInfoStatement, 3, - Configuration::getInstance().memSpec->NumberOfRanks); + Configuration::getInstance().memSpec->numberOfRanks); sqlite3_bind_int(insertGeneralInfoStatement, 4, - Configuration::getInstance().memSpec->NumberOfBanks); + Configuration::getInstance().memSpec->numberOfBanks); sqlite3_bind_int(insertGeneralInfoStatement, 5, - Configuration::getInstance().memSpec->clk.value()); + Configuration::getInstance().memSpec->tCK.value()); sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL); sqlite3_bind_text(insertGeneralInfoStatement, 7, mcconfig.c_str(), mcconfig.length(), NULL); @@ -337,18 +329,18 @@ void TlmRecorder::insertGeneralInfo() memspec.length(), NULL); sqlite3_bind_text(insertGeneralInfoStatement, 9, traces.c_str(), traces.length(), NULL); - if (!Configuration::getInstance().EnableWindowing) + if (!Configuration::getInstance().enableWindowing) sqlite3_bind_int64(insertGeneralInfoStatement, 10, 0); else sqlite3_bind_int64(insertGeneralInfoStatement, 10, - (Configuration::getInstance().memSpec->clk * - Configuration::getInstance().WindowSize).value()); - if (Configuration::getInstance().ControllerCoreRefEnablePostpone - || Configuration::getInstance().ControllerCoreRefEnablePullIn) { + (Configuration::getInstance().memSpec->tCK * + Configuration::getInstance().windowSize).value()); + if ((Configuration::getInstance().refreshMaxPostponed > 0) + || (Configuration::getInstance().refreshMaxPulledin > 0)) { sqlite3_bind_int(insertGeneralInfoStatement, 11, 1); sqlite3_bind_int(insertGeneralInfoStatement, 12, - std::max(Configuration::getInstance().ControllerCoreRefMaxPulledIn, - Configuration::getInstance().ControllerCoreRefMaxPostponed)); + std::max(Configuration::getInstance().refreshMaxPostponed, + Configuration::getInstance().refreshMaxPulledin)); } else { sqlite3_bind_int(insertGeneralInfoStatement, 11, 0); sqlite3_bind_int(insertGeneralInfoStatement, 12, 0); @@ -361,21 +353,21 @@ void TlmRecorder::insertCommandLengths() { MemSpec *memSpec = Configuration::getInstance().memSpec; - sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLength[Command::ACT]); - sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLength[Command::PRE]); - sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLength[Command::PREA]); - sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLength[Command::RD]); - sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLength[Command::RDA]); - sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLength[Command::WR]); - sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLength[Command::WRA]); - sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLength[Command::REFA]); - sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLength[Command::REFB]); - sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLength[Command::PDEA]); - sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLength[Command::PDXA]); - sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLength[Command::PDEP]); - sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLength[Command::PDXP]); - sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLength[Command::SREFEN]); - sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLength[Command::SREFEX]); + sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLengthInCycles[Command::ACT]); + sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLengthInCycles[Command::PRE]); + sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLengthInCycles[Command::PREA]); + sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLengthInCycles[Command::RD]); + sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLengthInCycles[Command::RDA]); + sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLengthInCycles[Command::WR]); + sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLengthInCycles[Command::WRA]); + sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLengthInCycles[Command::REFA]); + sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLengthInCycles[Command::REFB]); + sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLengthInCycles[Command::PDEA]); + sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLengthInCycles[Command::PDXA]); + sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLengthInCycles[Command::PDEP]); + sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLengthInCycles[Command::PDXP]); + sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLengthInCycles[Command::SREFEN]); + sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLengthInCycles[Command::SREFEX]); executeSqlStatement(insertCommandLengthsStatement); } @@ -439,7 +431,7 @@ void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement) int errorCode = sqlite3_step(statement); if (errorCode != SQLITE_DONE) { reportFatal("Error in TraceRecorder", - string("Could not execute statement. Error code: ") + to_string(errorCode)); + std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)); } sqlite3_reset(statement); } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 9c6e75e3..6da4608c 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -53,8 +53,6 @@ #include "DebugManager.h" #include "utils.h" -using namespace tlm; - class TlmRecorder { public: @@ -77,12 +75,12 @@ public: this->traces = traces; } - void recordPhase(tlm_generic_payload &trans, tlm_phase phase, + void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time time); void recordPower(double timeInSeconds, double averagePower); void recordDebugMessage(std::string message, sc_time time); void updateDataStrobe(const sc_time &begin, const sc_time &end, - tlm_generic_payload &trans); + tlm::tlm_generic_payload &trans); void closeConnection(); private: @@ -121,8 +119,8 @@ private: void createTables(std::string pathToURI); void setUpTransactionTerminatingPhases(); - void introduceTransactionSystem(tlm_generic_payload &trans); - void removeTransactionFromSystem(tlm_generic_payload &trans); + void introduceTransactionSystem(tlm::tlm_generic_payload &trans); + void removeTransactionFromSystem(tlm::tlm_generic_payload &trans); void commitRecordedDataToDB(); void insertGeneralInfo(); @@ -140,7 +138,7 @@ private: unsigned int totalNumTransactions; sc_time simulationTimeCoveredByRecording; - std::vector transactionTerminatingPhases; + std::vector transactionTerminatingPhases; sqlite3 *db = NULL; sqlite3_stmt *insertTransactionStatement, *insertRangeStatement, *updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement, diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 0dcc2d5d..71a54039 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -53,7 +53,7 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) tinyxml2::XMLDocument doc; loadXML(addressConfigURI, doc); tinyxml2::XMLElement *addressMap = doc.RootElement(); - string xmlNodeName(addressMap->Name()); + std::string xmlNodeName(addressMap->Name()); if (xmlNodeName != "addressmapping") reportFatal("AddressDecorder", "addressmap node expected"); @@ -124,10 +124,10 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (config.NumberOfMemChannels != amount.channel || memSpec->NumberOfRanks != amount.rank - || memSpec->NumberOfBankGroups != amount.bankgroup || memSpec->NumberOfBanks != amount.bank - || memSpec->NumberOfRows != amount.row || memSpec->NumberOfColumns != amount.column - || config.NumberOfDevicesOnDIMM * memSpec->bitWidth != amount.bytes * 8) + if (config.numberOfMemChannels != amount.channel || memSpec->numberOfRanks != amount.rank + || memSpec->numberOfBankGroups != amount.bankgroup || memSpec->numberOfBanks != amount.bank + || memSpec->numberOfRows != amount.row || memSpec->numberOfColumns != amount.column + || config.numberOfDevicesOnDIMM * memSpec->bitWidth != amount.bytes * 8) SC_REPORT_FATAL("XmlAddressDecoder", "Memspec and addressmapping do not match"); } diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index d49666bf..2eedddd4 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -332,7 +332,7 @@ bool operator !=(const Row &lhs, const Row &rhs) const Row Row::operator ++() { - id = (id + 1) % Configuration::getInstance().memSpec->NumberOfRows; + id = (id + 1) % Configuration::getInstance().memSpec->numberOfRows; return *this; } diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 0bb74af1..27aac730 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -41,8 +41,6 @@ #include #include -using namespace tlm; - class Thread { public: @@ -161,7 +159,7 @@ private: }; -class DramExtension : public tlm_extension +class DramExtension : public tlm::tlm_extension { public: DramExtension(); @@ -172,29 +170,29 @@ public: const BankGroup &bankgroup, const Bank &bank, const Row &row, const Column &column, unsigned int burstlength, uint64_t payloadID); - virtual tlm_extension_base *clone() const; - virtual void copy_from(const tlm_extension_base &ext); + virtual tlm::tlm_extension_base *clone() const; + virtual void copy_from(const tlm::tlm_extension_base &ext); - static DramExtension &getExtension(const tlm_generic_payload *payload); - static DramExtension &getExtension(const tlm_generic_payload &payload); + static DramExtension &getExtension(const tlm::tlm_generic_payload *payload); + static DramExtension &getExtension(const tlm::tlm_generic_payload &payload); // Used for convience, caller could also use getExtension(..) to access these field - static Thread getThread(const tlm_generic_payload *payload); - static Thread getThread(const tlm_generic_payload &payload); - static Channel getChannel(const tlm_generic_payload *payload); - static Channel getChannel(const tlm_generic_payload &payload); - static Rank getRank(const tlm_generic_payload *payload); - static Rank getRank(const tlm_generic_payload &payload); - static BankGroup getBankGroup(const tlm_generic_payload *payload); - static BankGroup getBankGroup(const tlm_generic_payload &payload); - static Bank getBank(const tlm_generic_payload *payload); - static Bank getBank(const tlm_generic_payload &payload); - static Row getRow(const tlm_generic_payload *payload); - static Row getRow(const tlm_generic_payload &payload); - static Column getColumn(const tlm_generic_payload *payload); - static Column getColumn(const tlm_generic_payload &payload); - static uint64_t getPayloadID(const tlm_generic_payload *payload); - static uint64_t getPayloadID(const tlm_generic_payload &payload); + static Thread getThread(const tlm::tlm_generic_payload *payload); + static Thread getThread(const tlm::tlm_generic_payload &payload); + static Channel getChannel(const tlm::tlm_generic_payload *payload); + static Channel getChannel(const tlm::tlm_generic_payload &payload); + static Rank getRank(const tlm::tlm_generic_payload *payload); + static Rank getRank(const tlm::tlm_generic_payload &payload); + static BankGroup getBankGroup(const tlm::tlm_generic_payload *payload); + static BankGroup getBankGroup(const tlm::tlm_generic_payload &payload); + static Bank getBank(const tlm::tlm_generic_payload *payload); + static Bank getBank(const tlm::tlm_generic_payload &payload); + static Row getRow(const tlm::tlm_generic_payload *payload); + static Row getRow(const tlm::tlm_generic_payload &payload); + static Column getColumn(const tlm::tlm_generic_payload *payload); + static Column getColumn(const tlm::tlm_generic_payload &payload); + static uint64_t getPayloadID(const tlm::tlm_generic_payload *payload); + static uint64_t getPayloadID(const tlm::tlm_generic_payload &payload); Thread getThread() const; Channel getChannel() const; @@ -224,21 +222,21 @@ private: // Used to indicate the time when a payload is created (in a traceplayer or in a core) // Note that this time can be different from the time the payload enters the DRAM system //(at that time the phase BEGIN_REQ is recorded), so timeOfGeneration =< time(BEGIN_REQ) -class GenerationExtension : public tlm_extension +class GenerationExtension : public tlm::tlm_extension { public: GenerationExtension(sc_time timeOfGeneration) : timeOfGeneration(timeOfGeneration) {} - virtual tlm_extension_base *clone() const; - virtual void copy_from(const tlm_extension_base &ext); + virtual tlm::tlm_extension_base *clone() const; + virtual void copy_from(const tlm::tlm_extension_base &ext); static GenerationExtension - &getExtension(const tlm_generic_payload *payload); + &getExtension(const tlm::tlm_generic_payload *payload); sc_time TimeOfGeneration() const { return timeOfGeneration; } - static sc_time getTimeOfGeneration(const tlm_generic_payload *payload); - static sc_time getTimeOfGeneration(const tlm_generic_payload &payload); + static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload); + static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); private: sc_time timeOfGeneration; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 3b9cdc1e..2e1795b8 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -42,7 +42,6 @@ #include "dramExtensions.h" #include -using namespace std; using namespace tinyxml2; using namespace tlm; @@ -78,7 +77,7 @@ std::string phaseNameToString(tlm_phase phase) return str; } -unsigned int queryUIntParameter(XMLElement *node, string name) +unsigned int queryUIntParameter(XMLElement *node, std::string name) { int result = 0; XMLElement *element; @@ -109,7 +108,7 @@ bool parameterExists(tinyxml2::XMLElement *node, std::string name) return false; } -double queryDoubleParameter(XMLElement *node, string name) +double queryDoubleParameter(XMLElement *node, std::string name) { double result = 0; XMLElement *element; @@ -128,7 +127,7 @@ double queryDoubleParameter(XMLElement *node, string name) return 0; } -bool queryBoolParameter(XMLElement *node, string name) +bool queryBoolParameter(XMLElement *node, std::string name) { bool result = false; XMLElement *element;// = node->FirstChildElement("parameter"); @@ -147,7 +146,7 @@ bool queryBoolParameter(XMLElement *node, string name) return 0; } -string queryStringParameter(XMLElement *node, string name) +std::string queryStringParameter(XMLElement *node, std::string name) { XMLElement *element; for (element = node->FirstChildElement("parameter"); element != NULL; @@ -161,7 +160,7 @@ string queryStringParameter(XMLElement *node, string name) return 0; } -string errorToString(XMLError error) +std::string errorToString(XMLError error) { switch (error) { case XML_NO_ERROR: @@ -209,7 +208,7 @@ string errorToString(XMLError error) } } -void loadXML(string uri, XMLDocument &doc) +void loadXML(std::string uri, XMLDocument &doc) { XMLError error = doc.LoadFile(uri.c_str()); @@ -219,12 +218,12 @@ void loadXML(string uri, XMLDocument &doc) } } -string loadTextFileContents(string filename) +std::string loadTextFileContents(std::string filename) { ifstream in(filename.c_str(), ios::in | ios::binary); if (in) { - string contents; + std::string contents; in.seekg(0, ios::end); contents.resize(in.tellg()); in.seekg(0, ios::beg); diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 826343d6..67955ff0 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -42,76 +42,10 @@ #include "ConfigurationLoader.h" #include "../common/XmlAddressDecoder.h" -using namespace std; +std::string Configuration::memspecUri = ""; +std::string Configuration::mcconfigUri = ""; -string Configuration::memspecUri = ""; -string Configuration::mcconfigUri = ""; - -bool string2bool(string s) -{ - if (s.compare("0") == 0) { - return false; - } else if (s.compare("1") == 0) { - return true; - } else { - SC_REPORT_FATAL("Configuration", ("Could not convert to bool: " + s).c_str()); - return false; - } -} - -int string2int(string s) -{ - return std::stoi(s); -} - -unsigned long long string2ull(string s) -{ - return std::stoull(s); -} - -StorageMode string2StoreMode(string s) -{ - if (s == "NoStorage") - return StorageMode::NoStorage; - else if (s == "Store") - return StorageMode::Store; - else if (s == "ErrorModel") - return StorageMode::ErrorModel; - else { - SC_REPORT_FATAL("Configuration", ("Unknown StorageMode: " + s).c_str()); - throw; - } -} - -EPowerDownMode string2PDNMode(string s) -{ - if (s == "NoPowerDown") - return EPowerDownMode::NoPowerDown; - else if (s == "Staggered") - return EPowerDownMode::Staggered; - else if (s == "TimeoutPDN") - return EPowerDownMode::TimeoutPDN; - else if (s == "TimeoutSREF") - return EPowerDownMode::TimeoutSREF; - else { - SC_REPORT_FATAL("Configuration", ("Unknown PowerDownMode: " + s).c_str()); - throw; - } -} - -ECCControllerMode string2ECCControllerMode(string s) -{ - if (s == "Disabled") - return ECCControllerMode::Disabled; - else if (s == "Hamming") - return ECCControllerMode::Hamming; - else { - SC_REPORT_FATAL("Configuration", ("Unknown ECCControllerMode: " + s).c_str()); - throw; - } -} - -enum sc_time_unit string2TimeUnit(string s) +enum sc_time_unit string2TimeUnit(std::string s) { if (s == "s") return SC_SEC; @@ -134,150 +68,83 @@ enum sc_time_unit string2TimeUnit(string s) void Configuration::setParameter(std::string name, std::string value) { - if (name == "BankwiseLogic") - BankwiseLogic = string2bool(value); - else if (name == "OpenPagePolicy") - OpenPagePolicy = string2bool(value); - else if (name == "AdaptivePagePolicy") - AdaptivePagePolicy = string2bool(value); - else if (name == "MaxNrOfTransactions") - MaxNrOfTransactions = string2int(value); + // MCConfig + if (name == "PagePolicy") + pagePolicy = value; else if (name == "Scheduler") - Scheduler = value; - else if (name == "SJFProbability") - { - if (string2int(value) > 100 || string2int(value) < 0) - SC_REPORT_FATAL("Configuration", - ("Invalid value for parameter " + name + - ". This parameter must be between 0 and 100.").c_str()); - else - SJFProbability = string2int(value); - } + scheduler = value; else if (name == "RequestBufferSize") - RequestBufferSize = string2int(value); - else if (name == "Capsize") - Capsize = string2int(value); + requestBufferSize = std::stoul(value); + else if (name == "CmdMux") + cmdMux = value; + else if (name == "RespQueue") + respQueue = value; + else if (name == "RefreshPolicy") + refreshPolicy = value; + else if (name == "RefreshMode") + refreshMode = std::stoul(value); + else if (name == "RefreshMaxPostponed") + refreshMaxPostponed = std::stoul(value); + else if (name == "RefreshMaxPulledin") + refreshMaxPulledin = std::stoul(value); + else if (name == "PowerDownPolicy") + powerDownPolicy = value; else if (name == "PowerDownTimeout") - powerDownTimeoutInClk = string2int(value); - else if (name == "PowerDownMode") - PowerDownMode = string2PDNMode(value); - else if (name == "ReadWriteGrouping") - ReadWriteGrouping = string2bool(value); - else if (name == "ReorderBuffer") - ReorderBuffer = string2bool(value); - + powerDownTimeout = std::stoul(value); //SimConfig------------------------------------------------ else if (name == "SimulationName") - SimulationName = value; + simulationName = value; else if (name == "DatabaseRecording") - DatabaseRecording = string2bool(value); + databaseRecording = std::stoul(value); else if (name == "PowerAnalysis") - PowerAnalysis = string2bool(value); + powerAnalysis = std::stoul(value); else if (name == "EnableWindowing") - EnableWindowing = string2bool(value); + enableWindowing = std::stoul(value); else if (name == "WindowSize") { - if (string2int(value) < 1) + windowSize = std::stoul(value); + if (windowSize == 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); - else - WindowSize = string2int(value); } else if (name == "Debug") - Debug = string2bool(value); + debug = std::stoul(value); else if (name == "NumberOfMemChannels") - NumberOfMemChannels = string2int(value); - else if (name == "ControllerCoreRefDisable") - ControllerCoreRefDisable = string2bool(value); - else if (name == "ControllerCoreRGR") - RowGranularRef = string2bool(value); - else if (name == "ControllerCoreRGRRowInc") - RowInc = string2int(value); - else if (name == "ControllerCoreRefMode") - { - RefMode = string2int(value); - if (RefMode != 1 && RefMode != 2 && RefMode != 4) - SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str()); - } - else if (name == "ControllerCoreRefNumARCmdsIntREFI") - NumAR = string2int(value); - else if (name == "ControllerCoreRGRB0") - RGRB0 = string2bool(value); - else if (name == "ControllerCoreRGRB1") - RGRB1 = string2bool(value); - else if (name == "ControllerCoreRGRB2") - RGRB2 = string2bool(value); - else if (name == "ControllerCoreRGRB3") - RGRB3 = string2bool(value); - else if (name == "ControllerCoreRGRB4") - RGRB4 = string2bool(value); - else if (name == "ControllerCoreRGRB5") - RGRB5 = string2bool(value); - else if (name == "ControllerCoreRGRB6") - RGRB6 = string2bool(value); - else if (name == "ControllerCoreRGRB7") - RGRB7 = string2bool(value); - else if (name == "ControllerCoreRGRB8") - RGRB8 = string2bool(value); - else if (name == "ControllerCoreRGRB9") - RGRB9 = string2bool(value); - else if (name == "ControllerCoreRGRB10") - RGRB10 = string2bool(value); - else if (name == "ControllerCoreRGRB11") - RGRB11 = string2bool(value); - else if (name == "ControllerCoreRGRB12") - RGRB12 = string2bool(value); - else if (name == "ControllerCoreRGRB13") - RGRB13 = string2bool(value); - else if (name == "ControllerCoreRGRB14") - RGRB14 = string2bool(value); - else if (name == "ControllerCoreRGRB15") - RGRB15 = string2bool(value); - else if (name == "ControllerCoreRefForceMaxPostponeBurst") - ControllerCoreRefForceMaxPostponeBurst = string2bool(value); - else if (name == "ControllerCoreRefEnablePostpone") - ControllerCoreRefEnablePostpone = string2bool(value); - else if (name == "ControllerCoreRefEnablePullIn") - ControllerCoreRefEnablePullIn = string2bool(value); - else if (name == "ControllerCoreRefMaxPostponed") - ControllerCoreRefMaxPostponed = string2int(value); - else if (name == "ControllerCoreRefMaxPulledIn") - ControllerCoreRefMaxPulledIn = string2int(value); + numberOfMemChannels = std::stoul(value); else if (name == "ThermalSimulation") - ThermalSimulation = string2bool(value); + thermalSimulation = std::stoul(value); else if (name == "SimulationProgressBar") - SimulationProgressBar = string2bool(value); + simulationProgressBar = std::stoul(value); else if (name == "NumberOfDevicesOnDIMM") { - if (string2int(value) < 1) + numberOfDevicesOnDIMM = std::stoul(value); + if (numberOfDevicesOnDIMM == 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); - else - NumberOfDevicesOnDIMM = string2int(value); } else if (name == "AddressOffset") { #ifdef DRAMSYS_GEM5 - AddressOffset = string2ull(value); + addressOffset = std::stoull(value); #else - AddressOffset = 0; + addressOffset = 0; #endif } else if (name == "UseMalloc") - UseMalloc = string2bool(value); + useMalloc = std::stoul(value); else if (name == "CheckTLM2Protocol") - CheckTLM2Protocol = string2bool(value); + checkTLM2Protocol = std::stoul(value); else if (name == "ECCControllerMode") - ECCMode = string2ECCControllerMode(value); + ECCMode = value; // Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode else if (name == "ErrorChipSeed") - ErrorChipSeed = string2int(value); + errorChipSeed = std::stoul(value); else if (name == "ErrorCSVFile") - ErrorCSVFile = value; + errorCSVFile = value; else if (name == "StoreMode") - StoreMode = string2StoreMode(value); + storeMode = value; // Temperature Simulation related else if (name == "TemperatureScale") { @@ -287,7 +154,7 @@ void Configuration::setParameter(std::string name, std::string value) temperatureSim.TemperatureScale = value; } else if (name == "StaticTemperatureDefaultValue") - temperatureSim.StaticTemperatureDefaultValue = string2int(value); + temperatureSim.StaticTemperatureDefaultValue = std::stoi(value); else if (name == "ThermalSimPeriod") temperatureSim.ThermalSimPeriod = std::stod(value.c_str()); else if (name == "ThermalSimUnit") @@ -300,15 +167,15 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "IceServerIp") temperatureSim.IceServerIp = value; else if (name == "IceServerPort") - temperatureSim.IceServerPort = string2int(value); + temperatureSim.IceServerPort = std::stoul(value); else if (name == "SimPeriodAdjustFactor") temperatureSim.SimPeriodAdjustFactor = std::stoi(value.c_str()); else if (name == "NPowStableCyclesToIncreasePeriod") temperatureSim.NPowStableCyclesToIncreasePeriod = std::stoi(value.c_str()); else if (name == "GenerateTemperatureMap") - temperatureSim.GenerateTemperatureMap = string2bool(value); + temperatureSim.GenerateTemperatureMap = std::stoul(value); else if (name == "GeneratePowerMap") - temperatureSim.GeneratePowerMap = string2bool(value); + temperatureSim.GeneratePowerMap = std::stoul(value); else SC_REPORT_FATAL("Configuration", ("Parameter " + name + " not defined in Configuration").c_str()); @@ -320,36 +187,23 @@ void Configuration::setPathToResources(std::string path) temperatureSim.setPathToResources(path); } -std::string Configuration::getPathToResources() -{ - return pathToResources; -} -// TODO: Never used -void Configuration::setParameters(std::map - parameterMap) -{ - for (auto item : parameterMap) { - setParameter(item.first, item.second); - } -} - // Returns the total memory size in bytes std::uint64_t Configuration::getSimMemSizeInBytes() { // 1. Get number of banks, rows, columns and data width in bits for one die (or chip) - std::string type = memSpec->MemoryType; - std::uint64_t ranks = memSpec->NumberOfRanks; - std::uint64_t bankgroups = memSpec->NumberOfBankGroups; - std::uint64_t banks = memSpec->NumberOfBanks; - std::uint64_t rows = memSpec->NumberOfRows; - std::uint64_t columns = memSpec->NumberOfColumns; + std::string type = memSpec->memoryType; + std::uint64_t ranks = memSpec->numberOfRanks; + std::uint64_t bankgroups = memSpec->numberOfBankGroups; + std::uint64_t banks = memSpec->numberOfBanks; + std::uint64_t rows = memSpec->numberOfRows; + std::uint64_t columns = memSpec->numberOfColumns; std::uint64_t bitWidth = memSpec->bitWidth; // 2. Calculate size of one DRAM chip in bits std::uint64_t chipBitSize = banks * rows * columns * bitWidth; // 3. Calculate size of one DRAM chip in bytes std::uint64_t chipSize = chipBitSize / 8; // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) - std::uint64_t memorySize = chipSize * NumberOfDevicesOnDIMM; + std::uint64_t memorySize = chipSize * numberOfDevicesOnDIMM; std::cout << headline << std::endl; std::cout << "Per Channel Configuration:" << std::endl << std::endl; @@ -363,7 +217,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::cout << " Chip data bus width: " << bitWidth << std::endl; std::cout << " Chip size in bits: " << chipBitSize << std::endl; std::cout << " Chip Size in bytes: " << chipSize << std::endl; - std::cout << " Devices/Chips on DIMM: " << NumberOfDevicesOnDIMM << std::endl; + std::cout << " Devices/Chips on DIMM: " << numberOfDevicesOnDIMM << std::endl; std::cout << std::endl; assert(memorySize > 0); @@ -376,7 +230,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() // The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc. unsigned int Configuration::getDataBusWidth() { - unsigned int dataBusWidth = memSpec->bitWidth * NumberOfDevicesOnDIMM; + unsigned int dataBusWidth = memSpec->bitWidth * numberOfDevicesOnDIMM; assert(dataBusWidth > 0); return dataBusWidth; } @@ -385,51 +239,35 @@ unsigned int Configuration::getDataBusWidth() unsigned int Configuration::getBytesPerBurst() { // First multiply to get the number of bits in a burst, then divide by 8 to get the value in bytes. The order is important. Think on a single x4 device. - unsigned int bytesPerBurst = (memSpec->BurstLength * getDataBusWidth()) / 8; + unsigned int bytesPerBurst = (memSpec->burstLength * getDataBusWidth()) / 8; assert(bytesPerBurst > 0); - if (NumberOfDevicesOnDIMM > 1) { + if (numberOfDevicesOnDIMM > 1) { // The least significant bits of the physical address are the byte // offset of the N-byte-wide memory module (DIMM) (a single data word // or burst element has N bytes. N = 2^(# bits for byte offset)). unsigned int burstElementSizeInBytes = AddressDecoder::getInstance().amount.bytes; - assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->BurstLength)); + assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->burstLength)); } return bytesPerBurst; } -bool Configuration::getRGRBank(unsigned int w) -{ - bool flg = w == 0 ? RGRB0 : w == 1 ? RGRB1 : w == 2 ? RGRB2 : w == 3 ? RGRB3 : w - == 4 ? RGRB4 : w == 5 ? RGRB5 : w == 6 ? RGRB6 : w == 7 ? RGRB7 : w == 8 ? RGRB8 - : w == 9 ? RGRB9 : w == 10 ? RGRB10 : w == 11 ? RGRB11 : w == 12 ? RGRB12 : w == - 13 ? RGRB13 : w == 14 ? RGRB14 : w == 15 ? RGRB15 : true; - return flg; -} -unsigned int Configuration::getNumAR(void) -{ - return NumAR; -} -unsigned int Configuration::getRowInc(void) -{ - return RowInc; -} - -unsigned int Configuration::getRefMode(void) -{ - return RefMode; -} - // Changes the number of bytes depeding on the ECC Controller. This function is needed for modules which get data directly or indirectly from the ECC Controller unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) { // Manipulate the number of bytes only if there is an ECC Controller selected - if (ECCMode == ECCControllerMode::Disabled) + if (ECCMode == "Disabled") return nBytes; - else { + else if (ECCMode == "Hamming") + { assert(pECC != nullptr); return pECC->AllocationSize(nBytes); } + else + { + SC_REPORT_FATAL("Configuration", ("ECC mode " + ECCMode + " unsupported").c_str()); + return 0; + } } diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index e8fb6bc6..69fb9fec 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -50,10 +50,6 @@ enum class StorageMode {NoStorage, Store, ErrorModel}; -enum class EPowerDownMode {NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF}; - -enum class ECCControllerMode {Disabled, Hamming}; - struct Configuration { static std::string memspecUri; @@ -63,80 +59,44 @@ struct Configuration DEF_SINGLETON(Configuration); // MCConfig: - bool BankwiseLogic = false; - bool OpenPagePolicy = true; - bool AdaptivePagePolicy = false; - unsigned int MaxNrOfTransactions = 8; - std::string Scheduler; - unsigned int SJFProbability; - unsigned int RequestBufferSize; - unsigned int Capsize = 5; - sc_time getPowerDownTimeout() - { - return powerDownTimeoutInClk * memSpec->clk; - } - EPowerDownMode PowerDownMode = EPowerDownMode::Staggered; - bool ReadWriteGrouping = false; - bool ReorderBuffer = false; - + std::string pagePolicy = "Open"; + std::string scheduler = "Fifo"; + std::string cmdMux = "Oldest"; + std::string respQueue = "Fifo"; + unsigned int requestBufferSize = 8; + std::string refreshPolicy = "Rankwise"; + unsigned int refreshMode = 1; + unsigned int refreshMaxPostponed = 0; + unsigned int refreshMaxPulledin = 0; + std::string powerDownPolicy = "NoPowerDown"; + unsigned int powerDownTimeout = 3; // SimConfig - std::string SimulationName = "default"; - bool DatabaseRecording = true; - bool PowerAnalysis = false; - bool EnableWindowing = false; - unsigned int WindowSize = 1000; - bool Debug = false; - unsigned int NumberOfMemChannels = 1; - bool ControllerCoreRefDisable = false; - bool RowGranularRef = false; - bool RGRB0 = true; - bool RGRB1 = true; - bool RGRB2 = true; - bool RGRB3 = true; - bool RGRB4 = true; - bool RGRB5 = true; - bool RGRB6 = true; - bool RGRB7 = true; - bool RGRB8 = true; - bool RGRB9 = true; - bool RGRB10 = true; - bool RGRB11 = true; - bool RGRB12 = true; - bool RGRB13 = true; - bool RGRB14 = true; - bool RGRB15 = true; - unsigned int NumAR = 8192; - unsigned int RefMode = 1; - unsigned int RowInc = 1; - bool getRGRBank(unsigned int); - unsigned int getNumAR(void); - unsigned int getRowInc(void); - unsigned int getRefMode(void); - bool ControllerCoreRefForceMaxPostponeBurst = false; - bool ControllerCoreRefEnablePostpone = false; - bool ControllerCoreRefEnablePullIn = false; - unsigned int ControllerCoreRefMaxPostponed = 8; - unsigned int ControllerCoreRefMaxPulledIn = 8; - bool ThermalSimulation = false; - bool SimulationProgressBar = false; - unsigned int NumberOfDevicesOnDIMM = 1; - bool CheckTLM2Protocol = false; - ECCControllerMode ECCMode = ECCControllerMode::Disabled; + std::string simulationName = "default"; + bool databaseRecording = false; + bool powerAnalysis = false; + bool enableWindowing = false; + unsigned int windowSize = 1000; + bool debug = false; + unsigned int numberOfMemChannels = 1; + bool thermalSimulation = false; + bool simulationProgressBar = false; + unsigned int numberOfDevicesOnDIMM = 8; + bool checkTLM2Protocol = false; + std::string ECCMode = "Disabled"; ECCBaseClass *pECC = nullptr; bool gem5 = false; - bool UseMalloc = false; - unsigned long long int AddressOffset = 0; + bool useMalloc = false; + unsigned long long int addressOffset = 0; // MemSpec (from DRAM-Power XML) MemSpec *memSpec; void setParameter(std::string name, std::string value); - void setParameters(std::map parameterMap); //Configs for Seed, csv file and StorageMode - unsigned int ErrorChipSeed; - std::string ErrorCSVFile = "not defined."; - StorageMode StoreMode; + unsigned int errorChipSeed; + std::string errorCSVFile = "not defined."; + std::string storeMode; // Temperature Simulation related TemperatureSimConfig temperatureSim; @@ -146,11 +106,6 @@ struct Configuration unsigned int getBytesPerBurst(); unsigned int adjustNumBytesAfterECC(unsigned bytes); void setPathToResources(std::string path); - std::string getPathToResources(); - -private: - Configuration() {} - unsigned int powerDownTimeoutInClk = 3; }; #endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 29a46b3e..7a8e9579 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -46,13 +46,11 @@ #include "memspec/MemSpecGDDR5.h" #include "memspec/MemSpecGDDR5X.h" #include "memspec/MemSpecGDDR6.h" -#include "../common/timingCalculations.h" using namespace tinyxml2; -using namespace std; void ConfigurationLoader::loadSimConfig(Configuration &config, - string simconfigUri) + std::string simconfigUri) { tinyxml2::XMLDocument doc; @@ -66,7 +64,7 @@ void ConfigurationLoader::loadSimConfig(Configuration &config, { if (simconfig->Attribute("src")) { XMLDocument doc; - string src(simconfig->Attribute("src")); + std::string src(simconfig->Attribute("src")); loadXML(src, doc); loadSimConfig(config, doc.FirstChildElement("simconfig")); } @@ -112,7 +110,7 @@ void ConfigurationLoader::loadConfigFromUri(Configuration &config, } void ConfigurationLoader::loadMCConfig(Configuration &config, - string mcconfigUri) + std::string mcconfigUri) { tinyxml2::XMLDocument doc; config.mcconfigUri = mcconfigUri; @@ -127,7 +125,7 @@ void ConfigurationLoader::loadMCConfig(Configuration &config, if (mcconfig->Attribute("src")) { XMLDocument doc; - string src(mcconfig->Attribute("src")); + std::string src(mcconfig->Attribute("src")); config.mcconfigUri = src; loadXML(src, doc); loadMCConfig(config, doc.FirstChildElement("mcconfig")); @@ -136,7 +134,7 @@ void ConfigurationLoader::loadMCConfig(Configuration &config, loadConfig(config, mcconfig); } -void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) +void ConfigurationLoader::loadMemSpec(Configuration &config, std::string memspecUri) { tinyxml2::XMLDocument doc; config.memspecUri = memspecUri; @@ -148,7 +146,7 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) void ConfigurationLoader::loadMemSpec(Configuration &config, XMLElement *memspec) { - string memoryType = queryStringParameter(memspec, "memoryType"); + std::string memoryType = queryStringParameter(memspec, "memoryType"); if (memoryType == "DDR4") { Configuration::getInstance().memSpec = new MemSpecDDR4(); @@ -211,21 +209,23 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec { MemSpec *memSpec = config.memSpec; - memSpec->MemoryId = queryStringParameter(xmlSpec, "memoryId"); - memSpec->MemoryType = queryStringParameter(xmlSpec, "memoryType"); + memSpec->memoryId = queryStringParameter(xmlSpec, "memoryId"); + memSpec->memoryType = queryStringParameter(xmlSpec, "memoryType"); // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); + memSpec->burstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->dataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->numberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->numberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); memSpec->bitWidth = queryUIntParameter(architecture, "width"); // Clock XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - memSpec->clk = FrequencyToClk(memSpec->clkMHz); + memSpec->fCKMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->tCK = sc_time(1.0 / memSpec->fCKMHz, SC_US); + + memSpec->burstDuration = memSpec->tCK * (memSpec->burstLength / memSpec->dataRate); } void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) @@ -236,38 +236,37 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL"); + memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL"); // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -293,57 +292,56 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); - memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - unsigned refMode = Configuration::getInstance().getRefMode(); - if (refMode == 1) + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tCCD_S = memSpec->tCK * queryUIntParameter(timings, "CCD_S"); + memSpec->tCCD_L = memSpec->tCK * queryUIntParameter(timings, "CCD_L"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + unsigned refreshMode = Configuration::getInstance().refreshMode; + if (refreshMode == 1) { - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); } - else if (refMode == 2) + else if (refreshMode == 2) { - memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2"); + memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC2"); } - else if (refMode == 4) + else if (refreshMode == 4) { - memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4"); + memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC4"); } else SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported"); - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); - memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); - memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); - memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S = memSpec->tCK * queryUIntParameter(timings, "RRD_S"); + memSpec->tRRD_L = memSpec->tCK * queryUIntParameter(timings, "RRD_L"); + memSpec->tWTR_S = memSpec->tCK * queryUIntParameter(timings, "WTR_S"); + memSpec->tWTR_L = memSpec->tCK * queryUIntParameter(timings, "WTR_L"); + memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL"); + memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL"); // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -372,44 +370,43 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture: XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB"); - memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB"); - memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tRPST = clk * queryUIntParameter(timings, "RPST"); - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS"); - memSpec->tDQS2DQ = clk * queryUIntParameter(timings, "DQS2DQ"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tWPRE = clk * queryUIntParameter(timings, "WPRE"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tSR = clk * queryUIntParameter(timings, "SR"); - memSpec->tXSR = clk * queryUIntParameter(timings, "XSR"); - memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB"); + memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB"); + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tRPST = memSpec->tCK * queryUIntParameter(timings, "RPST"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS"); + memSpec->tDQS2DQ = memSpec->tCK * queryUIntParameter(timings, "DQS2DQ"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWPRE = memSpec->tCK * queryUIntParameter(timings, "WPRE"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tSR = memSpec->tCK * queryUIntParameter(timings, "SR"); + memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR"); + memSpec->tESCKE = memSpec->tCK * queryUIntParameter(timings, "ESCKE"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCMDCKE = memSpec->tCK * queryUIntParameter(timings, "CMDCKE"); // Currents and voltages // TODO: to be completed @@ -423,36 +420,35 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tAC = clk * queryUIntParameter(timings, "AC"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tCCD_R = clk * queryUIntParameter(timings, "CCD_R"); - memSpec->tCCD_W = clk * queryUIntParameter(timings, "CCD_W"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tAC = memSpec->tCK * queryUIntParameter(timings, "AC"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tCCD_R = memSpec->tCK * queryUIntParameter(timings, "CCD_R"); + memSpec->tCCD_W = memSpec->tCK * queryUIntParameter(timings, "CCD_W"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tTAW = memSpec->tCK * queryUIntParameter(timings, "TAW"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -490,40 +486,39 @@ void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = 1; - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = 1; + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tRCpb = clk * queryUIntParameter(timings, "RCPB"); - memSpec->tRCab = clk * queryUIntParameter(timings, "RCAB"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tXSR = clk * queryUIntParameter(timings, "XSR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB"); - memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB"); - memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); + memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tRCpb = memSpec->tCK * queryUIntParameter(timings, "RCPB"); + memSpec->tRCab = memSpec->tCK * queryUIntParameter(timings, "RCAB"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD"); + memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB"); + memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR"); + memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); // Currents and voltages // TODO: to be completed @@ -537,55 +532,54 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for HBM2 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); -// memSpec->tDQSQ = clk * queryUIntParameter(timings, "DQSQ"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); - memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); - memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); - memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tPL = clk * queryUIntParameter(timings, "PL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); - memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); -// memSpec->tCCDR = clk * queryUIntParameter(timings, "CCDR"); - memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); - memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); - memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK"); +// memSpec->tDQSQ = memSpec->tCK * queryUIntParameter(timings, "DQSQ"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tPL = memSpec->tCK * queryUIntParameter(timings, "PL"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); +// memSpec->tCCDR = memSpec->tCK * queryUIntParameter(timings, "CCDR"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); memSpec->tPD = memSpec->tCKE; memSpec->tRDPDE = memSpec->tRL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK; memSpec->tWRPDE = memSpec->tWL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK + memSpec->tWR; memSpec->tWRAPDE = memSpec->tWL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR; - memSpec->tCKESR = memSpec->tCKE + memSpec->clk; + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK + memSpec->tWR; + memSpec->tCKESR = memSpec->tCKE + memSpec->tCK; memSpec->tRDSRE = memSpec->tRL + memSpec->tPL - + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk; - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRFCSB = clk * queryUIntParameter(timings, "RFCSB"); - memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tREFISB = clk * queryUIntParameter(timings, "REFISB"); + + (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK; + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCSB = memSpec->tCK * queryUIntParameter(timings, "RFCSB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFISB = memSpec->tCK * queryUIntParameter(timings, "REFISB"); // Currents and voltages // TODO: to be completed @@ -599,53 +593,52 @@ void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for GDDR5 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); - memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); - memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); - memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); - memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); - memSpec->tCL = clk * queryUIntParameter(timings, "CL"); - memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN"); - memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK"); - memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO"); - memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); - memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tCL = memSpec->tCK * queryUIntParameter(timings, "CL"); + memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); memSpec->tPD = memSpec->tCKE; - memSpec->tXPN = clk * queryUIntParameter(timings, "XPN"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->t32AW = clk * queryUIntParameter(timings, "32AW"); + memSpec->tXPN = memSpec->tCK * queryUIntParameter(timings, "XPN"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW"); memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; - memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tLK = clk * queryUIntParameter(timings, "LK"); + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK"); // Currents and voltages // TODO: to be completed @@ -659,53 +652,52 @@ void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for GDDR5X XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); - memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); - memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); - memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); - memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN"); - memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK"); - memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO"); - memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); - memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); memSpec->tPD = memSpec->tCKE; - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->t32AW = clk * queryUIntParameter(timings, "32AW"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); + memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW"); memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; - memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tLK = clk * queryUIntParameter(timings, "LK"); + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK"); // Currents and voltages // TODO: to be completed @@ -719,56 +711,55 @@ void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; - memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; - memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank; + memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks; + memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks; // MemTimings specific for GDDR6 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); - memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); - memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); - memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); - memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN"); - memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK"); - memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO"); - memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); - memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP"); + memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS"); + memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL"); + memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL"); + memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW"); + memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE"); memSpec->tPD = memSpec->tCKE; - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR"); + memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP"); + memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS"); + memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW"); memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK - + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; - memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tLK = clk * queryUIntParameter(timings, "LK"); - memSpec->tACTPDE = clk * queryUIntParameter(timings, "ACTPDE"); - memSpec->tPREPDE = clk * queryUIntParameter(timings, "PREPDE"); - memSpec->tREFPDE = clk * queryUIntParameter(timings, "REFPDE"); + + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD"); + memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK"); + memSpec->tACTPDE = memSpec->tCK * queryUIntParameter(timings, "ACTPDE"); + memSpec->tPREPDE = memSpec->tCK * queryUIntParameter(timings, "PREPDE"); + memSpec->tREFPDE = memSpec->tCK * queryUIntParameter(timings, "REFPDE"); // Currents and voltages // TODO: to be completed diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 6e96ff4a..b0396643 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -44,44 +44,10 @@ using namespace tlm; MemSpec::MemSpec() { - commandLength = std::vector(numberOfCommands(), 1); + commandLengthInCycles = std::vector(numberOfCommands(), 1); } -const std::vector &MemSpec::getBanks() const +sc_time MemSpec::getCommandLength(Command command) const { - static std::vector banks; - if (banks.size() == 0) { - for (unsigned int i = 0; i < NumberOfBanks; i++) - banks.push_back(Bank(i)); - } - return banks; + return tCK * commandLengthInCycles[command]; } - -sc_time MemSpec::getReadAccessTime() const -{ - return clk * (BurstLength / DataRate); -} - -sc_time MemSpec::getWriteAccessTime() const -{ - return clk * (BurstLength / DataRate); -} - -unsigned MemSpec::getCommandLength(Command command) const -{ - return commandLength[command]; -} - -//sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const -//{ -// if (command == Command::PDEA || command == Command::PDEP) -// return tCKE; -// else if (command == Command::SREFEN) -// return tCKESR; -// else -// { -// SC_REPORT_FATAL("getMinimalExecutionTime", -// "command is not know or command has a fixed execution time"); -// return SC_ZERO_TIME; -// } -//} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 0e95ed05..ff401235 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -44,51 +44,43 @@ #include "../../controller/Command.h" #include "../../common/utils.h" -using namespace tlm; - struct MemSpec { MemSpec(); virtual ~MemSpec() {} - const std::vector &getBanks() const; - - sc_time getWriteAccessTime() const; - sc_time getReadAccessTime() const; - virtual sc_time getRefreshIntervalAB() const = 0; virtual sc_time getRefreshIntervalPB() const = 0; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const = 0; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; - unsigned getCommandLength(Command) const; + sc_time getCommandLength(Command) const; - // Returns the minimum execution time for commands that have a variable execution time - //virtual sc_time getMinExecutionTimeForPowerDownCmd(Command command) const = 0; + std::string memoryId = "not defined."; + std::string memoryType = "not defined."; - std::string MemoryId = "not defined."; - std::string MemoryType = "not defined."; - - unsigned int NumberOfRanks; - unsigned int NumberOfBankGroups; - unsigned int NumberOfBanks; - unsigned int NumberOfRows; - unsigned int NumberOfColumns; - unsigned int BurstLength; - unsigned int DataRate; + unsigned int numberOfRanks; + unsigned int numberOfBankGroups; + unsigned int numberOfBanks; + unsigned int numberOfRows; + unsigned int numberOfColumns; + unsigned int burstLength; + unsigned int dataRate; unsigned int bitWidth; - unsigned int BanksPerRank; - unsigned int BanksPerGroup; - unsigned int GroupsPerRank; + unsigned int banksPerRank; + unsigned int banksPerGroup; + unsigned int groupsPerRank; // Clock - double clkMHz; - sc_time clk; + double fCKMHz; + sc_time tCK; - // Command lengths on bus, standardly one clock cycle - std::vector commandLength; + sc_time burstDuration; + + // Command lengths on bus, usually one clock cycle + std::vector commandLengthInCycles; }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 51b21916..fdf88bd5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -35,6 +35,8 @@ #include "MemSpecDDR3.h" +using namespace tlm; + sc_time MemSpecDDR3::getRefreshIntervalAB() const { return tREFI; @@ -53,16 +55,16 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload return tRP; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD || command == Command::RDA) - return tRL + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + burstDuration; + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tWR + tRP; else if (command == Command::REFA) return tRFC; - else if (command == Command::REFB) - return tRFC; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; else { SC_REPORT_FATAL("getExecutionTime", @@ -74,9 +76,9 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index c8c7beac..35f861c6 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -81,7 +81,7 @@ struct MemSpecDDR3 final : public MemSpec virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 0fd8bfb9..91d4762c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -35,6 +35,8 @@ #include "MemSpecDDR4.h" +using namespace tlm; + sc_time MemSpecDDR4::getRefreshIntervalAB() const { return tREFI; @@ -53,14 +55,16 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload return tRP; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD || command == Command::RDA) - return tRL + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + burstDuration; + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tWR + tRP; else if (command == Command::REFA) return tRFC; - else if (command == Command::REFB) - return tRFC; else { SC_REPORT_FATAL("getExecutionTime", @@ -72,9 +76,9 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index ecadfc18..b37ff5a6 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -87,7 +87,7 @@ struct MemSpecDDR4 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 5bcbcbc6..6c10ec1a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -35,6 +35,8 @@ #include "MemSpecGDDR5.h" +using namespace tlm; + sc_time MemSpecGDDR5::getRefreshIntervalAB() const { return tREFI; @@ -52,14 +54,18 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa else if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) - return tRCDRD + clk; + return tRCDRD; else - return tRCDWR + clk; + return tRCDWR; } - else if (command == Command::RD || command == Command::RDA) - return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime(); + else if (command == Command::RD) + return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tWR + tRP; else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) @@ -76,10 +82,10 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime()); + sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime()); + sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); else { SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index c04bbfd2..22fb4e38 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -83,7 +83,7 @@ struct MemSpecGDDR5 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index d7e148f6..779d4107 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -35,6 +35,8 @@ #include "MemSpecGDDR5X.h" +using namespace tlm; + sc_time MemSpecGDDR5X::getRefreshIntervalAB() const { return tREFI; @@ -52,14 +54,18 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo else if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) - return tRCDRD + clk; + return tRCDRD; else - return tRCDWR + clk; + return tRCDWR; } - else if (command == Command::RD || command == Command::RDA) - return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tWR + tRP; else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) @@ -76,10 +82,10 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime()); + sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime()); + sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); else { SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index a69d76ce..bfa2ece1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -83,7 +83,7 @@ struct MemSpecGDDR5X final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 9be62f01..c3365722 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -35,6 +35,8 @@ #include "MemSpecGDDR6.h" +using namespace tlm; + sc_time MemSpecGDDR6::getRefreshIntervalAB() const { return tREFI; @@ -52,14 +54,18 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa else if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) - return tRCDRD + clk; + return tRCDRD + tCK; else - return tRCDWR + clk; + return tRCDWR + tCK; } - else if (command == Command::RD || command == Command::RDA) - return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tWR + tRP; else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) @@ -76,10 +82,10 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime()); + sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime()); + sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); else { SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index 43924408..88b0e491 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -86,7 +86,7 @@ struct MemSpecGDDR6 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 7fa61d1b..f7898d5c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -35,9 +35,11 @@ #include "MemSpecHBM2.h" +using namespace tlm; + MemSpecHBM2::MemSpecHBM2() { - commandLength[Command::ACT] = 2; + commandLengthInCycles[Command::ACT] = 2; } sc_time MemSpecHBM2::getRefreshIntervalAB() const @@ -57,14 +59,18 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload else if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) - return tRCDRD + clk; + return tRCDRD + tCK; else - return tRCDWR + clk; + return tRCDWR + tCK; } - else if (command == Command::RD || command == Command::RDA) - return tRL + tDQSCK + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + tDQSCK + burstDuration; + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tWR + tRP; else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) @@ -81,10 +87,10 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL + tDQSCK, - sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + sc_time_stamp() + tRL + tDQSCK + burstDuration); else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL, - sc_time_stamp() + tWL + getWriteAccessTime()); + sc_time_stamp() + tWL + burstDuration); else { SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 72b96781..13217183 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -67,11 +67,11 @@ struct MemSpecHBM2 final : public MemSpec sc_time tXP; sc_time tCKE; sc_time tPD; // = tCKE; - sc_time tRDPDE; // = tRL + tPL + (BurstLength / DataRate) * clk + clk; - sc_time tWRPDE; // = tWL + tPL + (BurstLength / DataRate) * clk + clk + tWR; - sc_time tWRAPDE; // = tWL + tPL + (BurstLength / DataRate) * clk + clk + tWR; - sc_time tCKESR; // = tCKE + clk; - sc_time tRDSRE; // = tRL + tPL + (BurstLength / DataRate) * clk + clk; + sc_time tRDPDE; // = tRL + tPL + (BurstLength / DataRate) * tCK + tCK; + sc_time tWRPDE; // = tWL + tPL + (BurstLength / DataRate) * tCK + tCK + tWR; + sc_time tWRAPDE; // = tWL + tPL + (BurstLength / DataRate) * tCK + tCK + tWR; + sc_time tCKESR; // = tCKE + tCK; + sc_time tRDSRE; // = tRL + tPL + (BurstLength / DataRate) * tCK + tCK; sc_time tXS; sc_time tRFC; sc_time tRFCSB; @@ -85,7 +85,7 @@ struct MemSpecHBM2 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 106d3c13..b0b6ee34 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -35,19 +35,21 @@ #include "MemSpecLPDDR4.h" +using namespace tlm; + MemSpecLPDDR4::MemSpecLPDDR4() { - commandLength[Command::ACT] = 4; - commandLength[Command::PRE] = 2; - commandLength[Command::PREA] = 2; - commandLength[Command::RD] = 4; - commandLength[Command::RDA] = 4; - commandLength[Command::WR] = 4; - commandLength[Command::WRA] = 4; - commandLength[Command::REFA] = 2; - commandLength[Command::REFB] = 2; - commandLength[Command::SREFEN] = 2; - commandLength[Command::SREFEX] = 2; + commandLengthInCycles[Command::ACT] = 4; + commandLengthInCycles[Command::PRE] = 2; + commandLengthInCycles[Command::PREA] = 2; + commandLengthInCycles[Command::RD] = 4; + commandLengthInCycles[Command::RDA] = 4; + commandLengthInCycles[Command::WR] = 4; + commandLengthInCycles[Command::WRA] = 4; + commandLengthInCycles[Command::REFA] = 2; + commandLengthInCycles[Command::REFB] = 2; + commandLengthInCycles[Command::SREFEN] = 2; + commandLengthInCycles[Command::SREFEX] = 2; } sc_time MemSpecLPDDR4::getRefreshIntervalAB() const @@ -63,19 +65,23 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE) - return tRPpb + clk; + return tRPpb + tCK; else if (command == Command::PREA) - return tRPab + clk; + return tRPab + tCK; else if (command == Command::ACT) - return tRCD + 3 * clk; - else if (command == Command::RD || command == Command::RDA) - return tRL + tDQSCK + getReadAccessTime() + 3 * clk; - else if (command == Command::WR || command == Command::WRA) - return tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk; + return tRCD + 3 * tCK; + else if (command == Command::RD) + return tRL + tDQSCK + burstDuration + 3 * tCK; + else if (command == Command::RDA) + return burstDuration + tRTP - 5 * tCK + tRPpb; + else if (command == Command::WR) + return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK; + else if (command == Command::WRA) + return tWL + 4 * tCK + burstDuration + tWR + tRPpb; else if (command == Command::REFA) - return tRFCab + clk; + return tRFCab + tCK; else if (command == Command::REFB) - return tRFCpb + clk; + return tRFCpb + tCK; else { SC_REPORT_FATAL("getExecutionTime", @@ -87,11 +93,11 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * clk, - sc_time_stamp() + tRL + tDQSCK + getReadAccessTime() + 3 * clk); + return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * tCK, + sc_time_stamp() + tRL + tDQSCK + burstDuration + 3 * tCK); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * clk, - sc_time_stamp() + tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk); + return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * tCK, + sc_time_stamp() + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK); else { SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 67738e4e..5b05150a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -78,7 +78,7 @@ struct MemSpecLPDDR4 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index af3af2b4..314a4df1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -35,6 +35,8 @@ #include "MemSpecWideIO.h" +using namespace tlm; + sc_time MemSpecWideIO::getRefreshIntervalAB() const { return tREFI; @@ -53,10 +55,14 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo return tRP; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD || command == Command::RDA) - return tRL + tAC + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + tAC + burstDuration; + else if (command == Command::RDA) + return burstDuration + tRP; + else if (command == Command::WR) + return tWL + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration - tCK + tWR + tRP; else if (command == Command::REFA) return tRFC; else @@ -71,10 +77,10 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL + tAC, - sc_time_stamp() + tRL + tAC + getReadAccessTime()); + sc_time_stamp() + tRL + tAC + burstDuration); else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL, - sc_time_stamp() + tWL + getWriteAccessTime()); + sc_time_stamp() + tWL + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index e504c63b..0886ef17 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -91,7 +91,7 @@ struct MemSpecWideIO final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 7d122e17..b19e6f96 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -35,6 +35,8 @@ #include "MemSpecWideIO2.h" +using namespace tlm; + sc_time MemSpecWideIO2::getRefreshIntervalAB() const { return tREFI; @@ -54,10 +56,14 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl return tRPab; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD || command == Command::RDA) - return tRL + tDQSCK + getReadAccessTime(); - else if (command == Command::WR || command == Command::WRA) - return tWL + tDQSS + getWriteAccessTime(); + else if (command == Command::RD) + return tRL + tDQSCK + burstDuration; + else if (command == Command::RDA) + return burstDuration - 2 * tCK + tRTP + tRPpb; + else if (command == Command::WR) + return tWL + tDQSS + burstDuration; + else if (command == Command::WRA) + return tWL + burstDuration + tCK + tWR + tRPpb; else if (command == Command::REFA) return tRFCab; else if (command == Command::REFB) @@ -74,10 +80,10 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL + tDQSCK, - sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + sc_time_stamp() + tRL + tDQSCK + burstDuration); else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL + tDQSS, - sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); + sc_time_stamp() + tWL + tDQSS + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 4caff1e4..bd432a8f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -72,7 +72,7 @@ struct MemSpecWideIO2 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index c0aaa913..47fc5d24 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -34,12 +34,14 @@ #include "BankMachine.h" +using namespace tlm; + BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) { MemSpec *memSpec = Configuration::getInstance().memSpec; - rank = Rank(bank.ID() / memSpec->BanksPerRank); - bankgroup = BankGroup(bank.ID() / memSpec->BanksPerGroup); + rank = Rank(bank.ID() / memSpec->banksPerRank); + bankgroup = BankGroup(bank.ID() / memSpec->banksPerGroup); } std::pair BankMachine::getNextCommand() @@ -52,29 +54,33 @@ std::pair BankMachine::getNextCommand() void BankMachine::updateState(Command command) { - if (command == Command::ACT) + switch (command) { + case Command::ACT: currentState = BmState::Activated; currentRow = DramExtension::getRow(currentPayload); - } - else if (command == Command::PRE || command == Command::PREA) + break; + case Command::PRE: case Command::PREA: currentState = BmState::Precharged; - else if (command == Command::RD || command == Command::WR) + break; + case Command::RD: case Command::WR: currentPayload = nullptr; - else if (command == Command::RDA || command == Command::WRA) - { + break; + case Command::RDA: case Command::WRA: currentState = BmState::Precharged; currentPayload = nullptr; - } - else if (command == Command::PDEA || command == Command::PDEP || command == Command::SREFEN) + break; + case Command::PDEA: case Command::PDEP: case Command::SREFEN: sleeping = true; - else if (command == Command::REFA || command == Command::REFB) - { + break; + case Command::REFA: case Command::REFB: sleeping = false; blocked = false; - } - else if (command == Command::PDXA || command == Command::PDXP) + break; + case Command::PDXA: case Command::PDXP: sleeping = false; + break; + } } void BankMachine::block() @@ -118,21 +124,17 @@ BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Ban sc_time BankMachineOpen::start() { timeToSchedule = sc_max_time(); - sc_time delay = sc_max_time() - sc_time_stamp(); if (sleeping) - return delay; + return timeToSchedule; + currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - { - currentPayload = scheduler->getNextRequest(this); - if (currentPayload == nullptr) - return delay; - } + return timeToSchedule; if (currentState == BmState::Precharged && !blocked) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; } else if (currentState == BmState::Activated) @@ -141,12 +143,12 @@ sc_time BankMachineOpen::start() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RD, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::RD, rank, bankgroup, bank); nextCommand = Command::RD; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WR, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::WR, rank, bankgroup, bank); nextCommand = Command::WR; } else @@ -154,13 +156,11 @@ sc_time BankMachineOpen::start() } else if (!blocked) // row miss { - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; } } - - timeToSchedule = sc_time_stamp() + delay; - return delay; + return timeToSchedule; } BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) @@ -169,40 +169,35 @@ BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, sc_time BankMachineClosed::start() { timeToSchedule = sc_max_time(); - sc_time delay = sc_max_time() - sc_time_stamp(); if (sleeping) - return delay; + return timeToSchedule; + currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - { - currentPayload = scheduler->getNextRequest(this); - if (currentPayload == nullptr) - return delay; - } + return timeToSchedule; if (currentState == BmState::Precharged && !blocked) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; } else if (currentState == BmState::Activated) { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); nextCommand = Command::RDA; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); nextCommand = Command::WRA; } else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - timeToSchedule = sc_time_stamp() + delay; - return delay; + return timeToSchedule; } BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) @@ -211,37 +206,33 @@ BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, Checker sc_time BankMachineOpenAdaptive::start() { timeToSchedule = sc_max_time(); - sc_time delay = sc_max_time() - sc_time_stamp(); if (sleeping) - return delay; + return timeToSchedule; + currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - { - currentPayload = scheduler->getNextRequest(this); - if (currentPayload == nullptr) - return delay; - } + return timeToSchedule; if (currentState == BmState::Precharged && !blocked) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; } else if (currentState == BmState::Activated) { if (DramExtension::getRow(currentPayload) == currentRow) // row hit { - if (scheduler->hasRequest(bank) && !scheduler->hasRowHit(bank, currentRow)) + if (scheduler->hasFurtherRequest(bank) && !scheduler->hasFurtherRowHit(bank, currentRow)) { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); nextCommand = Command::RDA; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); nextCommand = Command::WRA; } else @@ -251,12 +242,12 @@ sc_time BankMachineOpenAdaptive::start() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RD, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::RD, rank, bankgroup, bank); nextCommand = Command::RD; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WR, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::WR, rank, bankgroup, bank); nextCommand = Command::WR; } else @@ -265,12 +256,11 @@ sc_time BankMachineOpenAdaptive::start() } else if (!blocked) // row miss { - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; } } - timeToSchedule = sc_time_stamp() + delay; - return delay; + return timeToSchedule; } BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) @@ -279,37 +269,33 @@ BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, Che sc_time BankMachineClosedAdaptive::start() { timeToSchedule = sc_max_time(); - sc_time delay = sc_max_time() - sc_time_stamp(); if (sleeping) - return delay; + return timeToSchedule; + currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - { - currentPayload = scheduler->getNextRequest(this); - if (currentPayload == nullptr) - return delay; - } + return timeToSchedule; if (currentState == BmState::Precharged && !blocked) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; } else if (currentState == BmState::Activated) { if (DramExtension::getRow(currentPayload) == currentRow) // row hit { - if (scheduler->hasRowHit(bank, currentRow)) + if (scheduler->hasFurtherRowHit(bank, currentRow)) { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RD, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::RD, rank, bankgroup, bank); nextCommand = Command::RD; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WR, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::WR, rank, bankgroup, bank); nextCommand = Command::WR; } else @@ -319,12 +305,12 @@ sc_time BankMachineClosedAdaptive::start() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); nextCommand = Command::RDA; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); nextCommand = Command::WRA; } else @@ -333,11 +319,10 @@ sc_time BankMachineClosedAdaptive::start() } else if (!blocked) // row miss TODO: remove this, can never happen { - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); } } - timeToSchedule = sc_time_stamp() + delay; - return delay; + return timeToSchedule; } diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 49fce270..ade2cf07 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -44,8 +44,6 @@ #include "scheduler/SchedulerIF.h" #include "checker/CheckerIF.h" -using namespace tlm; - class SchedulerIF; class CheckerIF; @@ -60,7 +58,7 @@ class BankMachine public: virtual ~BankMachine() {} virtual sc_time start() = 0; - std::pair getNextCommand(); + std::pair getNextCommand(); void updateState(Command); void block(); @@ -73,7 +71,7 @@ public: protected: BankMachine(SchedulerIF *, CheckerIF *, Bank); - tlm_generic_payload *currentPayload = nullptr; + tlm::tlm_generic_payload *currentPayload = nullptr; SchedulerIF *scheduler; CheckerIF *checker; Command nextCommand; diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 290f7c44..88e64544 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -38,88 +38,30 @@ #include "Command.h" #include +using namespace tlm; +using namespace DRAMPower; std::string commandToString(Command command) -{ - switch (command) { - case Command::RD: - return "RD"; - break; - case Command::RDA: - return "RDA"; - break; - case Command::WR: - return "WR"; - break; - case Command::WRA: - return "WRA"; - break; - case Command::PRE: - return "PRE"; - break; - case Command::ACT: - return "ACT"; - break; - case Command::PREA: - return "PREA"; - break; - case Command::REFA: - return "REFA"; - break; - case Command::REFB: - return "REFB"; - break; - case Command::PDEA: - return "PDEA"; - break; - case Command::PDXA: - return "PDXA"; - break; - case Command::PDEP: - return "PDEP"; - break; - case Command::PDXP: - return "PDXP"; - break; - case Command::SREFEN: - return "SREFEN"; - break; - case Command::SREFEX: - return "SREFEX"; - break; - - case Command::NOP: - return "NOP"; - break; - - default: - SC_REPORT_FATAL("command", "commandToString was called with unknown command"); - break; - } - - return ""; -} - -const std::vector &getAllCommands() -{ - static std::vector allCommands( { Command::NOP, - Command::RD, - Command::WR, - Command::RDA, - Command::WRA, - Command::PRE, - Command::ACT, - Command::REFB, - Command::PREA, - Command::REFA, - Command::PDEA, - Command::PDXA, - Command::PDEP, - Command::PDXP, - Command::SREFEN, - Command::SREFEX - }); - return allCommands; +{ + assert(command >= 0 && command <= 15); + static std::array stringOfCommand = + {"NOP", + "RD", + "WR", + "RDA", + "WRA", + "PRE", + "ACT", + "REFB", + "PREA", + "REFA", + "PDEA", + "PDXA", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX"}; + return stringOfCommand[command]; } unsigned numberOfCommands() @@ -127,48 +69,104 @@ unsigned numberOfCommands() return 16; } -bool commandIsIn(Command command, std::vector commands) +tlm_phase commandToPhase(Command command) { - for (Command c : commands) { - if (c == command) - return true; - } - return false; + assert(command >= 0 && command <= 15); + static std::array phaseOfCommand = + {UNINITIALIZED_PHASE, + BEGIN_RD, + BEGIN_WR, + BEGIN_RDA, + BEGIN_WRA, + BEGIN_PRE, + BEGIN_ACT, + BEGIN_REFB, + BEGIN_PREA, + BEGIN_REFA, + BEGIN_PDNA, + END_PDNA, + BEGIN_PDNP, + END_PDNP, + BEGIN_SREF, + END_SREF}; + return phaseOfCommand[command]; } -std::array phaseOfCommand = {UNINITIALIZED_PHASE, - BEGIN_RD, - BEGIN_WR, - BEGIN_RDA, - BEGIN_WRA, - BEGIN_PRE, - BEGIN_ACT, - BEGIN_REFB, - BEGIN_PREA, - BEGIN_REFA, - BEGIN_PDNA, - END_PDNA, - BEGIN_PDNP, - END_PDNP, - BEGIN_SREF, - END_SREF}; +Command phaseToCommand(tlm_phase phase) +{ + assert(phase >= 5 && phase <= 19); + static std::array commandOfPhase = + {Command::RD, + Command::WR, + Command::RDA, + Command::WRA, + Command::PRE, + Command::ACT, + Command::REFB, + Command::PREA, + Command::REFA, + Command::PDEA, + Command::PDXA, + Command::PDEP, + Command::PDXP, + Command::SREFEN, + Command::SREFEX}; + return commandOfPhase[phase - 5]; +} + +MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) +{ + assert(phase >= 5 && phase <= 19); + static std::array phaseOfCommand = + {MemCommand::RD, + MemCommand::WR, + MemCommand::RDA, + MemCommand::WRA, + MemCommand::PRE, + MemCommand::ACT, + MemCommand::REFB, + MemCommand::PREA, + MemCommand::REF, + MemCommand::PDN_S_ACT, + MemCommand::PUP_ACT, + MemCommand::PDN_S_PRE, + MemCommand::PUP_PRE, + MemCommand::SREN, + MemCommand::SREX}; + return phaseOfCommand[phase - 5]; +} + +bool phaseNeedsEnd(tlm_phase phase) +{ + return (phase >= 5 && phase <= 13); +} + +tlm_phase getEndPhase(tlm_phase phase) +{ + assert(phase >= 5 && phase <= 13); + return (phase + 15); +} bool isBankCommand(Command command) { + assert(command >= 0 && command <= 15); return (command <= 7); } bool isRankCommand(Command command) { + assert(command >= 0 && command <= 15); return (command >= 8); } bool isCasCommand(Command command) { + assert(command >= 0 && command <= 15); return (command <= 4); } bool isRasCommand(Command command) { + assert(command >= 0 && command <= 15); return (command >= 5); } diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 8365ef4d..64d32cc2 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -40,9 +40,34 @@ #include #include #include -#include "../common/protocol.h" +#include "../common/third_party/DRAMPower/src/MemCommand.h" -using namespace tlm; +// DO NOT CHANGE THE ORDER! +DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5 +DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6 +DECLARE_EXTENDED_PHASE(BEGIN_RDA); // 7 +DECLARE_EXTENDED_PHASE(BEGIN_WRA); // 8 +DECLARE_EXTENDED_PHASE(BEGIN_PRE); // 9 +DECLARE_EXTENDED_PHASE(BEGIN_ACT); // 10 +DECLARE_EXTENDED_PHASE(BEGIN_REFB); // 11 +DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 12 +DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 13 +DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 14 +DECLARE_EXTENDED_PHASE(END_PDNA); // 15 +DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 16 +DECLARE_EXTENDED_PHASE(END_PDNP); // 17 +DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18 +DECLARE_EXTENDED_PHASE(END_SREF); // 19 + +DECLARE_EXTENDED_PHASE(END_RD); // 20 +DECLARE_EXTENDED_PHASE(END_WR); // 21 +DECLARE_EXTENDED_PHASE(END_RDA); // 22 +DECLARE_EXTENDED_PHASE(END_WRA); // 23 +DECLARE_EXTENDED_PHASE(END_PRE); // 24 +DECLARE_EXTENDED_PHASE(END_ACT); // 25 +DECLARE_EXTENDED_PHASE(END_REFB); // 26 +DECLARE_EXTENDED_PHASE(END_PREA); // 27 +DECLARE_EXTENDED_PHASE(END_REFA); // 28 enum Command { @@ -64,15 +89,16 @@ enum Command SREFEX }; -std::string commandToString(Command command); -const std::vector &getAllCommands(); +std::string commandToString(Command); +tlm::tlm_phase commandToPhase(Command); +Command phaseToCommand(tlm::tlm_phase); +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); +bool phaseNeedsEnd(tlm::tlm_phase); +tlm::tlm_phase getEndPhase(tlm::tlm_phase); unsigned numberOfCommands(); -bool commandIsIn(Command command, std::vector commands); -bool isBankCommand(Command command); -bool isRankCommand(Command command); -bool isCasCommand(Command command); -bool isRasCommand(Command command); - -extern std::array phaseOfCommand; +bool isBankCommand(Command); +bool isRankCommand(Command); +bool isCasCommand(Command); +bool isRasCommand(Command); #endif // COMMAND_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 54811455..e0190723 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -35,12 +35,8 @@ #include "Controller.h" #include "../configuration/Configuration.h" -#include "scheduler/SchedulerFifo.h" -#include "scheduler/SchedulerFrFcfs.h" -#include "cmdmux/CmdMuxStrict.h" -#include "cmdmux/CmdMuxOldest.h" #include "../common/dramExtensions.h" -#include "../common/protocol.h" +#include "Command.h" #include "checker/CheckerDDR3.h" #include "checker/CheckerDDR4.h" #include "checker/CheckerWideIO.h" @@ -50,149 +46,161 @@ #include "checker/CheckerGDDR5.h" #include "checker/CheckerGDDR5X.h" #include "checker/CheckerGDDR6.h" -#include "refresh/RefreshManager.h" +#include "scheduler/SchedulerFifo.h" +#include "scheduler/SchedulerFrFcfs.h" +#include "scheduler/SchedulerFrFcfsGrp.h" +#include "cmdmux/CmdMuxStrict.h" +#include "cmdmux/CmdMuxOldest.h" +#include "respqueue/RespQueueFifo.h" +#include "respqueue/RespQueueReorder.h" +#include "refresh/RefreshManagerRankwise.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" #include "powerdown/PowerDownManagerStaggered.h" #include "powerdown/PowerDownManagerDummy.h" +using namespace tlm; + Controller::Controller(sc_module_name name) : - GenericController(name) + ControllerIF(name) { SC_METHOD(controllerMethod); - sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEventQueue; - dont_initialize(); + sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEvent; Configuration &config = Configuration::getInstance(); - MemSpec *memSpec = config.memSpec; - ranksNumberOfPayloads = std::vector(memSpec->NumberOfRanks); + memSpec = config.memSpec; + ranksNumberOfPayloads = std::vector(memSpec->numberOfRanks); // instantiate timing checker - if (memSpec->MemoryType == "DDR3") + if (memSpec->memoryType == "DDR3") checker = new CheckerDDR3(); - else if (memSpec->MemoryType == "DDR4") + else if (memSpec->memoryType == "DDR4") checker = new CheckerDDR4(); - else if (memSpec->MemoryType == "WIDEIO_SDR") + else if (memSpec->memoryType == "WIDEIO_SDR") checker = new CheckerWideIO(); - else if (memSpec->MemoryType == "LPDDR4") + else if (memSpec->memoryType == "LPDDR4") checker = new CheckerLPDDR4(); - else if (memSpec->MemoryType == "WIDEIO2") + else if (memSpec->memoryType == "WIDEIO2") checker = new CheckerWideIO2(); - else if (memSpec->MemoryType == "HBM2") + else if (memSpec->memoryType == "HBM2") checker = new CheckerHBM2(); - else if (memSpec->MemoryType == "GDDR5") + else if (memSpec->memoryType == "GDDR5") checker = new CheckerGDDR5(); - else if (memSpec->MemoryType == "GDDR5X") + else if (memSpec->memoryType == "GDDR5X") checker = new CheckerGDDR5X(); - else if (memSpec->MemoryType == "GDDR6") + else if (memSpec->memoryType == "GDDR6") checker = new CheckerGDDR6(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type!"); // instantiate scheduler and command mux - if (config.Scheduler == "FifoStrict") - { + if (config.scheduler == "Fifo") scheduler = new SchedulerFifo(); - commandMux = new CmdMuxStrict(); - } - else if (config.Scheduler == "FrFcfs") - { + else if (config.scheduler == "FrFcfs") scheduler = new SchedulerFrFcfs(); - commandMux = new CmdMuxOldest(); - } + else if (config.scheduler == "FrFcfsGrp") + scheduler = new SchedulerFrFcfsGrp(); else SC_REPORT_FATAL("Controller", "Selected scheduler not supported!"); + if (config.cmdMux == "Oldest") + cmdMux = new CmdMuxOldest(); + else if (config.cmdMux == "Strict") + cmdMux = new CmdMuxStrict(); + else + SC_REPORT_FATAL("Controller", "Selected cmdmux not supported!"); + + if (config.respQueue == "Fifo") + respQueue = new RespQueueFifo(); + else if (config.respQueue == "Reorder") + respQueue = new RespQueueReorder(); + else + SC_REPORT_FATAL("Controller", "Selected respqueue not supported!"); + // instantiate bank machines (one per bank) - if (config.OpenPagePolicy) + if (config.pagePolicy == "Open") { - if (config.AdaptivePagePolicy) - { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID))); - } - else - { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID))); - } + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) + bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID))); + } + else if (config.pagePolicy == "OpenAdaptive") + { + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) + bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID))); + } + else if (config.pagePolicy == "Closed") + { + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) + bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID))); + } + else if (config.pagePolicy == "ClosedAdaptive") + { + for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++) + bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID))); } else - { - if (config.AdaptivePagePolicy) - { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID))); - } - else - { - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID))); - } - } + SC_REPORT_FATAL("Controller", "Selected page policy not supported!"); - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { - bankMachinesOnRank.push_back(std::vector(bankMachines.begin() + rankID * memSpec->BanksPerRank, - bankMachines.begin() + (rankID + 1) * memSpec->BanksPerRank)); + bankMachinesOnRank.push_back(std::vector(bankMachines.begin() + rankID * memSpec->banksPerRank, + bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank)); } // instantiate power-down managers (one per rank) - if (config.PowerDownMode == EPowerDownMode::NoPowerDown) + if (config.powerDownPolicy == "NoPowerDown") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { PowerDownManagerIF *manager = new PowerDownManagerDummy(); powerDownManagers.push_back(manager); } } - else if (config.PowerDownMode == EPowerDownMode::Staggered) + else if (config.powerDownPolicy == "Staggered") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { PowerDownManagerIF *manager = new PowerDownManagerStaggered(Rank(rankID), checker); powerDownManagers.push_back(manager); - manager->triggerEntry(TriggerSource::Controller); - controllerEvent.notify(manager->start()); } } else SC_REPORT_FATAL("Controller", "Selected power-down mode not supported!"); // instantiate refresh managers (one per rank) - if (config.ControllerCoreRefDisable) + if (config.refreshPolicy == "NoRefresh") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) refreshManagers.push_back(new RefreshManagerDummy()); } - else if (config.BankwiseLogic) + else if (config.refreshPolicy == "Rankwise") { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) + { + RefreshManagerIF *manager = new RefreshManagerRankwise + (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); + refreshManagers.push_back(manager); + } + } + else if (config.refreshPolicy == "Bankwise") + { + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { // TODO: remove bankMachines in constructor RefreshManagerIF *manager = new RefreshManagerBankwise (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); - controllerEvent.notify(manager->start()); } } else - { - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) - { - RefreshManagerIF *manager = new RefreshManager - (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); - refreshManagers.push_back(manager); - controllerEvent.notify(manager->start()); - } - } + SC_REPORT_FATAL("Controller", "Selected refresh mode not supported!"); - startBandwidthIdleCollector(); + idleTimeCollector.start(); } Controller::~Controller() { - endBandwithIdleCollector(); + idleTimeCollector.end(); for (auto it : refreshManagers) delete it; @@ -200,46 +208,31 @@ Controller::~Controller() delete it; for (auto it : bankMachines) delete it; - delete commandMux; + delete respQueue; + delete cmdMux; delete scheduler; delete checker; } void Controller::controllerMethod() { - // (1) Release payload if arbiter has accepted the result - if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) - releasePayload(); + // (1) Release payload if arbiter has accepted the result (finish END_RESP) + if (payloadToRelease != nullptr && timeToRelease <= sc_time_stamp()) + finishEndResp(); - // (2) Send next result to arbiter - if (payloadToRelease == nullptr && !responseQueue.empty()) + // (2) Send next result to arbiter (start BEGIN_RESP) + if (payloadToRelease == nullptr) + startBeginResp(); + + // (3) Insert new request from arbiter into scheduler and restart appropriate BM (finish BEGIN_REQ) + if (payloadToAcquire != nullptr && timeToAcquire <= sc_time_stamp()) { - std::pair element = responseQueue.front(); - if (sc_time_stamp() >= element.first) - { - payloadToRelease = element.second; - responseQueue.pop(); - sendToFrontend(payloadToRelease, BEGIN_RESP); - } - } - - // (3) Accept new request from arbiter and start appropriate BM if necessary - if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) - { - if (scheduler->hasBufferSpace(payloadToAcquire)) - { - Bank bank = DramExtension::getBank(payloadToAcquire); - acquirePayload(); - - if (bankMachines[bank.ID()]->isIdle()) - bankMachines[bank.ID()]->start(); - } - else - PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); + unsigned bankID = DramExtension::getBank(payloadToAcquire).ID(); + finishBeginReq(); + bankMachines[bankID]->start(); } // (4) Start refresh and power-down managers to issue requests for the current time - // TODO: check if the order of start() matters, do I always need to start them at this point? No, only if something happened in steps 1-3!!! for (auto it : refreshManagers) it->start(); for (auto it : powerDownManagers) @@ -249,7 +242,7 @@ void Controller::controllerMethod() std::pair commandPair; std::vector> readyCommands; // (5.1) Check for power-down commands (PDEA/PDEP/SREFEN or PDXA/PDXP/SREFEX) - for (unsigned rankID = 0; rankID < Configuration::getInstance().memSpec->NumberOfRanks; rankID++) + for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { commandPair = powerDownManagers[rankID]->getNextCommand(); if (commandPair.second != nullptr) @@ -276,7 +269,7 @@ void Controller::controllerMethod() bool readyCmdBlocked = false; if (!readyCommands.empty()) { - commandPair = commandMux->selectCommand(readyCommands); + commandPair = cmdMux->selectCommand(readyCommands); if (commandPair.second != nullptr) // can happen with FIFO strict { Rank rank = DramExtension::getRank(commandPair.second); @@ -295,30 +288,46 @@ void Controller::controllerMethod() powerDownManagers[rank.ID()]->updateState(commandPair.first); checker->insert(commandPair.first, rank, bankgroup, bank); + if (isCasCommand(commandPair.first)) + { + scheduler->removeRequest(commandPair.second); + respQueue->insertPayload(commandPair.second, memSpec->getIntervalOnDataStrobe(commandPair.first).end); + + sc_time triggerTime = respQueue->getTriggerTime(); + if (triggerTime != sc_max_time()) + dataResponseEvent.notify(triggerTime - sc_time_stamp()); + + ranksNumberOfPayloads[rank.ID()]--; + } + if (ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerEntry(); + sendToDram(commandPair.first, commandPair.second); } else readyCmdBlocked = true; } - // (6) Restart bank machines and refresh managers to issue new requests for the future + // (6) Accept request from arbiter if scheduler is not full, otherwise backpressure (start END_REQ) + if (payloadToAcquire != nullptr && timeToAcquire == sc_max_time()) + startEndReq(); + + // (7) Restart bank machines, refresh managers and power-down managers to issue new requests for the future // TODO: check if all calls are necessary - sc_time delayForNextTrigger = sc_max_time(); + sc_time timeForNextTrigger = sc_max_time(); for (auto it : bankMachines) { - sc_time localDelay = it->start(); - if (!(localDelay == SC_ZERO_TIME && readyCmdBlocked)) - delayForNextTrigger = std::min(delayForNextTrigger, localDelay); + sc_time localTime = it->start(); + if (!(localTime == sc_time_stamp() && readyCmdBlocked)) + timeForNextTrigger = std::min(timeForNextTrigger, localTime); } - if (payloadToAcquire != nullptr && sc_time_stamp() >= timeToAcquire && scheduler->hasBufferSpace(payloadToAcquire)) - acquirePayload(); for (auto it : refreshManagers) - delayForNextTrigger = std::min(delayForNextTrigger, it->start()); + timeForNextTrigger = std::min(timeForNextTrigger, it->start()); for (auto it : powerDownManagers) - delayForNextTrigger = std::min(delayForNextTrigger, it->start()); + timeForNextTrigger = std::min(timeForNextTrigger, it->start()); - if (!(delayForNextTrigger == (sc_max_time() - sc_time_stamp()))) - controllerEvent.notify(delayForNextTrigger); + if (timeForNextTrigger != sc_max_time()) + controllerEvent.notify(timeForNextTrigger - sc_time_stamp()); } tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, @@ -328,19 +337,19 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, if (phase == BEGIN_REQ) { - notificationDelay += Configuration::getInstance().memSpec->clk; + notificationDelay += Configuration::getInstance().memSpec->tCK; payloadToAcquire = &trans; timeToAcquire = sc_time_stamp() + notificationDelay; beginReqEvent.notify(notificationDelay); } else if (phase = END_RESP) { - notificationDelay += Configuration::getInstance().memSpec->clk; + notificationDelay += Configuration::getInstance().memSpec->tCK; timeToRelease = sc_time_stamp() + notificationDelay; endRespEvent.notify(notificationDelay); } else - SC_REPORT_FATAL(0, "nb_transport_fw in controller was triggered with unknown phase"); + SC_REPORT_FATAL("Controller", "nb_transport_fw in controller was triggered with unknown phase"); PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); @@ -348,26 +357,10 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay) +tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &, + tlm_phase &, sc_time &) { - PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + - delay.to_string()); - - if (phase == END_RD || phase == END_RDA || phase == END_WR || phase == END_WRA) - { - // TODO: check this part (order of responses) - responseQueue.push({(sc_time_stamp() + delay), &trans}); - dataResponseEventQueue.notify(delay); - - Rank rank = DramExtension::getRank(trans); - ranksNumberOfPayloads[rank.ID()]--; - if (ranksNumberOfPayloads[rank.ID()] == 0) - { - refreshManagers[rank.ID()]->notifyIdle(); - powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); - } - } + SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; } @@ -377,7 +370,53 @@ unsigned int Controller::transport_dbg(tlm_generic_payload &) return 0; } -void Controller::releasePayload() +void Controller::finishBeginReq() +{ + uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToAcquire); + PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); + + if (totalNumberOfPayloads == 0) + idleTimeCollector.end(); + totalNumberOfPayloads++; + + Rank rank = DramExtension::getRank(payloadToAcquire); + if (ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerExit(); + + ranksNumberOfPayloads[rank.ID()]++; + + scheduler->storeRequest(payloadToAcquire); + payloadToAcquire->acquire(); + timeToAcquire = sc_max_time(); +} + +void Controller::startEndReq() +{ + if (scheduler->hasBufferSpace()) + { + payloadToAcquire->set_response_status(TLM_OK_RESPONSE); + sendToFrontend(payloadToAcquire, END_REQ); + payloadToAcquire = nullptr; + } + else + PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); +} + +void Controller::startBeginResp() +{ + payloadToRelease = respQueue->nextPayload(); + + if (payloadToRelease != nullptr) + sendToFrontend(payloadToRelease, BEGIN_RESP); + else + { + sc_time triggerTime = respQueue->getTriggerTime(); + if (triggerTime != sc_max_time()) + dataResponseEvent.notify(triggerTime - sc_time_stamp()); + } +} + +void Controller::finishEndResp() { uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToRelease); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); @@ -389,33 +428,7 @@ void Controller::releasePayload() totalNumberOfPayloads--; if (totalNumberOfPayloads == 0) - startBandwidthIdleCollector(); -} - -void Controller::acquirePayload() -{ - uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToAcquire); - PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); - - Rank rank = DramExtension::getRank(payloadToAcquire); - - if (totalNumberOfPayloads == 0) - endBandwithIdleCollector(); - totalNumberOfPayloads++; - - if(ranksNumberOfPayloads[rank.ID()] == 0) - { - refreshManagers[rank.ID()]->notifyActive(); - powerDownManagers[rank.ID()]->triggerExit(TriggerSource::Controller); - } - ranksNumberOfPayloads[rank.ID()]++; - - scheduler->storeRequest(payloadToAcquire); - payloadToAcquire->acquire(); - payloadToAcquire->set_response_status(TLM_OK_RESPONSE); - sendToFrontend(payloadToAcquire, END_REQ); - payloadToAcquire = nullptr; - timeToAcquire = sc_max_time(); + idleTimeCollector.start(); } void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) @@ -427,27 +440,7 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) void Controller::sendToDram(Command command, tlm_generic_payload *payload) { sc_time delay = SC_ZERO_TIME; - tlm_phase phase = phaseOfCommand[command]; + tlm_phase phase = commandToPhase(command); iSocket->nb_transport_fw(*payload, phase, delay); } - -void Controller::startBandwidthIdleCollector() -{ - if (!isIdle) - { - PRINTDEBUGMESSAGE(name(), "IDLE start"); - idleStart = sc_time_stamp(); - isIdle = true; - } -} - -void Controller::endBandwithIdleCollector() -{ - if (isIdle) - { - PRINTDEBUGMESSAGE(name(), "IDLE end"); - idleTime += sc_time_stamp() - idleStart; - isIdle = false; - } -} diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 6200bb69..53c116ab 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -42,7 +42,7 @@ #include #include #include -#include "GenericController.h" +#include "ControllerIF.h" #include "../common/dramExtensions.h" #include "BankMachine.h" #include "cmdmux/CmdMuxIF.h" @@ -51,14 +51,13 @@ #include "checker/CheckerIF.h" #include "refresh/RefreshManagerIF.h" #include "powerdown/PowerDownManagerIF.h" - -using namespace tlm; +#include "respqueue/RespQueueIF.h" class BankMachine; class SchedulerIF; class PowerDownManagerStaggered; -class Controller : public GenericController +class Controller : public ControllerIF { public: Controller(sc_module_name); @@ -66,42 +65,40 @@ public: virtual ~Controller(); protected: - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &); - virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &); - virtual unsigned int transport_dbg(tlm_generic_payload &); + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &); + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &); + virtual unsigned int transport_dbg(tlm::tlm_generic_payload &); - virtual void sendToFrontend(tlm_generic_payload *, tlm_phase); - virtual void sendToDram(Command, tlm_generic_payload *); + virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase); + virtual void sendToDram(Command, tlm::tlm_generic_payload *); private: unsigned totalNumberOfPayloads = 0; std::vector ranksNumberOfPayloads; - tlm_generic_payload *payloadToAcquire = nullptr; - sc_time timeToAcquire = sc_max_time(); - tlm_generic_payload *payloadToRelease = nullptr; - sc_time timeToRelease = sc_max_time(); - std::queue> responseQueue; + + MemSpec *memSpec; std::vector bankMachines; std::vector> bankMachinesOnRank; - CmdMuxIF *commandMux; + CmdMuxIF *cmdMux; SchedulerIF *scheduler; CheckerIF *checker; + RespQueueIF *respQueue; std::vector refreshManagers; std::vector powerDownManagers; - void releasePayload(); - void acquirePayload(); + tlm::tlm_generic_payload *payloadToAcquire = nullptr; + sc_time timeToAcquire = sc_max_time(); + tlm::tlm_generic_payload *payloadToRelease = nullptr; + sc_time timeToRelease = sc_max_time(); + + void finishBeginReq(); + void startEndReq(); + void startBeginResp(); + void finishEndResp(); void controllerMethod(); - sc_event beginReqEvent, endRespEvent, controllerEvent; - sc_event_queue dataResponseEventQueue; - - // Bandwidth related - sc_time idleStart; - bool isIdle = false; - void startBandwidthIdleCollector(); - void endBandwithIdleCollector(); + sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; }; #endif // CONTROLLER_H diff --git a/DRAMSys/library/src/controller/GenericController.h b/DRAMSys/library/src/controller/ControllerIF.h similarity index 51% rename from DRAMSys/library/src/controller/GenericController.h rename to DRAMSys/library/src/controller/ControllerIF.h index 896d6fcd..fbcf969f 100644 --- a/DRAMSys/library/src/controller/GenericController.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -1,5 +1,5 @@ -#ifndef GENERICCONTROLLER_H -#define GENERICCONTROLLER_H +#ifndef CONTROLLERIF_H +#define CONTROLLERIF_H #include #include @@ -7,37 +7,35 @@ #include #include "../configuration/Configuration.h" -using namespace tlm; - // Utiliy class to pass around the DRAMSys, without having to propagate the template defintions // throughout all classes -class GenericController : public sc_module +class ControllerIF : public sc_module { public: // Already create and bind sockets to the virtual functions - tlm_utils::simple_target_socket tSocket; // Arbiter side - tlm_utils::simple_initiator_socket iSocket; // DRAM side + tlm_utils::simple_target_socket tSocket; // Arbiter side + tlm_utils::simple_initiator_socket iSocket; // DRAM side // Destructor - virtual ~GenericController() + virtual ~ControllerIF() { sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec->BurstLength - / Configuration::getInstance().memSpec->DataRate - * Configuration::getInstance().memSpec->clk; + * Configuration::getInstance().memSpec->burstLength + / Configuration::getInstance().memSpec->dataRate + * Configuration::getInstance().memSpec->tCK; double bandwidth = (activeTime / sc_time_stamp() * 100); - double bandwidth_IDLE = ((activeTime) / (sc_time_stamp() - idleTime) * 100); + double bandwidthWoIdle = ((activeTime) / (sc_time_stamp() - idleTimeCollector.getIdleTime()) * 100); double maxBandwidth = ( - // clk in Mhz e.g. 800 [MHz]: - (1000000 / Configuration::getInstance().memSpec->clk.to_double()) + // fCK in Mhz e.g. 800 [MHz]: + (1000000 / Configuration::getInstance().memSpec->tCK.to_double()) // DataRate e.g. 2 - * Configuration::getInstance().memSpec->DataRate + * Configuration::getInstance().memSpec->dataRate // BusWidth e.g. 8 or 64 * Configuration::getInstance().memSpec->bitWidth // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); + * Configuration::getInstance().numberOfDevicesOnDIMM ) / ( 1024 ); std::cout << name() << std::string(" Total Time: ") << sc_time_stamp().to_string() @@ -49,8 +47,8 @@ public: << std::endl; std::cout << name() << std::string(" AVG BW\\IDLE: ") << std::fixed << std::setprecision(2) - << ((bandwidth_IDLE / 100) * maxBandwidth) - << " Gibit/s (" << bandwidth_IDLE << " %)" + << ((bandwidthWoIdle / 100) * maxBandwidth) + << " Gibit/s (" << bandwidthWoIdle << " %)" << endl; std::cout << name() << std::string(" MAX BW: ") << std::fixed << std::setprecision(2) @@ -60,24 +58,57 @@ public: protected: // Bind sockets with virtual functions - GenericController(sc_module_name name) : + ControllerIF(sc_module_name name) : sc_module(name), tSocket("tSocket"), iSocket("iSocket") { - tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw); - tSocket.register_transport_dbg(this, &GenericController::transport_dbg); - iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw); + tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw); + tSocket.register_transport_dbg(this, &ControllerIF::transport_dbg); + iSocket.register_nb_transport_bw(this, &ControllerIF::nb_transport_bw); } - SC_HAS_PROCESS(GenericController); + SC_HAS_PROCESS(ControllerIF); // Virtual transport functions - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; - virtual unsigned int transport_dbg(tlm_generic_payload &) = 0; - virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0; + virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) = 0; + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0; // Bandwidth related - sc_time idleTime = SC_ZERO_TIME; + class IdleTimeCollector + { + public: + void start() + { + if (!isIdle) + { + PRINTDEBUGMESSAGE("IdleTimeCollector", "IDLE start"); + idleStart = sc_time_stamp(); + isIdle = true; + } + } + + void end() + { + if (isIdle) + { + PRINTDEBUGMESSAGE("IdleTimeCollector", "IDLE end"); + idleTime += sc_time_stamp() - idleStart; + isIdle = false; + } + } + + sc_time getIdleTime() + { + return idleTime; + } + + private: + bool isIdle = false; + sc_time idleTime = SC_ZERO_TIME; + sc_time idleStart; + } idleTimeCollector; + uint64_t numberOfTransactionsServed = 0; }; -#endif // GENERICCONTROLLER_H +#endif // CONTROLLERIF_H diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index aa2c7722..bcfbc836 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -33,10 +33,10 @@ */ #include "ControllerRecordable.h" - -#include "../common/protocol.h" #include "../configuration/Configuration.h" +using namespace tlm; + tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { @@ -60,7 +60,7 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phas void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload) { - if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) + if (isCasCommand(command)) { TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); @@ -81,9 +81,9 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha uint64_t id __attribute__((unused)) = DramExtension::getExtension(trans).getPayloadID(); PRINTDEBUGMESSAGE(name(), "Recording " + phaseNameToString(phase) + " thread " + - to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( - bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " id " + to_string(id) + " at " + recTime.to_string()); + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( + bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + + std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string()); tlmRecorder->recordPhase(trans, phase, recTime); } diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index 60a70edd..752466b2 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -45,15 +45,15 @@ public: Controller(name), tlmRecorder(tlmRecorder) {} private: - tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay) override; - tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, + tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, + tlm::tlm_phase &phase, sc_time &delay) override; - void sendToFrontend(tlm_generic_payload *, tlm_phase) override; - void sendToDram(Command, tlm_generic_payload *) override; + void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase) override; + void sendToDram(Command, tlm::tlm_generic_payload *) override; - void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay); + void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay); TlmRecorder *tlmRecorder; }; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index ad58c159..1daf2dee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -42,17 +42,15 @@ CheckerDDR3::CheckerDDR3() SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); - - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + lastActivates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -66,7 +64,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -123,20 +121,20 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTR); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -154,12 +152,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + burstClocks + 2 * memSpec->clk - memSpec->tWL); + + memSpec->tRL + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + burstClocks + 2 * memSpec->clk - memSpec->tWL); + + memSpec->tRL + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) @@ -189,7 +187,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -211,12 +209,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -235,7 +233,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -262,22 +260,22 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + 5 * memSpec->clk); + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + 5 * memSpec->clk); + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + 4 * memSpec->clk + memSpec->tWR); + + memSpec->tWL + 4 * memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -294,17 +292,17 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + 5 * memSpec->clk); + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + 5 * memSpec->clk); + + memSpec->tRL + 5 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -325,12 +323,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + std::max(memSpec->tRL + 5 * memSpec->clk, memSpec->tAL + memSpec->tRTP + memSpec->tRP)); + + std::max(memSpec->tRL + 5 * memSpec->tCK, memSpec->tAL + memSpec->tRTP + memSpec->tRP)); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + std::max(memSpec->tWL + 5 * memSpec->clk + memSpec->tWR, memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP)); + + std::max(memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR, memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP)); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -362,9 +360,9 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG reportFatal("CheckerDDR3", "Unknown command!"); // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 5ee8144b..bf86b726 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -45,7 +45,7 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -58,8 +58,6 @@ private: // Four activate window std::vector> lastActivates; - - sc_time burstClocks; }; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 8576d1b6..143d5b90 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -42,19 +42,17 @@ CheckerDDR4::CheckerDDR4() SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); - - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + lastActivates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -68,7 +66,7 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -121,30 +119,30 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWTR_L); + + memSpec->burstDuration + memSpec->tWTR_L); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWTR_S); + + memSpec->burstDuration + memSpec->tWTR_S); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWTR_L); + + memSpec->burstDuration + memSpec->tWTR_L); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWTR_S); + + memSpec->burstDuration + memSpec->tWTR_S); } else if (command == Command::WR || command == Command::WRA) { @@ -154,12 +152,12 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL - + burstClocks + 2 * memSpec->clk - memSpec->tWL); + + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL - + burstClocks + 2 * memSpec->clk - memSpec->tWL); + + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -189,7 +187,7 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWR); + + memSpec->burstDuration + memSpec->tWR); } else if (command == Command::PREA) { @@ -207,12 +205,12 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWR); + + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWR); + + memSpec->burstDuration + memSpec->tWR); } else if (command == Command::REFA) { @@ -227,7 +225,7 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -245,9 +243,9 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG reportFatal("CheckerDDR4", "Unknown command!"); // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 2ff961a9..3f14d754 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -45,7 +45,7 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -59,8 +59,6 @@ private: // Four activate window std::vector> lastActivates; - - sc_time burstClocks; }; #endif // CHECKERDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index f607942f..d8b3c522 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -42,20 +42,18 @@ CheckerGDDR5::CheckerGDDR5() SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->NumberOfRanks); - last32Activates = std::vector>(memSpec->NumberOfRanks); - - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + last4Activates = std::vector>(memSpec->numberOfRanks); + last32Activates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -81,7 +79,7 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -108,8 +106,6 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::RD || command == Command::RDA) { @@ -135,32 +131,30 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); } else if (command == Command::WR || command == Command::WRA) { @@ -190,8 +184,6 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::PRE) { @@ -205,13 +197,11 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::PREA) { @@ -229,18 +219,16 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::REFA) { @@ -255,7 +243,7 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -268,8 +256,6 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::REFB) { @@ -292,7 +278,7 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -316,15 +302,15 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else { reportFatal("CheckerGDDR5", "Unknown command!"); } + // Check if command bus is free + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) @@ -350,5 +336,5 @@ void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index a17b7c28..937fd853 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -45,7 +45,7 @@ class CheckerGDDR5 final : public CheckerIF { public: CheckerGDDR5(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -61,8 +61,6 @@ private: std::vector> last4Activates; std::vector> last32Activates; - sc_time burstClocks; - unsigned bankwiseRefreshCounter = 0; }; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 1f1aee32..7c7d51aa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -42,20 +42,18 @@ CheckerGDDR5X::CheckerGDDR5X() SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - last4Activates = std::vector>(memSpec->NumberOfRanks); - last32Activates = std::vector>(memSpec->NumberOfRanks); - - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + last4Activates = std::vector>(memSpec->numberOfRanks); + last32Activates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -81,7 +79,7 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -108,8 +106,6 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::RD || command == Command::RDA) { @@ -135,32 +131,30 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); } else if (command == Command::WR || command == Command::WRA) { @@ -190,8 +184,6 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::PRE) { @@ -205,13 +197,11 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::PREA) { @@ -229,18 +219,16 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::REFA) { @@ -255,7 +243,7 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -268,8 +256,6 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::REFB) { @@ -292,7 +278,7 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -316,15 +302,15 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban if (last32Activates[rank.ID()].size() == 32) earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else { reportFatal("CheckerGDDR5X", "Unknown command!"); } + // Check if command bus is free + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) @@ -350,5 +336,5 @@ void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 355ca555..8f838914 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -45,7 +45,7 @@ class CheckerGDDR5X final : public CheckerIF { public: CheckerGDDR5X(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -61,8 +61,6 @@ private: std::vector> last4Activates; std::vector> last32Activates; - sc_time burstClocks; - unsigned bankwiseRefreshCounter = 0; }; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index 1a1ae3ae..74abbf99 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -42,19 +42,17 @@ CheckerGDDR6::CheckerGDDR6() SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); - - burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; + lastActivates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -80,7 +78,7 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -104,8 +102,6 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank if (lastActivates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::RD || command == Command::RDA) { @@ -131,32 +127,30 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); } else if (command == Command::WR || command == Command::WRA) { @@ -186,8 +180,6 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::PRE) { @@ -201,13 +193,11 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::PREA) { @@ -225,18 +215,16 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::REFA) { @@ -251,7 +239,7 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -264,8 +252,6 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else if (command == Command::REFB) { @@ -288,7 +274,7 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -309,15 +295,15 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank if (lastActivates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } else { reportFatal("CheckerGDDR6", "Unknown command!"); } + // Check if command bus is free + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) @@ -339,5 +325,5 @@ void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index f61007e6..501c0da6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -45,7 +45,7 @@ class CheckerGDDR6 final : public CheckerIF { public: CheckerGDDR6(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -60,8 +60,6 @@ private: // four activate window std::vector> lastActivates; - sc_time burstClocks; - unsigned bankwiseRefreshCounter = 0; }; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 31d028e9..e2c92f9e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -42,20 +42,18 @@ CheckerHBM2::CheckerHBM2() SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + (numberOfCommands(), std::vector(memSpec->numberOfBankGroups)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); - bankwiseRefreshCounter = std::vector(memSpec->NumberOfRanks); - - burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; + lastActivates = std::vector>(memSpec->numberOfRanks); + bankwiseRefreshCounter = std::vector(memSpec->numberOfRanks); } -sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -77,43 +75,43 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRTP + memSpec->tRP - memSpec->clk); + + memSpec->tRTP + memSpec->tRP - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP - memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB - memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB - memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK); if (lastActivates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, - lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk); + lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else if (command == Command::RD || command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -134,37 +132,37 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); } else if (command == Command::WR || command == Command::WRA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK); lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) @@ -190,12 +188,12 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -204,14 +202,14 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -224,20 +222,20 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else if (command == Command::REFA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -246,7 +244,7 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -260,21 +258,21 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else if (command == Command::REFB) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -283,7 +281,7 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -305,14 +303,14 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastActivates[rank.ID()].size() == 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); } else { reportFatal("CheckerHBM2", "Unknown command!"); } - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) @@ -325,20 +323,20 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - if (command == Command::RD || command == Command::RDA || command == Command::WR || command == Command::WRA) - lastCommandOnCASBus = sc_time_stamp(); + if (isCasCommand(command)) + lastCommandOnCasBus = sc_time_stamp(); else if (command == Command::ACT) - lastCommandOnRASBus = sc_time_stamp() + memSpec->clk; + lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK; else - lastCommandOnRASBus = sc_time_stamp(); + lastCommandOnRasBus = sc_time_stamp(); if (command == Command::ACT || command == Command::REFB) { if (lastActivates[rank.ID()].size() == 4) lastActivates[rank.ID()].pop(); - lastActivates[rank.ID()].push(lastCommandOnRASBus); + lastActivates[rank.ID()].push(lastCommandOnRasBus); } if (command == Command::REFB) - bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 06c688b2..77b27f64 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -45,7 +45,7 @@ class CheckerHBM2 final : public CheckerIF { public: CheckerHBM2(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -55,14 +55,12 @@ private: std::vector> lastScheduledByCommandAndBankGroup; std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; - sc_time lastCommandOnRASBus; - sc_time lastCommandOnCASBus; + sc_time lastCommandOnRasBus; + sc_time lastCommandOnCasBus; // Four activate window std::vector> lastActivates; std::vector bankwiseRefreshCounter; - - sc_time burstClocks; }; #endif // CHECKERHBM2_H diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 64e43f5a..9bc99979 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -46,7 +46,7 @@ class CheckerIF public: virtual ~CheckerIF() {} - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; virtual void insert(Command, Rank, BankGroup, Bank) = 0; }; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index ed7b9116..943298db 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -42,15 +42,15 @@ CheckerLPDDR4::CheckerLPDDR4() SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -63,16 +63,16 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD - + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -84,18 +84,18 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab - 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->tCK); if (lastActivates[rank.ID()].size() == 4) - earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->tCK); } else if (command == Command::RD || command == Command::RDA) { @@ -112,19 +112,19 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); } else if (command == Command::WR || command == Command::WRA) { @@ -133,11 +133,11 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) @@ -150,15 +150,15 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -167,23 +167,23 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban else if (command == Command::PREA) { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK); // lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; // if (lastCommandStart != SC_ZERO_TIME) @@ -197,16 +197,16 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban { lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD - + memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + + memSpec->tWR + 3 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -228,20 +228,20 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD - + memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + + memSpec->tWR + 3 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -260,16 +260,16 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); if (lastActivates[rank.ID()].size() == 4) - earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK); } else { reportFatal("CheckerLPDDR4", "Unknown command!"); } // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) @@ -280,7 +280,7 @@ void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - lastCommandOnBus = sc_time_stamp() + (memSpec->getCommandLength(command) - 1) * memSpec->clk; + lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK; if (command == Command::ACT || command == Command::REFB) { diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index fbadc16e..f52c732e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -45,7 +45,7 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 118abc31..c0236fee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -42,17 +42,15 @@ CheckerWideIO::CheckerWideIO() SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); - - burstClocks = memSpec->BurstLength * memSpec->clk; + lastActivates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -61,12 +59,12 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban { lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL - + burstClocks - memSpec->clk + memSpec->tWR + memSpec->tRP); + + memSpec->burstDuration - memSpec->tCK + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -98,29 +96,29 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR); + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWTR); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->clk + memSpec->tWR); + + memSpec->tWL + memSpec->tCK + memSpec->tWR); } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR); + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWTR); } else if (command == Command::WR || command == Command::WRA) { @@ -130,20 +128,20 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + burstClocks + memSpec->clk); + + memSpec->tRL + memSpec->burstDuration + memSpec->tCK); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + burstClocks + memSpec->clk); + + memSpec->tRL + memSpec->burstDuration + memSpec->tCK); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); } else if (command == Command::PRE) { @@ -152,12 +150,12 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR); } else if (command == Command::PREA) { @@ -166,21 +164,21 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR); + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR); } else if (command == Command::REFA) { @@ -190,12 +188,12 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -214,9 +212,9 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban reportFatal("CheckerWideIO", "Unknown command!"); } // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 6bcc0796..65a8adee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -45,7 +45,7 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: @@ -58,8 +58,6 @@ private: // Four activate window std::vector> lastActivates; - - sc_time burstClocks; }; #endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 463e3eb8..8a2a73fb 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -42,15 +42,15 @@ CheckerWideIO2::CheckerWideIO2() SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + (numberOfCommands(), std::vector(memSpec->numberOfBanks)); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + (numberOfCommands(), std::vector(memSpec->numberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); - lastActivates = std::vector>(memSpec->NumberOfRanks); + lastActivates = std::vector>(memSpec->numberOfRanks); } -sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -68,12 +68,12 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb); + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -114,20 +114,20 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWR - memSpec->tRTP); + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP); } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR); } else if (command == Command::WR || command == Command::WRA) { @@ -137,12 +137,12 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD + memSpec->clk - memSpec->tWL); + + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->tCK - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD + memSpec->clk - memSpec->tWL); + + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->tCK - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) @@ -160,12 +160,12 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk); + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK); } else if (command == Command::PREA) { @@ -175,26 +175,26 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk); + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk); + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->tCK); } else if (command == Command::REFA) { @@ -205,12 +205,12 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb); + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -237,12 +237,12 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb); + + memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -260,9 +260,9 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba reportFatal("CheckerWideIO2", "Unknown command!"); } // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK); - return (earliestTimeToStart - sc_time_stamp()); + return earliestTimeToStart; } void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index 7c27933d..7068601a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -45,7 +45,7 @@ class CheckerWideIO2 final : public CheckerIF { public: CheckerWideIO2(); - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; virtual void insert(Command, Rank, BankGroup, Bank) override; private: diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h index 2e599656..1ec6b817 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h @@ -40,14 +40,12 @@ #include #include "../Command.h" -using namespace tlm; - class CmdMuxIF { public: virtual ~CmdMuxIF() {} - virtual std::pair - selectCommand(std::vector> &) = 0; + virtual std::pair + selectCommand(std::vector> &) = 0; }; #endif // CMDMUXIF_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index 6414c3ce..3ff4abe5 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -36,6 +36,8 @@ #include "../../common/dramExtensions.h" +using namespace tlm; + std::pair CmdMuxOldest::selectCommand(std::vector> &readyCommands) { diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h index 124d056c..9198501a 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h @@ -40,8 +40,8 @@ class CmdMuxOldest : public CmdMuxIF { public: - std::pair - selectCommand(std::vector> &); + std::pair + selectCommand(std::vector> &); }; #endif // CMDMUXOLDEST_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index 6e2d623e..3b37d837 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -36,6 +36,8 @@ #include "../../common/dramExtensions.h" +using namespace tlm; + std::pair CmdMuxStrict::selectCommand(std::vector> &readyCommands) { diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h index 8c98b8c6..1517eeda 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h @@ -40,8 +40,8 @@ class CmdMuxStrict : public CmdMuxIF { public: - std::pair - selectCommand(std::vector> &); + std::pair + selectCommand(std::vector> &); private: uint64_t nextPayloadID = 0; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp index b24db7fb..37013c81 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp @@ -34,6 +34,8 @@ #include "PowerDownManagerDummy.h" +using namespace tlm; + std::pair PowerDownManagerDummy::getNextCommand() { return std::pair(Command::NOP, nullptr); @@ -41,5 +43,5 @@ std::pair PowerDownManagerDummy::getNextCommand( sc_time PowerDownManagerDummy::start() { - return sc_max_time() - sc_time_stamp(); + return sc_max_time(); } diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h index 8aef3f54..bc934dd5 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h @@ -37,17 +37,16 @@ #include "PowerDownManagerIF.h" -using namespace tlm; - class PowerDownManagerDummy final : public PowerDownManagerIF { public: PowerDownManagerDummy() {} - virtual void triggerEntry(TriggerSource) override {} - virtual void triggerExit(TriggerSource) override {} + virtual void triggerEntry() override {} + virtual void triggerExit() override {} + virtual void triggerInterruption() override {} - virtual std::pair getNextCommand() override; + virtual std::pair getNextCommand() override; virtual void updateState(Command) override {} virtual sc_time start() override; }; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h index d6a12ac4..2fa72a17 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h @@ -40,19 +40,16 @@ #include #include "../Command.h" -using namespace tlm; - -enum class TriggerSource {Controller, RefreshManager}; - class PowerDownManagerIF { public: virtual ~PowerDownManagerIF() {} - virtual void triggerEntry(TriggerSource) = 0; - virtual void triggerExit(TriggerSource) = 0; + virtual void triggerEntry() = 0; + virtual void triggerExit() = 0; + virtual void triggerInterruption() = 0; - virtual std::pair getNextCommand() = 0; + virtual std::pair getNextCommand() = 0; virtual void updateState(Command) = 0; virtual sc_time start() = 0; }; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index cf3cc839..09610719 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -35,46 +35,38 @@ #include "PowerDownManagerStaggered.h" #include "../../common/utils.h" +using namespace tlm; + PowerDownManagerStaggered::PowerDownManagerStaggered(Rank rank, CheckerIF *checker) : rank(rank), checker(checker) { setUpDummy(powerDownPayload, rank); } -void PowerDownManagerStaggered::triggerEntry(TriggerSource source) +void PowerDownManagerStaggered::triggerEntry() { - if (source == TriggerSource::Controller) - controllerIdle = true; + controllerIdle = true; - // TODO: check if state is always idle here - if (state == PdmState::Idle && controllerIdle) - triggered = true; + if (state == PdmState::Idle) + entryTriggered = true; } -void PowerDownManagerStaggered::triggerExit(TriggerSource source) +void PowerDownManagerStaggered::triggerExit() { - if (source == TriggerSource::Controller) - { - controllerIdle = false; - enterSelfRefresh = false; + controllerIdle = false; + enterSelfRefresh = false; + entryTriggered = false; - if (state == PdmState::Idle) - triggered = false; - else - triggered = true; - } - else // if (source == TriggerSource::RefreshManager) - { - if (state == PdmState::Idle && !enterSelfRefresh) - triggered = false; - else if (state == PdmState::PrechargePd && !triggered) - { - triggered = true; - enterSelfRefresh = true; - } - else if (state == PdmState::ActivePd) // TODO: check if normal else is also ok here - triggered = true; - } + if (state != PdmState::Idle) + exitTriggered = true; +} + +void PowerDownManagerStaggered::triggerInterruption() +{ + entryTriggered = false; + + if (state != PdmState::Idle) + exitTriggered = true; } std::pair PowerDownManagerStaggered::getNextCommand() @@ -88,75 +80,89 @@ std::pair PowerDownManagerStaggered::getNextComm sc_time PowerDownManagerStaggered::start() { timeToSchedule = sc_max_time(); - sc_time delay = sc_max_time() - sc_time_stamp(); - if (triggered) + if (exitTriggered) { - if (state == PdmState::Idle) - { - if (enterSelfRefresh) - nextCommand = Command::SREFEN; - else if (activatedBanks == 0) - nextCommand = Command::PDEP; - else - nextCommand = Command::PDEA; - } - else if (state == PdmState::ActivePd) + if (state == PdmState::ActivePdn) nextCommand = Command::PDXA; - else if (state == PdmState::PrechargePd) + else if (state == PdmState::PrechargePdn) nextCommand = Command::PDXP; else if (state == PdmState::SelfRefresh) nextCommand = Command::SREFEX; - else // if (state == PdmState::Refresh) + else if (state == PdmState::ExtraRefresh) nextCommand = Command::REFA; - delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + } + else if (entryTriggered) + { + if (activatedBanks != 0) + nextCommand = Command::PDEA; + else + nextCommand = Command::PDEP; + + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + } + else if (enterSelfRefresh) + { + nextCommand = Command::SREFEN; + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); } - return delay; + return timeToSchedule; } void PowerDownManagerStaggered::updateState(Command command) { - if (command == Command::ACT) + switch (command) + { + case Command::ACT: activatedBanks++; - else if (command == Command::PRE) + break; + case Command::PRE: activatedBanks--; - else if (command == Command::PREA) + break; + case Command::PREA: activatedBanks = 0; - else if (command == Command::PDEA) - { - state = PdmState::ActivePd; - triggered = false; - } - else if (command == Command::PDEP) - { - state = PdmState::PrechargePd; - triggered = false; - } - else if (command == Command::SREFEN) - { + break; + case Command::PDEA: + state = PdmState::ActivePdn; + entryTriggered = false; + break; + case Command::PDEP: + state = PdmState::PrechargePdn; + entryTriggered = false; + break; + case Command::SREFEN: state = PdmState::SelfRefresh; - triggered = false; + entryTriggered = false; enterSelfRefresh = false; - } - else if (command == Command::PDXA) - { + break; + case Command::PDXA: state = PdmState::Idle; - triggered = false; - } - else if (command == Command::PDXP) - { + exitTriggered = false; + break; + case Command::PDXP: state = PdmState::Idle; - if (!enterSelfRefresh) - triggered = false; - } - else if (command == Command::SREFEX) - state = PdmState::Refresh; - else if (command == Command::REFA && state == PdmState::Refresh) - { - state = PdmState::Idle; - triggered = false; + exitTriggered = false; + if (controllerIdle) + enterSelfRefresh = true; + break; + case Command::SREFEX: + state = PdmState::ExtraRefresh; + break; + case Command::REFA: + if (state == PdmState::ExtraRefresh) + { + state = PdmState::Idle; + exitTriggered = false; + } + else if (controllerIdle) + entryTriggered = true; + break; + case Command::REFB: + if (controllerIdle) + entryTriggered = true; + break; } } diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h index 350e38b5..fee58fb3 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h @@ -39,32 +39,32 @@ #include "../BankMachine.h" #include "../checker/CheckerIF.h" -using namespace tlm; - class PowerDownManagerStaggered final : public PowerDownManagerIF { public: PowerDownManagerStaggered(Rank, CheckerIF *); - virtual void triggerEntry(TriggerSource) override; - virtual void triggerExit(TriggerSource) override; + virtual void triggerEntry() override; + virtual void triggerExit() override; + virtual void triggerInterruption() override; - virtual std::pair getNextCommand() override; + virtual std::pair getNextCommand() override; virtual void updateState(Command) override; virtual sc_time start() override; private: - enum class PdmState {Idle, ActivePd, PrechargePd, SelfRefresh, Refresh} state = PdmState::Idle; - tlm_generic_payload powerDownPayload; + enum class PdmState {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = PdmState::Idle; + tlm::tlm_generic_payload powerDownPayload; Rank rank; CheckerIF *checker; - sc_time timeToSchedule; + sc_time timeToSchedule = sc_max_time(); Command nextCommand; - bool triggered = false; - bool enterSelfRefresh = false; bool controllerIdle = true; + bool entryTriggered = true; + bool exitTriggered = false; + bool enterSelfRefresh = false; unsigned activatedBanks = 0; }; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 0475ec6b..349bef14 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -37,33 +37,33 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" +using namespace tlm; + RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) - : bankMachines(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) + : bankMachinesOnRank(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; timeForNextTrigger = memSpec->getRefreshIntervalPB(); - refreshPayloads = std::vector(memSpec->BanksPerRank); - for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) + refreshPayloads = std::vector(memSpec->banksPerRank); + for (unsigned bankID = 0; bankID < memSpec->banksPerRank; bankID++) { setUpDummy(refreshPayloads[bankID], rank, bankMachines[bankID]->getBank()); allBankMachines.push_back(bankMachines[bankID]); } remainingBankMachines = allBankMachines; - if (config.ControllerCoreRefEnablePostpone) - maxPostponed = config.ControllerCoreRefMaxPostponed * memSpec->BanksPerRank; - if (config.ControllerCoreRefEnablePullIn) - maxPulledin = -(config.ControllerCoreRefMaxPulledIn * memSpec->BanksPerRank); + maxPostponed = config.refreshMaxPostponed * memSpec->banksPerRank; + maxPulledin = -(config.refreshMaxPulledin * memSpec->banksPerRank); } std::pair RefreshManagerBankwise::getNextCommand() { if (sc_time_stamp() == timeToSchedule) return std::pair - (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); + (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->banksPerRank]); else return std::pair(Command::NOP, nullptr); } @@ -74,9 +74,9 @@ sc_time RefreshManagerBankwise::start() if (sc_time_stamp() >= timeForNextTrigger) { - powerDownManager->triggerExit(TriggerSource::RefreshManager); + powerDownManager->triggerInterruption(); if (sleeping) - return sc_max_time() - sc_time_stamp(); + return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) { @@ -84,7 +84,6 @@ sc_time RefreshManagerBankwise::start() state = RmState::Regular; } - sc_time delay; if (state == RmState::Regular) { currentIterator = remainingBankMachines.begin(); @@ -107,7 +106,7 @@ sc_time RefreshManagerBankwise::start() { flexibilityCounter++; timeForNextTrigger += memSpec->getRefreshIntervalPB(); - return timeForNextTrigger - sc_time_stamp(); + return timeForNextTrigger; } else { @@ -115,10 +114,9 @@ sc_time RefreshManagerBankwise::start() nextCommand = Command::PRE; else nextCommand = Command::REFB; - delay = checker->delayToSatisfyConstraints(nextCommand, rank, + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); - timeToSchedule = sc_time_stamp() + delay; - return delay; + return timeToSchedule; } } else // if (state == RmState::Pulledin) @@ -140,7 +138,7 @@ sc_time RefreshManagerBankwise::start() { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalPB(); - return timeForNextTrigger - sc_time_stamp(); + return timeForNextTrigger; } else { @@ -148,21 +146,21 @@ sc_time RefreshManagerBankwise::start() nextCommand = Command::PRE; else nextCommand = Command::REFB; - delay = checker->delayToSatisfyConstraints(nextCommand, rank, + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); - timeToSchedule = sc_time_stamp() + delay; - return delay; + return timeToSchedule; } } } else - return timeForNextTrigger - sc_time_stamp(); + return timeForNextTrigger; } void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *payload) { - if (command == Command::REFB) + switch (command) { + case Command::REFB: remainingBankMachines.erase(currentIterator); if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; @@ -176,23 +174,23 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalPB(); - powerDownManager->triggerEntry(TriggerSource::RefreshManager); } - } - else if (command == Command::REFA) - { + break; + case Command::REFA: // Refresh command after SREFEX state = RmState::Regular; // TODO: check if this assignment is necessary timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalPB(); sleeping = false; - } - else if (command == Command::PDEA || command == Command::PDEP) + break; + case Command::PDEA: case Command::PDEP: sleeping = true; - else if (command == Command::SREFEN) - { + break; + case Command::SREFEN: sleeping = true; timeForNextTrigger = sc_max_time(); - } - else if (command == Command::PDXA || command == Command::PDXP) + break; + case Command::PDXA: case Command::PDXP: sleeping = false; + break; + } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index e92cc08f..285329b5 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -43,26 +43,21 @@ #include #include -using namespace tlm; - class RefreshManagerBankwise final : public RefreshManagerIF { public: RefreshManagerBankwise(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - virtual std::pair getNextCommand() override; + virtual std::pair getNextCommand() override; virtual sc_time start() override; - virtual void updateState(Command, tlm_generic_payload *) override; - - virtual void notifyActive() override {} - virtual void notifyIdle() override {} + virtual void updateState(Command, tlm::tlm_generic_payload *) override; private: enum class RmState {Regular, Pulledin} state = RmState::Regular; const MemSpec *memSpec; - std::vector &bankMachines; + std::vector &bankMachinesOnRank; PowerDownManagerIF *powerDownManager; - std::vector refreshPayloads; + std::vector refreshPayloads; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); Rank rank; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp index c6c1428c..1f4c1d9e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -34,6 +34,8 @@ #include "RefreshManagerDummy.h" +using namespace tlm; + std::pair RefreshManagerDummy::getNextCommand() { return std::pair(Command::NOP, nullptr); @@ -41,5 +43,5 @@ std::pair RefreshManagerDummy::getNextCommand() sc_time RefreshManagerDummy::start() { - return sc_max_time() - sc_time_stamp(); + return sc_max_time(); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index e9c2cabe..58ea2a59 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -41,17 +41,12 @@ #include "RefreshManagerIF.h" #include "../Command.h" -using namespace tlm; - class RefreshManagerDummy final : public RefreshManagerIF { public: - virtual std::pair getNextCommand() override; + virtual std::pair getNextCommand() override; virtual sc_time start() override; - virtual void updateState(Command, tlm_generic_payload *) override {} - - virtual void notifyActive() override {} - virtual void notifyIdle() override {} + virtual void updateState(Command, tlm::tlm_generic_payload *) override {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index cedf94c9..89283183 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -40,19 +40,14 @@ #include #include "../Command.h" -using namespace tlm; - class RefreshManagerIF { public: virtual ~RefreshManagerIF() {} - virtual std::pair getNextCommand() = 0; + virtual std::pair getNextCommand() = 0; virtual sc_time start() = 0; - virtual void updateState(Command, tlm_generic_payload *) = 0; - - virtual void notifyIdle() = 0; - virtual void notifyActive() = 0; + virtual void updateState(Command, tlm::tlm_generic_payload *) = 0; }; #endif // REFRESHMANAGERIF_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp similarity index 61% rename from DRAMSys/library/src/controller/refresh/RefreshManager.cpp rename to DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp index 148c8828..90c56855 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp @@ -32,37 +32,27 @@ * Author: Lukas Steiner */ -#include "RefreshManager.h" +#include "RefreshManagerRankwise.h" #include "../../common/dramExtensions.h" #include "../../configuration/Configuration.h" #include "../../common/utils.h" -RefreshManager::RefreshManager(std::vector &bankMachines, +using namespace tlm; + +RefreshManagerRankwise::RefreshManagerRankwise(std::vector &bankMachines, PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) - : bankMachines(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) + : bankMachinesOnRank(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; timeForNextTrigger = memSpec->getRefreshIntervalAB(); setUpDummy(refreshPayload, rank); - if (config.ControllerCoreRefEnablePostpone) - maxPostponed = config.ControllerCoreRefMaxPostponed; - if (config.ControllerCoreRefEnablePullIn) - maxPulledin = -config.ControllerCoreRefMaxPulledIn; + maxPostponed = config.refreshMaxPostponed; + maxPulledin = -config.refreshMaxPulledin; } -void RefreshManager::notifyActive() -{ - controllerIdle = false; -} - -void RefreshManager::notifyIdle() -{ - controllerIdle = true; -} - -std::pair RefreshManager::getNextCommand() +std::pair RefreshManagerRankwise::getNextCommand() { if (sc_time_stamp() == timeToSchedule) return std::pair(nextCommand, &refreshPayload); @@ -70,15 +60,15 @@ std::pair RefreshManager::getNextCommand() return std::pair(Command::NOP, nullptr); } -sc_time RefreshManager::start() +sc_time RefreshManagerRankwise::start() { timeToSchedule = sc_max_time(); if (sc_time_stamp() >= timeForNextTrigger) { - powerDownManager->triggerExit(TriggerSource::RefreshManager); + powerDownManager->triggerInterruption(); if (sleeping) - return sc_max_time() - sc_time_stamp(); + return timeToSchedule; if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) { @@ -86,64 +76,84 @@ sc_time RefreshManager::start() state = RmState::Regular; } - sc_time delay; if (state == RmState::Regular) { - bool forcedRefresh = (flexibilityCounter == maxPostponed); - if (!forcedRefresh && !controllerIdle) // no forced refresh & controller is busy -> postpone + if (flexibilityCounter == maxPostponed) // forced refresh { - flexibilityCounter++; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); - return timeForNextTrigger - sc_time_stamp(); + for (auto it : bankMachinesOnRank) + it->block(); } else { - if (forcedRefresh) + bool controllerBusy = false; + for (auto it : bankMachinesOnRank) { - for (auto it : bankMachines) - it->block(); + if (!it->isIdle()) + { + controllerBusy = true; + break; + } } - if (activatedBanks > 0) - nextCommand = Command::PREA; - else - nextCommand = Command::REFA; - delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; - return delay; + if (controllerBusy) + { + flexibilityCounter++; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + return timeForNextTrigger; + } } + + if (activatedBanks > 0) + nextCommand = Command::PREA; + else + nextCommand = Command::REFA; + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + return timeToSchedule; } else // if (state == RmState::Pulledin) { - if (!controllerIdle) + bool controllerBusy = false; + for (auto it : bankMachinesOnRank) + { + if (!it->isIdle()) + { + controllerBusy = true; + break; + } + } + + if (controllerBusy) { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); - return timeForNextTrigger - sc_time_stamp(); + return timeForNextTrigger; } else { // nextCommand stays Command::REFA - delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; - return delay; + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + return timeToSchedule; } } } else - return timeForNextTrigger - sc_time_stamp(); + return timeForNextTrigger; } -void RefreshManager::updateState(Command command, tlm_generic_payload *) +void RefreshManagerRankwise::updateState(Command command, tlm_generic_payload *) { - if (command == Command::ACT) - activatedBanks++; - else if (command == Command::PRE) - activatedBanks--; - else if (command == Command::PREA) - activatedBanks = 0; - else if (command == Command::REFA) + switch (command) { + case Command::ACT: + activatedBanks++; + break; + case Command::PRE: + activatedBanks--; + break; + case Command::PREA: + activatedBanks = 0; + break; + case Command::REFA: if (sleeping) { // Refresh command after SREFEX @@ -162,17 +172,18 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); - powerDownManager->triggerEntry(TriggerSource::RefreshManager); } } - } - else if (command == Command::PDEA || command == Command::PDEP) + break; + case Command::PDEA: case Command::PDEP: sleeping = true; - else if (command == Command::SREFEN) - { + break; + case Command::SREFEN: sleeping = true; timeForNextTrigger = sc_max_time(); - } - else if (command == Command::PDXA || command == Command::PDXP) + break; + case Command::PDXA: case Command::PDXP: sleeping = false; + break; + } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h similarity index 79% rename from DRAMSys/library/src/controller/refresh/RefreshManager.h rename to DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h index e6a2942a..3dd93385 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h @@ -32,8 +32,8 @@ * Author: Lukas Steiner */ -#ifndef REFRESHMANAGER_H -#define REFRESHMANAGER_H +#ifndef REFRESHMANAGERRANKWISE_H +#define REFRESHMANAGERRANKWISE_H #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" @@ -41,33 +41,27 @@ #include "../powerdown/PowerDownManagerIF.h" #include "../checker/CheckerIF.h" -using namespace tlm; - -class RefreshManager final : public RefreshManagerIF +class RefreshManagerRankwise final : public RefreshManagerIF { public: - RefreshManager(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); + RefreshManagerRankwise(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - virtual std::pair getNextCommand() override; + virtual std::pair getNextCommand() override; virtual sc_time start() override; - virtual void updateState(Command, tlm_generic_payload *) override; - - virtual void notifyActive() override; - virtual void notifyIdle() override; + virtual void updateState(Command, tlm::tlm_generic_payload *) override; private: enum class RmState {Regular, Pulledin} state = RmState::Regular; const MemSpec *memSpec; - std::vector &bankMachines; + std::vector &bankMachinesOnRank; PowerDownManagerIF *powerDownManager; - tlm_generic_payload refreshPayload; + tlm::tlm_generic_payload refreshPayload; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); Rank rank; CheckerIF *checker; Command nextCommand; - bool controllerIdle = true; unsigned activatedBanks = 0; int flexibilityCounter = 0; @@ -77,4 +71,4 @@ private: bool sleeping = false; }; -#endif // REFRESHMANAGER_H +#endif // REFRESHMANAGERRANKWISE_H diff --git a/DRAMSys/library/src/common/timingCalculations.cpp b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp similarity index 62% rename from DRAMSys/library/src/common/timingCalculations.cpp rename to DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp index be69fb44..5374b48d 100644 --- a/DRAMSys/library/src/common/timingCalculations.cpp +++ b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, University of Kaiserslautern + * Copyright (c) 2019, University of Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,43 +29,39 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: - * Janik Schlemminger - * Matthias Jung + * Author: Lukas Steiner */ -#include "timingCalculations.h" -#include "../configuration/memspec/MemSpec.h" -#include "DebugManager.h" -#include "../configuration/Configuration.h" -#include "utils.h" +#include "RespQueueFifo.h" -sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, - sc_time constraint) +using namespace tlm; + +void RespQueueFifo::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) { - if (previous + constraint > start) - return previous + constraint - start; - else - return SC_ZERO_TIME; + buffer.push({payload, strobeEnd}); } -const sc_time FrequencyToClk(double frequencyMhz) +tlm_generic_payload *RespQueueFifo::nextPayload() { - return sc_time(1 / frequencyMhz, SC_US); + if (!buffer.empty()) + { + std::pair element = buffer.front(); + if (element.second <= sc_time_stamp()) + { + buffer.pop(); + return element.first; + } + } + return nullptr; } -const sc_time clkAlign(sc_time time, Alignment alignment) +sc_time RespQueueFifo::getTriggerTime() const { - sc_time clk = Configuration::getInstance().memSpec->clk; - if (alignment == UP) - return ceil(time / clk) * clk; - else - return floor(time / clk) * clk; + if (!buffer.empty()) + { + sc_time triggerTime = buffer.front().second; + if (triggerTime > sc_time_stamp()) + return triggerTime; + } + return sc_max_time(); } - -bool isClkAligned(sc_time time, sc_time clk) -{ - return !((time / clk) - ceil(time / clk)); -} - - diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h new file mode 100644 index 00000000..8a5e0dd2 --- /dev/null +++ b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef RESPQUEUEFIFO_H +#define RESPQUEUEFIFO_H + +#include +#include +#include "RespQueueIF.h" +#include +#include + +class RespQueueFifo final : public RespQueueIF +{ +public: + virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override; + virtual tlm::tlm_generic_payload *nextPayload() override; + virtual sc_time getTriggerTime() const override; + +private: + std::queue> buffer; +}; + +#endif // RESPQUEUEFIFO_H diff --git a/DRAMSys/library/src/common/timingCalculations.h b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h similarity index 74% rename from DRAMSys/library/src/common/timingCalculations.h rename to DRAMSys/library/src/controller/respqueue/RespQueueIF.h index 7288b93c..078ddb93 100644 --- a/DRAMSys/library/src/common/timingCalculations.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, University of Kaiserslautern + * Copyright (c) 2019, University of Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,24 +29,21 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: - * Janik Schlemminger - * Matthias Jung + * Author: Lukas Steiner */ -#ifndef TIMINGCALCULATIONS_H -#define TIMINGCALCULATIONS_H +#ifndef RESPQUEUEIF_H +#define RESPQUEUEIF_H #include #include -#include "dramExtensions.h" -sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, - sc_time constraint); +class RespQueueIF +{ +public: + virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0; + virtual tlm::tlm_generic_payload *nextPayload() = 0; + virtual sc_time getTriggerTime() const = 0; +}; -enum Alignment {UP, DOWN}; -const sc_time clkAlign(sc_time time, Alignment alignment = UP); -bool isClkAligned(sc_time time, sc_time clk); -const sc_time FrequencyToClk(double frequencyMhz); - -#endif // TIMINGCALCULATIONS_H +#endif // RESPQUEUEIF_H diff --git a/DRAMSys/library/src/common/protocol.h b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp similarity index 53% rename from DRAMSys/library/src/common/protocol.h rename to DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp index 986ef847..5ee814f9 100644 --- a/DRAMSys/library/src/common/protocol.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, University of Kaiserslautern + * Copyright (c) 2019, University of Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,63 +29,46 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung + * Author: Lukas Steiner */ -#ifndef PROTOCOL_H -#define PROTOCOL_H +#include "RespQueueReorder.h" +#include "../../common/dramExtensions.h" -// DRAM Control Phases -DECLARE_EXTENDED_PHASE(BEGIN_PRE); -DECLARE_EXTENDED_PHASE(END_PRE); +using namespace tlm; -DECLARE_EXTENDED_PHASE(BEGIN_PREA); -DECLARE_EXTENDED_PHASE(END_PREA); +void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) +{ + buffer[DramExtension::getPayloadID(payload)] = {payload, strobeEnd}; +} -DECLARE_EXTENDED_PHASE(BEGIN_ACT); -DECLARE_EXTENDED_PHASE(END_ACT); - -DECLARE_EXTENDED_PHASE(BEGIN_REFA); -DECLARE_EXTENDED_PHASE(END_REFA); - -DECLARE_EXTENDED_PHASE(BEGIN_REFB); -DECLARE_EXTENDED_PHASE(END_REFB); - -// Phases for Read and Write -DECLARE_EXTENDED_PHASE(BEGIN_WR); -DECLARE_EXTENDED_PHASE(END_WR); - -DECLARE_EXTENDED_PHASE(BEGIN_RD); -DECLARE_EXTENDED_PHASE(END_RD); - -DECLARE_EXTENDED_PHASE(BEGIN_WRA); -DECLARE_EXTENDED_PHASE(END_WRA); - -DECLARE_EXTENDED_PHASE(BEGIN_RDA); -DECLARE_EXTENDED_PHASE(END_RDA); - -// Phases for Power Down -DECLARE_EXTENDED_PHASE(BEGIN_PDNP); -DECLARE_EXTENDED_PHASE(END_PDNP); - -DECLARE_EXTENDED_PHASE(BEGIN_PDNA); -DECLARE_EXTENDED_PHASE(END_PDNA); - -DECLARE_EXTENDED_PHASE(BEGIN_SREF); -DECLARE_EXTENDED_PHASE(END_SREF); - -// Phases for Power Down Bankwise -DECLARE_EXTENDED_PHASE(BEGIN_PDNPB); -DECLARE_EXTENDED_PHASE(END_PDNPB); - -DECLARE_EXTENDED_PHASE(BEGIN_PDNAB); -DECLARE_EXTENDED_PHASE(END_PDNAB); - -DECLARE_EXTENDED_PHASE(BEGIN_SREFB); -DECLARE_EXTENDED_PHASE(END_SREFB); - -#endif // PROTOCOL_H +tlm_generic_payload *RespQueueReorder::nextPayload() +{ + if (!buffer.empty()) + { + if (buffer.begin()->first == currentPayloadID) + { + std::pair element = buffer.begin()->second; + if (element.second <= sc_time_stamp()) + { + buffer.erase(currentPayloadID++); + return element.first; + } + } + } + return nullptr; +} +sc_time RespQueueReorder::getTriggerTime() const +{ + if (!buffer.empty()) + { + if (buffer.begin()->first == currentPayloadID) + { + sc_time triggerTime = buffer.begin()->second.second; + if (triggerTime > sc_time_stamp()) + return triggerTime; + } + } + return sc_max_time(); +} diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h new file mode 100644 index 00000000..242b9d8d --- /dev/null +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef RESPQUEUEREORDER_H +#define RESPQUEUEREORDER_H + +#include +#include +#include "RespQueueIF.h" +#include + +class RespQueueReorder final : public RespQueueIF +{ +public: + virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override; + virtual tlm::tlm_generic_payload *nextPayload() override; + virtual sc_time getTriggerTime() const override; + +private: + uint64_t currentPayloadID = 0; + // Muss die Zeit aller Payloads gespeichert werden? + std::map> buffer; +}; + +#endif // RESPQUEUEREORDER_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index ce31bc50..87cdc55e 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -34,16 +34,18 @@ #include "SchedulerFifo.h" +using namespace tlm; + SchedulerFifo::SchedulerFifo() { - buffer = std::vector> - (Configuration::getInstance().memSpec->NumberOfBanks); - maxNumberOfRequests = Configuration::getInstance().MaxNrOfTransactions; + buffer = std::vector> + (Configuration::getInstance().memSpec->numberOfBanks); + requestBufferSize = Configuration::getInstance().requestBufferSize; } -bool SchedulerFifo::hasBufferSpace(tlm_generic_payload *payload) +bool SchedulerFifo::hasBufferSpace() { - if (buffer[DramExtension::getBank(payload).ID()].size() < maxNumberOfRequests) + if (buffer[lastBankID].size() < requestBufferSize) return true; else return false; @@ -51,37 +53,39 @@ bool SchedulerFifo::hasBufferSpace(tlm_generic_payload *payload) void SchedulerFifo::storeRequest(tlm_generic_payload *payload) { - buffer[DramExtension::getBank(payload).ID()].push(payload); + lastBankID = DramExtension::getBank(payload).ID(); + buffer[lastBankID].push_back(payload); +} + +void SchedulerFifo::removeRequest(tlm_generic_payload *payload) +{ + buffer[DramExtension::getBank(payload).ID()].pop_front(); } tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) { unsigned bankID = bankMachine->getBank().ID(); if (!buffer[bankID].empty()) - { - tlm_generic_payload *front = buffer[bankID].front(); - buffer[bankID].pop(); - return front; - } + return buffer[bankID].front(); else return nullptr; } -bool SchedulerFifo::hasRowHit(Bank bank, Row row) +bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row) { - if (!buffer[bank.ID()].empty()) + if (buffer[bank.ID()].size() >= 2) { - tlm_generic_payload *front = buffer[bank.ID()].front(); - if (DramExtension::getRow(front) == row) + tlm_generic_payload *nextRequest = buffer[bank.ID()][1]; + if (DramExtension::getRow(nextRequest) == row) return true; } return false; } -bool SchedulerFifo::hasRequest(Bank bank) +bool SchedulerFifo::hasFurtherRequest(Bank bank) { - if (buffer[bank.ID()].empty()) - return false; - else + if (buffer[bank.ID()].size() >= 2) return true; + else + return false; } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index f2d9f8be..dc9359bc 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -37,25 +37,25 @@ #include #include -#include +#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" #include "../BankMachine.h" -using namespace tlm; - class SchedulerFifo : public SchedulerIF { public: SchedulerFifo(); - virtual bool hasBufferSpace(tlm_generic_payload *) override; - virtual void storeRequest(tlm_generic_payload *) override; - virtual tlm_generic_payload *getNextRequest(BankMachine *) override; - virtual bool hasRowHit(Bank, Row) override; - virtual bool hasRequest(Bank) override; + virtual bool hasBufferSpace() override; + virtual void storeRequest(tlm::tlm_generic_payload *) override; + virtual void removeRequest(tlm::tlm_generic_payload *) override; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual bool hasFurtherRowHit(Bank, Row) override; + virtual bool hasFurtherRequest(Bank) override; private: - std::vector> buffer; - unsigned maxNumberOfRequests; + std::vector> buffer; + unsigned requestBufferSize; + unsigned lastBankID; }; #endif // SCHEDULERFIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index eb784508..f730eac5 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -36,16 +36,18 @@ #include +using namespace tlm; + SchedulerFrFcfs::SchedulerFrFcfs() { buffer = std::vector> - (Configuration::getInstance().memSpec->NumberOfBanks); - maxNumberOfRequests = Configuration::getInstance().MaxNrOfTransactions; + (Configuration::getInstance().memSpec->numberOfBanks); + requestBufferSize = Configuration::getInstance().requestBufferSize; } -bool SchedulerFrFcfs::hasBufferSpace(tlm_generic_payload *payload) +bool SchedulerFrFcfs::hasBufferSpace() { - if (buffer[DramExtension::getBank(payload).ID()].size() < maxNumberOfRequests) + if (buffer[lastBankID].size() < requestBufferSize) return true; else return false; @@ -53,7 +55,22 @@ bool SchedulerFrFcfs::hasBufferSpace(tlm_generic_payload *payload) void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) { - buffer[DramExtension::getBank(payload).ID()].push_back(payload); + lastBankID = DramExtension::getBank(payload).ID(); + buffer[lastBankID].push_back(payload); +} + +void SchedulerFrFcfs::removeRequest(tlm_generic_payload *payload) +{ + unsigned bankID = DramExtension::getBank(payload).ID(); + for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) + { + if (*it == payload) + { + buffer[bankID].erase(it); + return; + } + } + SC_REPORT_FATAL("SchedulerFrFcfs", "removeRequest failed!"); } tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) @@ -61,51 +78,41 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) unsigned bankID = bankMachine->getBank().ID(); if (!buffer[bankID].empty()) { - BmState currentState = bankMachine->getState(); - if (currentState == BmState::Precharged) - { - tlm_generic_payload *result = buffer[bankID].front(); - buffer[bankID].pop_front(); - return result; - } - else if (currentState == BmState::Activated) + if (bankMachine->getState() == BmState::Activated) { // Search for row hit Row openRow = bankMachine->getOpenRow(); for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) { if (DramExtension::getRow(*it) == openRow) - { - tlm_generic_payload *result = *it; - buffer[bankID].erase(it); - return result; - } + return *it; } - // No row hit found - tlm_generic_payload *result = buffer[bankID].front(); - buffer[bankID].pop_front(); - return result; } - else - SC_REPORT_FATAL("SchedulerFrFcfs", "Wrong BM state!"); + // No row hit found or bank precharged + return buffer[bankID].front(); } return nullptr; } -bool SchedulerFrFcfs::hasRowHit(Bank bank, Row row) +bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row) { + unsigned rowHitCounter = 0; for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++) { if (DramExtension::getRow(*it) == row) - return true; + { + rowHitCounter++; + if (rowHitCounter == 2) + return true; + } } return false; } -bool SchedulerFrFcfs::hasRequest(Bank bank) +bool SchedulerFrFcfs::hasFurtherRequest(Bank bank) { - if (buffer[bank.ID()].empty()) - return false; - else + if (buffer[bank.ID()].size() >= 2) return true; + else + return false; } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 5bf4f264..7cce4050 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -42,20 +42,20 @@ #include "../../common/dramExtensions.h" #include "../BankMachine.h" -using namespace tlm; - class SchedulerFrFcfs : public SchedulerIF { public: SchedulerFrFcfs(); - virtual bool hasBufferSpace(tlm_generic_payload *) override; - virtual void storeRequest(tlm_generic_payload *) override; - virtual tlm_generic_payload *getNextRequest(BankMachine *) override; - virtual bool hasRowHit(Bank, Row) override; - virtual bool hasRequest(Bank) override; + virtual bool hasBufferSpace() override; + virtual void storeRequest(tlm::tlm_generic_payload *) override; + virtual void removeRequest(tlm::tlm_generic_payload *) override; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual bool hasFurtherRowHit(Bank, Row) override; + virtual bool hasFurtherRequest(Bank) override; private: - std::vector> buffer; - unsigned maxNumberOfRequests; + std::vector> buffer; + unsigned requestBufferSize; + unsigned lastBankID; }; #endif // SCHEDULERFRFCFS_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp new file mode 100644 index 00000000..c2df4082 --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2020, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "SchedulerFrFcfsGrp.h" + +using namespace tlm; + +SchedulerFrFcfsGrp::SchedulerFrFcfsGrp() +{ + buffer = std::vector> + (Configuration::getInstance().memSpec->numberOfBanks); + requestBufferSize = Configuration::getInstance().requestBufferSize; +} + +bool SchedulerFrFcfsGrp::hasBufferSpace() +{ + if (buffer[lastBankID].size() < requestBufferSize) + return true; + else + return false; +} + +void SchedulerFrFcfsGrp::storeRequest(tlm_generic_payload *payload) +{ + lastBankID = DramExtension::getBank(payload).ID(); + buffer[lastBankID].push_back(payload); +} + +void SchedulerFrFcfsGrp::removeRequest(tlm_generic_payload *payload) +{ + lastCommand = payload->get_command(); + unsigned bankID = DramExtension::getBank(payload).ID(); + for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) + { + if (*it == payload) + { + buffer[bankID].erase(it); + return; + } + } + SC_REPORT_FATAL("SchedulerFrFcfs", "removeRequest failed!"); +} + +tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine) +{ + unsigned bankID = bankMachine->getBank().ID(); + if (!buffer[bankID].empty()) + { + if (bankMachine->getState() == BmState::Activated) + { + // Filter all row hits + Row openRow = bankMachine->getOpenRow(); + std::list rowHits; + for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) + { + if (DramExtension::getRow(*it) == openRow) + rowHits.push_back(*it); + } + + if (!rowHits.empty()) + { + for (auto outerIt = rowHits.begin(); outerIt != rowHits.end(); outerIt++) + { + if ((*outerIt)->get_command() == lastCommand) + { + bool hazardDetected = false; + for (auto innerIt = rowHits.begin(); *innerIt != *outerIt; innerIt++) + { + if ((*outerIt)->get_address() == (*innerIt)->get_address()) + { + hazardDetected = true; + break; + } + } + if (!hazardDetected) + return *outerIt; + } + } + // no rd/wr hit found -> take first row hit + return *rowHits.begin(); + } + } + // No row hit found or bank precharged + return buffer[bankID].front(); + } + return nullptr; +} + +bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row) +{ + unsigned rowHitCounter = 0; + for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++) + { + if (DramExtension::getRow(*it) == row) + { + rowHitCounter++; + if (rowHitCounter == 2) + return true; + } + } + return false; +} + +bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank) +{ + if (buffer[bank.ID()].size() >= 2) + return true; + else + return false; +} diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h new file mode 100644 index 00000000..8c7ed9bc --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2020, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef SCHEDULERFRFCFSGRP_H +#define SCHEDULERFRFCFSGRP_H + +#include +#include +#include + +#include "SchedulerIF.h" +#include "../../common/dramExtensions.h" +#include "../BankMachine.h" + +class SchedulerFrFcfsGrp : public SchedulerIF +{ +public: + SchedulerFrFcfsGrp(); + virtual bool hasBufferSpace() override; + virtual void storeRequest(tlm::tlm_generic_payload *) override; + virtual void removeRequest(tlm::tlm_generic_payload *) override; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual bool hasFurtherRowHit(Bank, Row) override; + virtual bool hasFurtherRequest(Bank) override; +private: + std::vector> buffer; + unsigned requestBufferSize; + tlm::tlm_command lastCommand = tlm::TLM_READ_COMMAND; + unsigned lastBankID; +}; + +#endif // SCHEDULERFRFCFSGRP_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index c882a3b0..2c2723a6 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -40,8 +40,6 @@ #include "../../common/DebugManager.h" #include "../BankMachine.h" -using namespace tlm; - enum class BmState; class BankMachine; @@ -49,11 +47,12 @@ class SchedulerIF { public: virtual ~SchedulerIF() {} - virtual bool hasBufferSpace(tlm_generic_payload *) = 0; - virtual void storeRequest(tlm_generic_payload *) = 0; - virtual tlm_generic_payload *getNextRequest(BankMachine *) = 0; - virtual bool hasRowHit(Bank, Row) = 0; - virtual bool hasRequest(Bank) = 0; + virtual bool hasBufferSpace() = 0; + virtual void storeRequest(tlm::tlm_generic_payload *) = 0; + virtual void removeRequest(tlm::tlm_generic_payload *) = 0; + virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) = 0; + virtual bool hasFurtherRowHit(Bank, Row) = 0; + virtual bool hasFurtherRequest(Bank) = 0; }; #endif // SCHEDULERIF_H diff --git a/DRAMSys/library/src/error/ECC/Word.cpp b/DRAMSys/library/src/error/ECC/Word.cpp index 47794ea0..a59c38e3 100644 --- a/DRAMSys/library/src/error/ECC/Word.cpp +++ b/DRAMSys/library/src/error/ECC/Word.cpp @@ -5,6 +5,7 @@ #include using std::cout; +using std::deque; CWord::CWord(unsigned nBitLength) : m_nBitLength(nBitLength) diff --git a/DRAMSys/library/src/error/ECC/Word.h b/DRAMSys/library/src/error/ECC/Word.h index c3edb1ae..743d7cfe 100644 --- a/DRAMSys/library/src/error/ECC/Word.h +++ b/DRAMSys/library/src/error/ECC/Word.h @@ -3,15 +3,12 @@ #include #include "Bit.h" -using std::deque; - - class CWord { protected: unsigned m_nBitLength; - deque m_word; + std::deque m_word; public: diff --git a/DRAMSys/library/src/error/eccbaseclass.cpp b/DRAMSys/library/src/error/eccbaseclass.cpp index 6c41e6d1..0f2fc4e1 100644 --- a/DRAMSys/library/src/error/eccbaseclass.cpp +++ b/DRAMSys/library/src/error/eccbaseclass.cpp @@ -1,5 +1,7 @@ #include "eccbaseclass.h" +using namespace tlm; + tlm::tlm_sync_enum ECCBaseClass::nb_transport_fw( int id, tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay ) { diff --git a/DRAMSys/library/src/error/eccbaseclass.h b/DRAMSys/library/src/error/eccbaseclass.h index 720be2d7..57f20aa7 100644 --- a/DRAMSys/library/src/error/eccbaseclass.h +++ b/DRAMSys/library/src/error/eccbaseclass.h @@ -11,9 +11,6 @@ #include "../common/XmlAddressDecoder.h" #include "../common/DebugManager.h" -using namespace std; -using namespace tlm; - class ECCBaseClass : sc_module { public: @@ -23,7 +20,7 @@ public: }; private: - map m_mDataPointer; + std::map m_mDataPointer; public: // Function prototype for calculated the size of memory needed for saving the encoded data diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index b23b8dff..9b20c68b 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -43,18 +43,18 @@ void errorModel::init() { - powerAnalysis = Configuration::getInstance().PowerAnalysis; - thermalSim = Configuration::getInstance().ThermalSimulation; + powerAnalysis = Configuration::getInstance().powerAnalysis; + thermalSim = Configuration::getInstance().thermalSimulation; // Get Configuration parameters: - burstLenght = Configuration::getInstance().memSpec->BurstLength; - numberOfColumns = Configuration::getInstance().memSpec->NumberOfColumns; + burstLenght = Configuration::getInstance().memSpec->burstLength; + numberOfColumns = Configuration::getInstance().memSpec->numberOfColumns; bytesPerColumn = AddressDecoder::getInstance().amount.bytes; // Adjust number of bytes per column dynamically to the selected ecc controller bytesPerColumn = Configuration::getInstance().adjustNumBytesAfterECC( bytesPerColumn); - numberOfRows = Configuration::getInstance().memSpec->NumberOfRows; + numberOfRows = Configuration::getInstance().memSpec->numberOfRows; numberOfBitErrorEvents = 0; @@ -253,7 +253,7 @@ void errorModel::markBitFlips() { double temp = getTemperature(); for (unsigned int row = 0; - row < Configuration::getInstance().memSpec->NumberOfRows; row++) { + row < Configuration::getInstance().memSpec->numberOfRows; row++) { // If the row has never been accessed ignore it and go to the next one if (lastRowAccess[row] != SC_ZERO_TIME) { // Get the time interval between now and the last acivate/refresh @@ -497,8 +497,8 @@ double errorModel::getTemperature() if (thermalSim == true && powerAnalysis == true) { // TODO // check if this is best way to request information to DRAMPower. - unsigned long long clk_cycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); + unsigned long long clk_cycles = sc_time_stamp() / + Configuration::getInstance().memSpec->tCK; DRAMPower->calcWindowEnergy(clk_cycles); float average_power = (float)DRAMPower->getPower().average_power; temperature = TemperatureController::getInstance().getTemperature( @@ -514,7 +514,7 @@ double errorModel::getTemperature() void errorModel::parseInputData() { - std::string fileName = Configuration::getInstance().ErrorCSVFile; + std::string fileName = Configuration::getInstance().errorCSVFile; std::ifstream inputFile(fileName); if (inputFile.is_open()) { diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index f275e057..7f80a9ff 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -37,7 +37,6 @@ #include "Arbiter.h" -using namespace std; using namespace tlm; Arbiter::Arbiter(sc_module_name name) : @@ -48,10 +47,10 @@ Arbiter::Arbiter(sc_module_name name) : // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; ++i) + for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; ++i) { channelIsFree.push_back(true); - pendingRequests.push_back(queue()); + pendingRequests.push_back(std::queue()); nextPayloadID.push_back(0); } @@ -68,13 +67,14 @@ Arbiter::Arbiter(sc_module_name name) : tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, tlm_phase &phase, sc_time &fwDelay) { - sc_time notDelay = clkAlign(sc_time_stamp() + fwDelay) - - (sc_time_stamp() + fwDelay); + sc_time notDelay = std::ceil((sc_time_stamp() + fwDelay) / Configuration::getInstance().memSpec->tCK) + * Configuration::getInstance().memSpec->tCK - sc_time_stamp(); + if (phase == BEGIN_REQ) { // adjust address offset: payload.set_address(payload.get_address() - - Configuration::getInstance().AddressOffset); + Configuration::getInstance().addressOffset); // In the begin request phase the socket ID is appended to the payload. // It will extracted from the payload and used later. @@ -83,7 +83,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, } else if (phase == END_RESP) { - notDelay += Configuration::getInstance().memSpec->clk; + notDelay += Configuration::getInstance().memSpec->tCK; payload.release(); } @@ -112,7 +112,7 @@ unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) { // adjust address offset: trans.set_address(trans.get_address() - - Configuration::getInstance().AddressOffset); + Configuration::getInstance().addressOffset); DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress( trans.get_address()); @@ -127,7 +127,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // Check the valid range of initiatorSocket ID and channel Id // TODO: initiatorSocket ID not checked - assert(channelId < Configuration::getInstance().NumberOfMemChannels); + assert(channelId < Configuration::getInstance().numberOfMemChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index b8576eda..907a8fcf 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -48,12 +48,8 @@ #include #include "../common/XmlAddressDecoder.h" #include "../common/dramExtensions.h" -#include "../common/timingCalculations.h" #include "../configuration/ConfigurationLoader.h" -using namespace std; -using namespace tlm; - class Arbiter : public sc_module { public: @@ -66,36 +62,36 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; - vector channelIsFree; + std::vector channelIsFree; // used to account for the request_accept_delay in the dram controllers // This is a queue of new transactions. The phase of a new request is BEGIN_REQ. - vector> pendingRequests; + std::vector> pendingRequests; // used to account for the response_accept_delay in the initiators (traceplayer, core etc.) // This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP. - std::map> receivedResponses; + std::map> receivedResponses; // Initiated by initiator side // This function is called when an arbiter's target socket receives a transaction from a device - tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay); + tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &fwDelay); // Initiated by dram side // This function is called when an arbiter's initiator socket receives a transaction from a memory controller - tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay); + tlm::tlm_sync_enum nb_transport_bw(int channelId, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &bwDelay); virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans); - void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase); + void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase); - void sendToChannel(unsigned int channelId, tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay); + void sendToChannel(unsigned int channelId, tlm::tlm_generic_payload &payload, + const tlm::tlm_phase &phase, const sc_time &delay); - void sendToInitiator(unsigned int id, tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay); + void sendToInitiator(unsigned int id, tlm::tlm_generic_payload &payload, + const tlm::tlm_phase &phase, const sc_time &delay); - void appendDramExtension(int socketId, tlm_generic_payload &payload); + void appendDramExtension(int socketId, tlm::tlm_generic_payload &payload); std::vector nextPayloadID; bool addressIsValid(DecodedAddress &decodedAddress); diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index f705a6fc..7eabae3e 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -65,11 +65,9 @@ #include "../controller/Controller.h" #include "../controller/ControllerRecordable.h" -using namespace std; - DRAMSys::DRAMSys(sc_module_name name, - string simulationToRun, - string pathToResources) : sc_module(name), tSocket("DRAMSys_tSocket") + std::string simulationToRun, + std::string pathToResources) : sc_module(name), tSocket("DRAMSys_tSocket") { // Initialize ecc pointer ecc = nullptr; @@ -77,11 +75,11 @@ DRAMSys::DRAMSys(sc_module_name name, logo(); // Read Configuration Setup: - string memspec; - string mcconfig; - string amconfig; - string simconfig; - string thermalconfig; + std::string memspec; + std::string mcconfig; + std::string amconfig; + std::string simconfig; + std::string thermalconfig; // TODO: Setup never used? Setup setup(simulationToRun, @@ -134,12 +132,12 @@ DRAMSys::DRAMSys(sc_module_name name, AddressDecoder::getInstance().print(); // Setup the debug manager: - setupDebugManager(Configuration::getInstance().SimulationName); + setupDebugManager(Configuration::getInstance().simulationName); // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. std::string simName; - simName = Configuration::getInstance().SimulationName; + simName = Configuration::getInstance().simulationName; tinyxml2::XMLDocument simulationdoc; loadXML(simulationToRun, simulationdoc); tinyxml2::XMLElement *simulation = @@ -151,7 +149,7 @@ DRAMSys::DRAMSys(sc_module_name name, if (r != NULL) { std::string sid; sid = r; - simName = sid + '_' + Configuration::getInstance().SimulationName; + simName = sid + '_' + Configuration::getInstance().simulationName; } } } @@ -165,22 +163,22 @@ DRAMSys::DRAMSys(sc_module_name name, void DRAMSys::logo() { -#define REDTXT(s) string(("\033[0;31m"+string((s))+"\033[0m")) -#define BOLDBLUETXT(s) string(("\033[1;34m"+string((s))+"\033[0m")) - cout << endl; - cout << REDTXT(" |||") << endl; - cout << REDTXT(" +---+ Microelectronic Systems") << endl; - cout << REDTXT("=| |= Design Research Group") << endl; - cout << REDTXT("=| |= ") << BOLDBLUETXT("University of Kaiserslautern") - << endl; - cout << REDTXT(" +---+ ") << endl; - cout << REDTXT(" ||| ") << "DRAMSys v4.0" << endl; - cout << endl; +#define REDTXT(s) std::string("\033[0;31m"+std::string(s)+"\033[0m") +#define BOLDBLUETXT(s) std::string("\033[1;34m"+std::string(s)+"\033[0m") + std::cout << std::endl; + std::cout << REDTXT(" |||") << std::endl; + std::cout << REDTXT(" +---+ Microelectronic Systems") << std::endl; + std::cout << REDTXT("=| |= Design Research Group") << std::endl; + std::cout << REDTXT("=| |= ") << BOLDBLUETXT("University of Kaiserslautern") + << std::endl; + std::cout << REDTXT(" +---+ ") << std::endl; + std::cout << REDTXT(" ||| ") << "DRAMSys v4.0" << std::endl; + std::cout << std::endl; #undef REDTXT #undef BOLDBLUETXT } -void DRAMSys::setupDebugManager(const string &traceName __attribute__((unused))) +void DRAMSys::setupDebugManager(const std::string &traceName __attribute__((unused))) { #ifdef DEBUGGING auto &dbg = DebugManager::getInstance(); @@ -191,18 +189,18 @@ void DRAMSys::setupDebugManager(const string &traceName __attribute__((unused))) #endif } -void DRAMSys::setupTlmRecorders(const string &traceName, - const string &pathToResources) +void DRAMSys::setupTlmRecorders(const std::string &traceName, + const std::string &pathToResources) { // Create TLM Recorders, one per channel. for (size_t i = 0; - i < Configuration::getInstance().NumberOfMemChannels; + i < Configuration::getInstance().numberOfMemChannels; i++) { std::string sqlScriptURI = pathToResources - + string("scripts/createTraceDB.sql"); + + std::string("scripts/createTraceDB.sql"); std::string dbName = traceName - + string("_ch") + + std::string("_ch") + std::to_string(i) + ".tdb"; @@ -213,15 +211,15 @@ void DRAMSys::setupTlmRecorders(const string &traceName, tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri); tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri); - std::string traceNames = Configuration::getInstance().SimulationName; + std::string traceNames = Configuration::getInstance().simulationName; tlmRecorder->recordTracenames(traceNames); tlmRecorders.push_back(tlmRecorder); } } -void DRAMSys::instantiateModules(const string &traceName, - const string &pathToResources) +void DRAMSys::instantiateModules(const std::string &traceName, + const std::string &pathToResources) { // The first call to getInstance() creates the Temperature Controller. // The same instance will be accessed by all other modules. @@ -229,19 +227,17 @@ void DRAMSys::instantiateModules(const string &traceName, // Create and properly initialize TLM recorders. // They need to be ready before creating some modules. - bool recordingEnabled = Configuration::getInstance().DatabaseRecording; + bool recordingEnabled = Configuration::getInstance().databaseRecording; if (recordingEnabled) setupTlmRecorders(traceName, pathToResources); // Create new ECC Controller - switch (Configuration::getInstance().ECCMode) { - case ECCControllerMode::Hamming: + if (Configuration::getInstance().ECCMode == "Hamming") ecc = new ECCHamming("ECCHamming"); - break; - default: + else if (Configuration::getInstance().ECCMode == "Disabled") ecc = nullptr; - break; - } + else + SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode"); // Save ECC Controller into the configuration struct to adjust it dynamically Configuration::getInstance().pECC = ecc; @@ -250,12 +246,12 @@ void DRAMSys::instantiateModules(const string &traceName, arbiter = new Arbiter("arbiter"); // Create DRAM - std::string memoryType = Configuration::getInstance().memSpec->MemoryType; - for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) + std::string memoryType = Configuration::getInstance().memSpec->memoryType; + for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); - GenericController *controller; + ControllerIF *controller; if (recordingEnabled) controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]); else @@ -329,12 +325,11 @@ void DRAMSys::instantiateModules(const string &traceName, dram = new DramGDDR6(str.c_str()); } else - { SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); - } + drams.push_back(dram); - if (Configuration::getInstance().CheckTLM2Protocol) { + if (Configuration::getInstance().checkTLM2Protocol) { str = "TLMCheckerController" + std::to_string(i); tlm_utils::tlm2_base_protocol_checker<> *controllerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str()); @@ -346,17 +341,20 @@ void DRAMSys::instantiateModules(const string &traceName, void DRAMSys::bindSockets() { // If ECC Controller enabled, put it between Trace and arbiter - if (Configuration::getInstance().ECCMode != ECCControllerMode::Disabled) { + if (Configuration::getInstance().ECCMode == "Hamming") + { assert(ecc != nullptr); tSocket.bind(ecc->t_socket); ecc->i_socket.bind(arbiter->tSocket); - } else { - tSocket.bind(arbiter->tSocket); } + else if (Configuration::getInstance().ECCMode == "Disabled") + tSocket.bind(arbiter->tSocket); + else + SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode"); - if (Configuration::getInstance().CheckTLM2Protocol) { + if (Configuration::getInstance().checkTLM2Protocol) { for (size_t i = 0; - i < Configuration::getInstance().NumberOfMemChannels; + i < Configuration::getInstance().numberOfMemChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind( @@ -365,7 +363,7 @@ void DRAMSys::bindSockets() } } else { for (size_t i = 0; - i < Configuration::getInstance().NumberOfMemChannels; + i < Configuration::getInstance().numberOfMemChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); @@ -401,8 +399,8 @@ DRAMSys::~DRAMSys() } } -void DRAMSys::report(string message) +void DRAMSys::report(std::string message) { PRINTDEBUGMESSAGE(name(), message); - cout << message << endl; + std::cout << message << std::endl; } diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 354241f0..15410755 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -51,7 +51,7 @@ #include "../common/third_party/tinyxml2/tinyxml2.h" #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" -#include "../controller/GenericController.h" +#include "../controller/ControllerIF.h" #include "../common/TlmRecorder.h" class DRAMSys : public sc_module @@ -66,8 +66,8 @@ public: SC_HAS_PROCESS(DRAMSys); DRAMSys(sc_module_name name, - string simulationToRun, - string pathToResources); + std::string simulationToRun, + std::string pathToResources); ~DRAMSys(); @@ -87,8 +87,7 @@ private: // All transactions pass through the same arbiter Arbiter *arbiter; // Each DRAM unit has a controller - std::vector controllers; - //std::vector controllers; + std::vector controllers; // TODO: Each DRAM has a reorder buffer (check this!) ReorderBuffer *reorder; @@ -101,12 +100,12 @@ private: std::vector tlmRecorders; void report(std::string message); - void setupTlmRecorders(const string &traceName, - const string &pathToResources); - void instantiateModules(const string &traceName, - const string &pathToResources); + void setupTlmRecorders(const std::string &traceName, + const std::string &pathToResources); + void instantiateModules(const std::string &traceName, + const std::string &pathToResources); void bindSockets(); - void setupDebugManager(const string &traceName); + void setupDebugManager(const std::string &traceName); }; #endif // DRAMSYS_H diff --git a/DRAMSys/library/src/simulation/ExampleInitiator.h b/DRAMSys/library/src/simulation/ExampleInitiator.h index 45233838..1e0bbcd5 100644 --- a/DRAMSys/library/src/simulation/ExampleInitiator.h +++ b/DRAMSys/library/src/simulation/ExampleInitiator.h @@ -8,8 +8,6 @@ #include "../common/dramExtensions.h" #include "TracePlayer.h" -using namespace std; - struct ExampleInitiator : sc_module { // TLM-2 socket, defaults to 32-bits wide, base protocol diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 1ad91a0e..3747a1b0 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -46,9 +46,6 @@ #include #include "../configuration/ConfigurationLoader.h" -using namespace std; -using namespace tlm; - struct IArbiter : public sc_module { public: @@ -78,18 +75,18 @@ public: protected: // Initiated by initiator side // This function is called when an arbiter's target socket receives a transaction from a device - virtual tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay) = 0; + virtual tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &fwDelay) = 0; // Initiated by dram side // This function is called when an arbiter's initiator socket receives a transaction from a memory controller - virtual tlm_sync_enum nb_transport_bw(int channelId, - tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay) = 0; + virtual tlm::tlm_sync_enum nb_transport_bw(int channelId, + tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &bwDelay) = 0; virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) = 0; - void appendDramExtension(int socketId, tlm_generic_payload &payload) + void appendDramExtension(int socketId, tlm::tlm_generic_payload &payload) { // Append Generation Extension GenerationExtension *genExtension = new GenerationExtension(clkAlign( diff --git a/DRAMSys/library/src/simulation/MemoryManager.cpp b/DRAMSys/library/src/simulation/MemoryManager.cpp index f5dee080..e000fc3e 100644 --- a/DRAMSys/library/src/simulation/MemoryManager.cpp +++ b/DRAMSys/library/src/simulation/MemoryManager.cpp @@ -39,12 +39,7 @@ #include "../configuration/Configuration.h" #include -using namespace std; - -MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0) -{ - -} +MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0) {} MemoryManager::~MemoryManager() { diff --git a/DRAMSys/library/src/simulation/ReorderBuffer.h b/DRAMSys/library/src/simulation/ReorderBuffer.h index 5b10544c..d2d84077 100644 --- a/DRAMSys/library/src/simulation/ReorderBuffer.h +++ b/DRAMSys/library/src/simulation/ReorderBuffer.h @@ -40,11 +40,9 @@ #include #include +#include #include -using namespace std; -using namespace tlm; - struct ReorderBuffer: public sc_module { public: tlm_utils::simple_initiator_socket iSocket; @@ -60,43 +58,43 @@ public: private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; - deque pendingRequestsInOrder; - set receivedResponses; + std::deque pendingRequestsInOrder; + std::set receivedResponses; bool responseIsPendingInInitator; // Initiated by dram side - tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase, + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &bwDelay) { payloadEventQueue.notify(payload, phase, bwDelay); - return TLM_ACCEPTED; + return tlm::TLM_ACCEPTED; } // Initiated by initator side (players) - tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &fwDelay) { - if (phase == BEGIN_REQ) { + if (phase == tlm::BEGIN_REQ) { payload.acquire(); - } else if (phase == END_RESP) { + } else if (phase == tlm::END_RESP) { payload.release(); } payloadEventQueue.notify(payload, phase, fwDelay); - return TLM_ACCEPTED; + return tlm::TLM_ACCEPTED; } - void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) + void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) { //Phases initiated by initiator side - if (phase == BEGIN_REQ) { + if (phase == tlm::BEGIN_REQ) { pendingRequestsInOrder.push_back(&payload); sendToTarget(payload, phase, SC_ZERO_TIME ); } - else if (phase == END_RESP) { + else if (phase == tlm::END_RESP) { responseIsPendingInInitator = false; pendingRequestsInOrder.pop_front(); receivedResponses.erase(&payload); @@ -104,10 +102,10 @@ private: } //Phases initiated by dram side - else if (phase == END_REQ) { + else if (phase == tlm::END_REQ) { sendToInitiator(payload, phase, SC_ZERO_TIME); - } else if (phase == BEGIN_RESP) { - sendToTarget(payload, END_RESP, SC_ZERO_TIME); + } else if (phase == tlm::BEGIN_RESP) { + sendToTarget(payload, tlm::END_RESP, SC_ZERO_TIME); receivedResponses.emplace(&payload); sendNextResponse(); } @@ -119,24 +117,24 @@ private: } } - void sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase, + void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_time &delay) { - tlm_phase TPhase = phase; + tlm::tlm_phase TPhase = phase; sc_time TDelay = delay; iSocket->nb_transport_fw(payload, TPhase, TDelay); } - void sendToInitiator(tlm_generic_payload &payload, const tlm_phase &phase, + void sendToInitiator(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_time &delay) { - sc_assert(phase == END_REQ || - (phase == BEGIN_RESP && pendingRequestsInOrder.front() == &payload + sc_assert(phase == tlm::END_REQ || + (phase == tlm::BEGIN_RESP && pendingRequestsInOrder.front() == &payload && receivedResponses.count(&payload))); - tlm_phase TPhase = phase; + tlm::tlm_phase TPhase = phase; sc_time TDelay = delay; tSocket->nb_transport_bw(payload, TPhase, TDelay); } @@ -147,9 +145,9 @@ private: //has been received if (!responseIsPendingInInitator && receivedResponses.count(pendingRequestsInOrder.front())) { - tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); + tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; - sendToInitiator(*payloadToSend, BEGIN_RESP, SC_ZERO_TIME); + sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, SC_ZERO_TIME); } // else if(!responseIsPendingInInitator && receivedResponses.size()>0 && !receivedResponses.count(pendingRequestsInOrder.front())>0) // { diff --git a/DRAMSys/library/src/simulation/SimpleArbiter.h b/DRAMSys/library/src/simulation/SimpleArbiter.h index 5434576b..a61b9a66 100644 --- a/DRAMSys/library/src/simulation/SimpleArbiter.h +++ b/DRAMSys/library/src/simulation/SimpleArbiter.h @@ -40,10 +40,6 @@ #include "IArbiter.h" #include "../common/XmlAddressDecoder.h" #include "../common/dramExtensions.h" -#include "../controller/core/timingCalculations.h" - -using namespace std; -using namespace tlm; // Annotated References [X,Y] --> Please refer to TLM AT Cheat Sheet on README @@ -72,8 +68,8 @@ protected: TlmRecorder *tlmRecorder; // Initiated by initiator side // This function is called when an arbiter's target socket receives a transaction from a device - virtual tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay) + virtual tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &fwDelay) { if (phase == BEGIN_REQ) { payload.acquire(); @@ -100,13 +96,13 @@ protected: // 4-Phase Handshake [1.1] // 4-Phase Handshake [1.7] - return TLM_ACCEPTED; + return tlm::TLM_ACCEPTED; } // Initiated by dram side // This function is called when an arbiter's initiator socket receives a transaction from a memory controller - virtual tlm_sync_enum nb_transport_bw(int /*channelId*/, - tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay) + virtual tlm::tlm_sync_enum nb_transport_bw(int /*channelId*/, + tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &bwDelay) { tlmRecorder->recordPhase(payload, phase, bwDelay + sc_time_stamp()); @@ -117,10 +113,10 @@ protected: // Early Completion [3.1] tlmRecorder->recordPhase(payload, END_RESP, bwDelay + sc_time_stamp()); tlmRecorder->recordArbiterPhase(payload, BEGIN_RESP, sc_time_stamp() + bwDelay); - return TLM_COMPLETED; + return tlm::TLM_COMPLETED; } // 4-Phase Handshake [1.3] - return TLM_ACCEPTED; + return tlm::TLM_ACCEPTED; } virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) @@ -132,7 +128,7 @@ protected: return iSocket[getISocketIndex(trans)]->transport_dbg(trans); } - virtual unsigned int getISocketIndex(tlm_generic_payload &payload) + virtual unsigned int getISocketIndex(tlm::tlm_generic_payload &payload) { return DramExtension::getBank(payload).ID(); } diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index e45e1233..2ae960b7 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -43,31 +43,26 @@ #include "../common/XmlAddressDecoder.h" #include "TracePlayer.h" -using namespace std; -using namespace tlm; - template class StlPlayer : public TracePlayer { public: StlPlayer(sc_module_name name, - string pathToTrace, + std::string pathToTrace, sc_time playerClk, TracePlayerListener *listener) : TracePlayer(name, listener), file(pathToTrace) { if (!file.is_open()) - SC_REPORT_FATAL(0, (string("Could not open trace ") + pathToTrace).c_str()); + SC_REPORT_FATAL(0, (std::string("Could not open trace ") + pathToTrace).c_str()); this->playerClk = playerClk; - this->burstlength = Configuration::getInstance().memSpec->BurstLength; + this->burstlength = Configuration::getInstance().memSpec->burstLength; this->dataLength = Configuration::getInstance().getBytesPerBurst(); this->lineCnt = 0; } - - void nextPayload() { std::string line; @@ -95,10 +90,10 @@ public: // Trace files MUST provide timestamp, command and address for every // transaction. The data information depends on the storage mode // configuration. - string time; - string command; - string address; - string dataStr; + std::string time; + std::string command; + std::string address; + std::string dataStr; std::istringstream iss(line); @@ -106,7 +101,7 @@ public: iss >> time; if (time.empty()) SC_REPORT_FATAL("StlPlayer", - ("Malformed trace file. Timestamp could not be found (line " + to_string( + ("Malformed trace file. Timestamp could not be found (line " + std::to_string( lineCnt) + ").").c_str()); sc_time sendingTime = std::stoull(time.c_str()) * playerClk; @@ -114,41 +109,41 @@ public: iss >> command; if (command.empty()) SC_REPORT_FATAL("StlPlayer", - ("Malformed trace file. Command could not be found (line " + to_string( + ("Malformed trace file. Command could not be found (line " + std::to_string( lineCnt) + ").").c_str()); - enum tlm_command cmd; + enum tlm::tlm_command cmd; if (command == "read") { - cmd = TLM_READ_COMMAND; + cmd = tlm::TLM_READ_COMMAND; } else if (command == "write") { - cmd = TLM_WRITE_COMMAND; + cmd = tlm::TLM_WRITE_COMMAND; } else { SC_REPORT_FATAL("StlPlayer", - (string("Corrupted tracefile, command ") + command + - string(" unknown")).c_str()); + (std::string("Corrupted tracefile, command ") + command + + std::string(" unknown")).c_str()); } // Get the address. iss >> address; if (address.empty()) SC_REPORT_FATAL("StlPlayer", - ("Malformed trace file. Address could not be found (line " + to_string( + ("Malformed trace file. Address could not be found (line " + std::to_string( lineCnt) + ").").c_str()); unsigned long long addr = std::stoull(address.c_str(), 0, 16); // Get the data if necessary. - if (Configuration::getInstance().StoreMode != StorageMode::NoStorage - && cmd != TLM_READ_COMMAND) { + if (storageEnabled && cmd == tlm::TLM_WRITE_COMMAND) + { // The input trace file must provide the data to be stored into the memory. iss >> dataStr; if (dataStr.empty()) SC_REPORT_FATAL("StlPlayer", - ("Malformed trace file. Data information could not be found (line " + to_string( + ("Malformed trace file. Data information could not be found (line " + std::to_string( lineCnt) + ").").c_str()); // Check if data length in the trace file is correct. We need two characters to represent 1 byte in hexadecimal. if (dataStr.length() != (dataLength * 2)) SC_REPORT_FATAL("StlPlayer", - ("Data in the trace file has an invalid length (line " + to_string( + ("Data in the trace file has an invalid length (line " + std::to_string( lineCnt) + ").").c_str()); // Set data @@ -158,7 +153,7 @@ public: // Fill up the payload. payload->set_address(addr); - payload->set_response_status(TLM_INCOMPLETE_RESPONSE); + payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); payload->set_dmi_allowed(false); payload->set_byte_enable_length(0); payload->set_streaming_width(burstlength); @@ -170,17 +165,17 @@ public: { // Send the transaction directly or schedule it to be sent in the future. if (sendingTime <= sc_time_stamp()) - this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME); + this->payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, SC_ZERO_TIME); else - this->payloadEventQueue.notify(*payload, BEGIN_REQ, + this->payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, sendingTime - sc_time_stamp()); } else - payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime); + payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, sendingTime); } private: - ifstream file; + std::ifstream file; unsigned int lineCnt; unsigned int burstlength; diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index aeb02e00..a0ecc5b3 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -61,7 +61,7 @@ public: SC_CTOR(TemperatureController) { temperatureScale = Configuration::getInstance().temperatureSim.TemperatureScale; - dynamicTempSimEnabled = Configuration::getInstance().ThermalSimulation; + dynamicTempSimEnabled = Configuration::getInstance().thermalSimulation; staticTemperature = Configuration::getInstance().temperatureSim.StaticTemperatureDefaultValue; diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index 4631c5a9..29eaf26e 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -40,21 +40,18 @@ #include "TracePlayer.h" -using namespace std; -using namespace tlm; - struct TraceGenerator : public TracePlayer { public: - TraceGenerator(sc_module_name name, unsigned int clkMhz, TracePlayerListener *listener) + TraceGenerator(sc_module_name name, unsigned int fCKMhz, TracePlayerListener *listener) : TracePlayer(name, listener), transCounter(0) { - if (clkMhz == 0) - clk = Configuration::getInstance().memSpec->clk; + if (fCKMhz == 0) + tCK = Configuration::getInstance().memSpec->tCK; else - clk = FrequencyToClk(clkMhz); + tCK = sc_time(1.0 / fCKMhz, SC_US); - this->burstlenght = Configuration::getInstance().memSpec->BurstLength; + this->burstlenght = Configuration::getInstance().memSpec->burstLength; } virtual void nextPayload() override @@ -69,20 +66,20 @@ public: char[16]; // TODO: column / burst breite payload->set_address(0x0); - payload->set_response_status(TLM_INCOMPLETE_RESPONSE); + payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); payload->set_dmi_allowed(false); payload->set_byte_enable_length(0); payload->set_streaming_width(this->burstlenght); payload->set_data_ptr(dataElement); payload->set_data_length(16); - payload->set_command(TLM_READ_COMMAND); + payload->set_command(tlm::TLM_READ_COMMAND); transCounter++; - this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME); + this->payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, SC_ZERO_TIME); } private: unsigned int burstlenght; - sc_time clk; + sc_time tCK; unsigned int transCounter; }; diff --git a/DRAMSys/library/src/simulation/TracePlayer.cpp b/DRAMSys/library/src/simulation/TracePlayer.cpp index f9aa8fb6..025221d7 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.cpp +++ b/DRAMSys/library/src/simulation/TracePlayer.cpp @@ -38,16 +38,17 @@ #include "TracePlayer.h" +using namespace tlm; + TracePlayer::TracePlayer(sc_module_name name, TracePlayerListener *listener) : sc_module(name), payloadEventQueue(this, &TracePlayer::peqCallback), - numberOfTransactions(0), - transactionsSent(0), - transactionsReceived(0), - listener(listener), - finished(false) + listener(listener) { iSocket.register_nb_transport_bw(this, &TracePlayer::nb_transport_bw); + + if (Configuration::getInstance().storeMode != "NoStorage") + storageEnabled = true; } gp *TracePlayer::allocatePayload() @@ -85,7 +86,7 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, } else if (phase == BEGIN_RESP) { payload.release(); sendToTarget(payload, END_RESP, SC_ZERO_TIME); - if (Configuration::getInstance().SimulationProgressBar) + if (Configuration::getInstance().simulationProgressBar) listener->transactionFinished(); transactionsReceived++; @@ -113,7 +114,7 @@ void TracePlayer::setNumberOfTransactions(unsigned int n) numberOfTransactions = n; } -unsigned int TracePlayer::getNumberOfLines(string pathToTrace) +unsigned int TracePlayer::getNumberOfLines(std::string pathToTrace) { // Reference: http://stackoverflow.com/questions/3482064/counting-the-number-of-lines-in-a-text-file ifstream newFile; diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index b866e5ce..6eabd60c 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -50,19 +50,15 @@ #include "../configuration/Configuration.h" #include "../common/DebugManager.h" #include "../common/XmlAddressDecoder.h" -#include "../common/timingCalculations.h" #include "TracePlayerListener.h" -using namespace std; -using namespace tlm; - struct TracePlayer : public sc_module { public: tlm_utils::simple_initiator_socket iSocket; TracePlayer(sc_module_name name, TracePlayerListener *listener); virtual void nextPayload() = 0; - unsigned int getNumberOfLines(string pathToTrace); + unsigned int getNumberOfLines(std::string pathToTrace); protected: gp *allocatePayload(); @@ -70,19 +66,20 @@ protected: void finish(); void terminate(); void setNumberOfTransactions(unsigned int n); - unsigned int numberOfTransactions; + unsigned int numberOfTransactions = 0; + bool storageEnabled; private: - tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase, + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &bwDelay); - void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase); - void sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase, + void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase); + void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_time &delay); MemoryManager memoryManager; - unsigned int transactionsSent; - unsigned int transactionsReceived; + unsigned int transactionsSent = 0; + unsigned int transactionsReceived = 0; TracePlayerListener *listener; - bool finished; + bool finished = false; }; #endif // TRACEPLAYER_H diff --git a/DRAMSys/library/src/simulation/TracePlayerListener.h b/DRAMSys/library/src/simulation/TracePlayerListener.h index 430c10a0..b05ccd74 100644 --- a/DRAMSys/library/src/simulation/TracePlayerListener.h +++ b/DRAMSys/library/src/simulation/TracePlayerListener.h @@ -43,7 +43,7 @@ class TracePlayerListener public: virtual void tracePlayerTerminates() = 0; virtual void transactionFinished() = 0; - virtual ~TracePlayerListener() {}; + virtual ~TracePlayerListener() {} }; #endif // TRACEPLAYERLISTENER_H diff --git a/DRAMSys/library/src/simulation/TraceSetup.cpp b/DRAMSys/library/src/simulation/TraceSetup.cpp index 79a241d6..778b25ac 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.cpp +++ b/DRAMSys/library/src/simulation/TraceSetup.cpp @@ -35,7 +35,7 @@ #include "TraceSetup.h" -traceSetup::traceSetup(std::string uri, +TraceSetup::TraceSetup(std::string uri, std::string pathToResources, std::vector *devices) { @@ -61,13 +61,12 @@ traceSetup::traceSetup(std::string uri, device = device->NextSiblingElement("device")) { sc_time playerClk; - unsigned int frequency = device->IntAttribute("clkMhz"); + unsigned int frequencyMHz = device->IntAttribute("clkMhz"); - if (frequency == 0) { + if (frequencyMHz == 0) reportFatal("traceSetup", "No Frequency Defined"); - } else { - playerClk = FrequencyToClk(frequency); - } + else + playerClk = sc_time(1.0 / frequencyMHz, SC_US); std::string name = device->GetText(); @@ -80,7 +79,7 @@ traceSetup::traceSetup(std::string uri, std::string ext = name.substr(pos + 1); std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); - std::string stlFile = pathToResources + string("traces/") + name; + std::string stlFile = pathToResources + std::string("traces/") + name; std::string moduleName = name; // replace all '.' to '_' @@ -97,30 +96,30 @@ traceSetup::traceSetup(std::string uri, } devices->push_back(player); - if (Configuration::getInstance().SimulationProgressBar) { + if (Configuration::getInstance().simulationProgressBar) { totalTransactions += player->getNumberOfLines(stlFile); } } remainingTransactions = totalTransactions; - NumberOfTracePlayers = devices->size(); + numberOfTracePlayers = devices->size(); } -void traceSetup::tracePlayerTerminates() +void TraceSetup::tracePlayerTerminates() { finishedTracePlayers++; - if (finishedTracePlayers == NumberOfTracePlayers) { + if (finishedTracePlayers == numberOfTracePlayers) { sc_stop(); } } -void traceSetup::transactionFinished() +void TraceSetup::transactionFinished() { remainingTransactions--; loadbar(totalTransactions - remainingTransactions, totalTransactions); if (remainingTransactions == 0) { - cout << endl; + std::cout << std::endl; } } diff --git a/DRAMSys/library/src/simulation/TraceSetup.h b/DRAMSys/library/src/simulation/TraceSetup.h index 49f91049..a65ae1f2 100644 --- a/DRAMSys/library/src/simulation/TraceSetup.h +++ b/DRAMSys/library/src/simulation/TraceSetup.h @@ -44,19 +44,19 @@ #include "StlPlayer.h" -class traceSetup : public TracePlayerListener +class TraceSetup : public TracePlayerListener { public: - traceSetup(std::string uri, + TraceSetup(std::string uri, std::string pathToResources, std::vector *devices); virtual void tracePlayerTerminates() override; virtual void transactionFinished() override; - virtual ~traceSetup() {}; + virtual ~TraceSetup() {} private: - unsigned int NumberOfTracePlayers; + unsigned int numberOfTracePlayers; unsigned int totalTransactions = 0; unsigned int remainingTransactions; unsigned int finishedTracePlayers = 0; diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index b23e9c58..feaea294 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -54,26 +54,34 @@ #include #include "../../common/DebugManager.h" #include "../../common/dramExtensions.h" -#include "../../common/timingCalculations.h" #include "../../configuration/Configuration.h" -#include "../../common/protocol.h" #include "../../common/utils.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../common/third_party/DRAMPower/src/MemCommand.h" +#include "../../controller/Command.h" using namespace tlm; using namespace DRAMPower; Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") { + Configuration &config = Configuration::getInstance(); // Adjust number of bytes per burst dynamically to the selected ecc controller - // TODO: ECC only used for WideIO? - bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerBurst); + bytesPerBurst = config.adjustNumBytesAfterECC(bytesPerBurst); + + if (config.storeMode == "NoStorage") + storeMode = StorageMode::NoStorage; + else if (config.storeMode == "Store") + storeMode = StorageMode::Store; + else if (config.storeMode == "ErrorModel") + storeMode = StorageMode::ErrorModel; + else + SC_REPORT_FATAL(this->name(), "Unsupported storage mode"); uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes(); - if (StoreMode == StorageMode::Store) + if (storeMode == StorageMode::Store) { - if (Configuration::getInstance().UseMalloc) + if (Configuration::getInstance().useMalloc) { memory = (unsigned char *)malloc(memorySize); if (!memory) @@ -97,13 +105,9 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") Dram::~Dram() { - if (Configuration::getInstance().PowerAnalysis) + if (Configuration::getInstance().powerAnalysis) { - libDRAMPower *DRAMPower = dynamic_cast(this->DRAMPower); - if (DRAMPower == nullptr) - SC_REPORT_FATAL("Dram", "Power Analysis active but libDRAMPowerIF instantiated"); - - if (!Configuration::getInstance().DatabaseRecording) + if (!Configuration::getInstance().databaseRecording) DRAMPower->calcEnergy(); // Print the final total energy and the average power for @@ -111,130 +115,47 @@ Dram::~Dram() std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().NumberOfDevicesOnDIMM + * Configuration::getInstance().numberOfDevicesOnDIMM << std::string(" pJ") << std::endl; std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getPower().average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM + * Configuration::getInstance().numberOfDevicesOnDIMM << std::string(" mW") << std::endl; - } - delete DRAMPower; - if (Configuration::getInstance().UseMalloc) + delete DRAMPower; + } + + if (Configuration::getInstance().useMalloc) free(memory); } tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay) + tlm_phase &phase, sc_time &) { - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + assert(phase >= 5 && phase <= 19); - // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); + if (Configuration::getInstance().powerAnalysis) + { + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned long long cycle = sc_time_stamp() / memSpec->tCK; + DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); + } - if (phase == BEGIN_PRE) + if (storeMode == StorageMode::Store) { - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); - } - else if (phase == BEGIN_PREA) - { - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - sendToController(payload, END_PREA, - delay + memSpec->getExecutionTime(Command::PREA, payload)); - } - else if (phase == BEGIN_ACT) - { - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); - } - else if (phase == BEGIN_WR) - { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); - // save data: - if (StoreMode == StorageMode::Store) // Use Storage - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); - } - else if (phase == BEGIN_RD) - { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); - // load data: - if (StoreMode == StorageMode::Store) // use StorageMode + if (phase == BEGIN_RD || phase == BEGIN_RDA) { unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); - } - else if (phase == BEGIN_WRA) - { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); - // save data: - if (StoreMode == StorageMode::Store) // Use Storage + else if (phase == BEGIN_WR || phase == BEGIN_WRA) { unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); - } - else if (phase == BEGIN_RDA) - { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); - // Load data: - if (StoreMode == StorageMode::Store) // use StorageMode - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); - } - else if (phase == BEGIN_REFA) - { - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA, payload)); - } - else if (phase == BEGIN_REFB) - { - DRAMPower->doCommand(MemCommand::REFB, bank, cycle); - sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFB, payload)); - } - // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length - else if (phase == BEGIN_PDNA) - { - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); - } - else if (phase == END_PDNA) - { - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); - } - else if (phase == BEGIN_PDNP) - { - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); - } - else if (phase == END_PDNP) - { - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); - } - else if (phase == BEGIN_SREF) - { - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); - } - else if (phase == END_SREF) - { - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); - } - else - { - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); } return TLM_ACCEPTED; @@ -245,7 +166,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans) PRINTDEBUGMESSAGE(name(), "transport_dgb"); // TODO: This part is not tested yet, neither with traceplayers nor with GEM5 coupling - if (StoreMode == StorageMode::NoStorage) + if (storeMode == StorageMode::NoStorage) { SC_REPORT_FATAL("DRAM", "Debug Transport is used in combination with NoStorage"); @@ -262,7 +183,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans) if (cmd == TLM_READ_COMMAND) { - if (StoreMode == StorageMode::Store) + if (storeMode == StorageMode::Store) { // Use Storage unsigned char *phyAddr = memory + trans.get_address(); memcpy(ptr, phyAddr, trans.get_data_length()); @@ -275,7 +196,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans) } else if (cmd == TLM_WRITE_COMMAND) { - if (StoreMode == StorageMode::Store) + if (storeMode == StorageMode::Store) { // Use Storage unsigned char *phyAddr = memory + trans.get_address(); memcpy(phyAddr, ptr, trans.get_data_length()); @@ -290,11 +211,3 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans) } return 0; } - -void Dram::sendToController(tlm_generic_payload &payload, const tlm_phase &phase, - const sc_time &delay) -{ - tlm_phase TPhase = phase; - sc_time TDelay = delay; - tSocket->nb_transport_bw(payload, TPhase, TDelay); -} diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index e317768c..04a286f9 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -43,15 +43,10 @@ #include #include #include -#include "../../common/protocol.h" #include "../../configuration/Configuration.h" #include "../../configuration/memspec/MemSpec.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -using namespace std; -using namespace tlm; -using namespace DRAMPower; - class Dram : public sc_module { private: @@ -64,18 +59,16 @@ protected: MemSpec *memSpec = Configuration::getInstance().memSpec; // Data Storage: - StorageMode StoreMode = Configuration::getInstance().StoreMode; + enum class StorageMode {NoStorage, Store, ErrorModel} storeMode; + unsigned char *memory; - libDRAMPowerDummy *DRAMPower; + libDRAMPower *DRAMPower; - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay); + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &delay); - virtual unsigned int transport_dbg(tlm_generic_payload &trans); - - void sendToController(tlm_generic_payload &payload, const tlm_phase &phase, - const sc_time &delay); + virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans); public: tlm_utils::simple_target_socket tSocket; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index bcdb03eb..0e785ae2 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -40,72 +40,71 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecDDR3.h" +using namespace DRAMPower; + DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); - // Parameters for DRAMPower - MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) + if (Configuration::getInstance().powerAnalysis) { - sc_time clk = memSpec->clk; + MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.dataRate = memSpec->dataRate; + memArchSpec.nbrOfRows = memSpec->numberOfRows; + memArchSpec.nbrOfBanks = memSpec->numberOfBanks; + memArchSpec.nbrOfColumns = memSpec->numberOfColumns; + memArchSpec.nbrOfRanks = memSpec->numberOfRanks; memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups; memArchSpec.twoVoltageDomains = false; memArchSpec.dll = true; MemTimingSpec memTimingSpec; - //FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk; - //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; - //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; - //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; - //FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk; - //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; - //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD / clk; - memTimingSpec.CCD_L = memSpec->tCCD / clk; - memTimingSpec.CCD_S = memSpec->tCCD / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; + //FIXME: memTimingSpec.FAWB = memSpec->tFAW / memSpec->tCK; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / memSpec->tCK; + //FIXME: memTimingSpec.RCB = memSpec->tRC / memSpec->tCK; + //FIXME: memTimingSpec.RPB = memSpec->tRP / memSpec->tCK; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD / memSpec->tCK; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / memSpec->tCK; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / memSpec->tCK; + memTimingSpec.AL = memSpec->tAL / memSpec->tCK; + memTimingSpec.CCD = memSpec->tCCD / memSpec->tCK; + memTimingSpec.CCD_L = memSpec->tCCD / memSpec->tCK; + memTimingSpec.CCD_S = memSpec->tCCD / memSpec->tCK; + memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK; + memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK; + memTimingSpec.clkMhz = memSpec->fCKMHz; // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tFAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD / clk; - memTimingSpec.RRD_L = memSpec->tRRD / clk; - memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tFAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR / clk; - memTimingSpec.WTR_L = memSpec->tWTR / clk; - memTimingSpec.WTR_S = memSpec->tWTR / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + memTimingSpec.clkPeriod = 1000.0 / memSpec->fCKMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / memSpec->tCK; + memTimingSpec.FAW = memSpec->tFAW / memSpec->tCK; + memTimingSpec.RAS = memSpec->tRAS / memSpec->tCK; + memTimingSpec.RC = memSpec->tRC / memSpec->tCK; + memTimingSpec.RCD = memSpec->tRCD / memSpec->tCK; + memTimingSpec.REFI = memSpec->tREFI / memSpec->tCK; + memTimingSpec.RFC = memSpec->tRFC / memSpec->tCK; + memTimingSpec.RL = memSpec->tRL / memSpec->tCK; + memTimingSpec.RP = memSpec->tRP / memSpec->tCK; + memTimingSpec.RRD = memSpec->tRRD / memSpec->tCK; + memTimingSpec.RRD_L = memSpec->tRRD / memSpec->tCK; + memTimingSpec.RRD_S = memSpec->tRRD / memSpec->tCK; + memTimingSpec.RTP = memSpec->tRTP / memSpec->tCK; + memTimingSpec.TAW = memSpec->tFAW / memSpec->tCK; + memTimingSpec.WL = memSpec->tWL / memSpec->tCK; + memTimingSpec.WR = memSpec->tWR / memSpec->tCK; + memTimingSpec.WTR = memSpec->tWTR / memSpec->tCK; + memTimingSpec.WTR_L = memSpec->tWTR / memSpec->tCK; + memTimingSpec.WTR_S = memSpec->tWTR / memSpec->tCK; + memTimingSpec.XP = memSpec->tXP / memSpec->tCK; + memTimingSpec.XPDLL = memSpec->tXPDLL / memSpec->tCK; + memTimingSpec.XS = memSpec->tXS / memSpec->tCK; + memTimingSpec.XSDLL = memSpec->tXSDLL / memSpec->tCK; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; @@ -134,14 +133,12 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memPowerSpec.vdd2 = 0; MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; + powerSpec.id = memSpec->memoryId; + powerSpec.memoryType = memSpec->memoryType; powerSpec.memTimingSpec = memTimingSpec; powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; DRAMPower = new libDRAMPower(powerSpec, 0); } - else - DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 7fb03743..0ed29672 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -40,72 +40,71 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecDDR4.h" +using namespace DRAMPower; + DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); - // Parameters for DRAMPower - MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) + if (Configuration::getInstance().powerAnalysis) { - sc_time clk = memSpec->clk; + MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.dataRate = memSpec->dataRate; + memArchSpec.nbrOfRows = memSpec->numberOfRows; + memArchSpec.nbrOfBanks = memSpec->numberOfBanks; + memArchSpec.nbrOfColumns = memSpec->numberOfColumns; + memArchSpec.nbrOfRanks = memSpec->numberOfRanks; memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups; memArchSpec.twoVoltageDomains = true; memArchSpec.dll = true; MemTimingSpec memTimingSpec; - //FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk; - //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; - //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; - //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; - //FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / clk; - //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / clk; - //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / clk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; + //FIXME: memTimingSpec.FAWB = memSpec->tFAW / memSpec->tCK; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / memSpec->tCK; + //FIXME: memTimingSpec.RCB = memSpec->tRC / memSpec->tCK; + //FIXME: memTimingSpec.RPB = memSpec->tRP / memSpec->tCK; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / memSpec->tCK; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / memSpec->tCK; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / memSpec->tCK; + memTimingSpec.AL = memSpec->tAL / memSpec->tCK; + memTimingSpec.CCD = memSpec->tCCD_S / memSpec->tCK; + memTimingSpec.CCD_L = memSpec->tCCD_L / memSpec->tCK; + memTimingSpec.CCD_S = memSpec->tCCD_S / memSpec->tCK; + memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK; + memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK; + memTimingSpec.clkMhz = memSpec->fCKMHz; // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tFAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tFAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + memTimingSpec.clkPeriod = 1000.0 / memSpec->fCKMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / memSpec->tCK; + memTimingSpec.FAW = memSpec->tFAW / memSpec->tCK; + memTimingSpec.RAS = memSpec->tRAS / memSpec->tCK; + memTimingSpec.RC = memSpec->tRC / memSpec->tCK; + memTimingSpec.RCD = memSpec->tRCD / memSpec->tCK; + memTimingSpec.REFI = memSpec->tREFI / memSpec->tCK; + memTimingSpec.RFC = memSpec->tRFC / memSpec->tCK; + memTimingSpec.RL = memSpec->tRL / memSpec->tCK; + memTimingSpec.RP = memSpec->tRP / memSpec->tCK; + memTimingSpec.RRD = memSpec->tRRD_S / memSpec->tCK; + memTimingSpec.RRD_L = memSpec->tRRD_L / memSpec->tCK; + memTimingSpec.RRD_S = memSpec->tRRD_S / memSpec->tCK; + memTimingSpec.RTP = memSpec->tRTP / memSpec->tCK; + memTimingSpec.TAW = memSpec->tFAW / memSpec->tCK; + memTimingSpec.WL = memSpec->tWL / memSpec->tCK; + memTimingSpec.WR = memSpec->tWR / memSpec->tCK; + memTimingSpec.WTR = memSpec->tWTR_S / memSpec->tCK; + memTimingSpec.WTR_L = memSpec->tWTR_L / memSpec->tCK; + memTimingSpec.WTR_S = memSpec->tWTR_S / memSpec->tCK; + memTimingSpec.XP = memSpec->tXP / memSpec->tCK; + memTimingSpec.XPDLL = memSpec->tXPDLL / memSpec->tCK; + memTimingSpec.XS = memSpec->tXS / memSpec->tCK; + memTimingSpec.XSDLL = memSpec->tXSDLL / memSpec->tCK; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; @@ -134,14 +133,12 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memPowerSpec.vdd2 = memSpec->vDD2; MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; + powerSpec.id = memSpec->memoryId; + powerSpec.memoryType = memSpec->memoryType; powerSpec.memTimingSpec = memTimingSpec; powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; DRAMPower = new libDRAMPower(powerSpec, 0); } - else - DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp index 3e580346..3d5f2e48 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp @@ -42,16 +42,9 @@ DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5"); - // Parameters for DRAMPower - MemSpecGDDR5 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramGDDR5", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) - SC_REPORT_FATAL("DramGDDR5", "DRAMPower not supported for GDDR5"); - else - DRAMPower = new libDRAMPowerDummy(); + if (Configuration::getInstance().powerAnalysis) + SC_REPORT_FATAL("DramGDDR5", "DRAMPower does not support GDDR5"); } diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp index a3f492e7..48105864 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp @@ -42,16 +42,9 @@ DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X"); - // Parameters for DRAMPower - MemSpecGDDR5X *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramGDDR5X", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) - SC_REPORT_FATAL("DramGDDR5X", "DRAMPower not supported for GDDR5X"); - else - DRAMPower = new libDRAMPowerDummy(); + if (Configuration::getInstance().powerAnalysis) + SC_REPORT_FATAL("DramGDDR5X", "DRAMPower does not support GDDR5X"); } diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp index 8260db52..9ff895ee 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp @@ -42,16 +42,9 @@ DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6"); - // Parameters for DRAMPower - MemSpecGDDR6 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramGDDR6", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) - SC_REPORT_FATAL("DramGDDR6", "DRAMPower not supported for GDDR6"); - else - DRAMPower = new libDRAMPowerDummy(); + if (Configuration::getInstance().powerAnalysis) + SC_REPORT_FATAL("DramGDDR6", "DRAMPower does not support GDDR6"); } diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp index 3ee73ea0..395ca2da 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp @@ -42,16 +42,9 @@ DramHBM2::DramHBM2(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2"); - // Parameters for DRAMPower - MemSpecHBM2 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramHBM2", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) - SC_REPORT_FATAL("DramHBM2", "DRAMPower not supported for HBM2"); - else - DRAMPower = new libDRAMPowerDummy(); + if (Configuration::getInstance().powerAnalysis) + SC_REPORT_FATAL("DramHBM2", "DRAMPower does not support HBM2"); } diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp index 38df1da5..3587606c 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp @@ -42,16 +42,9 @@ DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4"); - // Parameters for DRAMPower - MemSpecLPDDR4 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramLPDDR4", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) - SC_REPORT_FATAL("DramLPDDR4", "DRAMPower not supported for LPDDR4"); - else - DRAMPower = new libDRAMPowerDummy(); + if (Configuration::getInstance().powerAnalysis) + SC_REPORT_FATAL("DramLPDDR4", "DRAMPower does not support LPDDR4"); } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 97c03e38..d1a8df14 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -57,24 +57,19 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe { // Create a thread that is triggered every $powerWindowSize // to generate a Power over Time plot in the Trace analyzer: - if (Configuration::getInstance().PowerAnalysis) - { - DRAMPower = dynamic_cast(Dram::DRAMPower); - if (DRAMPower == nullptr) - SC_REPORT_FATAL("DramRecordable", "Power Analysis active but libDRAMPowerIF instantiated"); + if (Configuration::getInstance().powerAnalysis) SC_THREAD(powerWindow); - } } template DramRecordable::~DramRecordable() { - if (Configuration::getInstance().PowerAnalysis) + if (Configuration::getInstance().powerAnalysis) { - DRAMPower->calcEnergy(); + this->DRAMPower->calcEnergy(); tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM); + this->DRAMPower->getPower().window_average_power + * Configuration::getInstance().numberOfDevicesOnDIMM); } tlmRecorder->closeConnection(); } @@ -83,35 +78,43 @@ template tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - // Recording time used by the traceAnalyzer + recordPhase(payload, phase, delay); + return BaseDram::nb_transport_fw(payload, phase, delay); +} + +template +void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) +{ sc_time recTime = sc_time_stamp() + delay; // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. - if (phase == END_PDNA || phase == END_PDNAB) - recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); - else if (phase == END_PDNP || phase == END_PDNPB) - recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); - else if (phase == END_SREF || phase == END_SREFB) - recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); + if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) + recTime += this->memSpec->getCommandLength(phaseToCommand(phase)); - unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID(); - unsigned int ch __attribute__((unused)) = DramExtension::getExtension(payload).getChannel().ID(); - unsigned int bg __attribute__((unused)) = DramExtension::getExtension(payload).getBankGroup().ID(); - unsigned int bank __attribute__((unused)) = DramExtension::getExtension(payload).getBank().ID(); - unsigned int row __attribute__((unused)) = DramExtension::getExtension(payload).getRow().ID(); - unsigned int col __attribute__((unused)) = DramExtension::getExtension(payload).getColumn().ID(); + unsigned int thr __attribute__((unused)) = DramExtension::getExtension(trans).getThread().ID(); + unsigned int ch __attribute__((unused)) = DramExtension::getExtension(trans).getChannel().ID(); + unsigned int bg __attribute__((unused)) = DramExtension::getExtension(trans).getBankGroup().ID(); + unsigned int bank __attribute__((unused)) = DramExtension::getExtension(trans).getBank().ID(); + unsigned int row __attribute__((unused)) = DramExtension::getExtension(trans).getRow().ID(); + unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID(); PRINTDEBUGMESSAGE(this->name(), "Recording " + phaseNameToString(phase) + " thread " + - to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( - bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " at " + recTime.to_string()); + std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string( + bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " + + std::to_string(col) + " at " + recTime.to_string()); - tlmRecorder->recordPhase(payload, phase, recTime); + tlmRecorder->recordPhase(trans, phase, recTime); + + if (phaseNeedsEnd(phase)) + { + recTime += this->memSpec->getExecutionTime(phaseToCommand(phase), trans); + tlmRecorder->recordPhase(trans, getEndPhase(phase), recTime); + } - return BaseDram::nb_transport_fw(payload, phase, delay); } + // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for visualization purposes. template @@ -123,36 +126,35 @@ void DramRecordable::powerWindow() // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clkCycles = sc_time_stamp().value() / this->memSpec->clk.value(); + clkCycles = sc_time_stamp() / this->memSpec->tCK; - DRAMPower->calcWindowEnergy(clkCycles); + this->DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(this->DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM); + this->DRAMPower->getPower().window_average_power + * Configuration::getInstance().numberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW - PRINTDEBUGMESSAGE(this->name(), string("\tWindow Energy: \t") + to_string( - DRAMPower->getEnergy().window_energy * - Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); - PRINTDEBUGMESSAGE(this->name(), string("\tWindow Average Power: \t") + to_string( - DRAMPower->getPower().window_average_power * - Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); + PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string( + this->DRAMPower->getEnergy().window_energy * + Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[pJ]")); + PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string( + this->DRAMPower->getPower().window_average_power * + Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[mW]")); } while (true); } template class DramRecordable; template class DramRecordable; -template class DramRecordable; template class DramRecordable; +template class DramRecordable; template class DramRecordable; -template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; - +template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h index c11f9a81..fe835bf1 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -42,8 +42,6 @@ #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -using namespace tlm; - template class DramRecordable final : public BaseDram { @@ -53,13 +51,15 @@ public: ~DramRecordable(); private: - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay) override; + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &delay) override; + + void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay); + TlmRecorder *tlmRecorder; - libDRAMPower *DRAMPower; - sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * - Configuration::getInstance().WindowSize; + sc_time powerWindowSize = Configuration::getInstance().memSpec->tCK * + Configuration::getInstance().windowSize; // When working with floats, we have to decide ourselves what is an // acceptable definition for "equal". Here the number is compared with a diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 1ee85597..71ccca31 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -44,70 +44,68 @@ #include "../../configuration/memspec/MemSpecWideIO.h" using namespace tlm; +using namespace DRAMPower; DramWideIO::DramWideIO(sc_module_name name) : Dram(name) { - // Parameters for DRAMPower - MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) + if (Configuration::getInstance().powerAnalysis) { - sc_time clk = memSpec->clk; + MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.burstLength = memSpec->burstLength; + memArchSpec.dataRate = memSpec->dataRate; + memArchSpec.nbrOfRows = memSpec->numberOfRows; + memArchSpec.nbrOfBanks = memSpec->numberOfBanks; + memArchSpec.nbrOfColumns = memSpec->numberOfColumns; + memArchSpec.nbrOfRanks = memSpec->numberOfRanks; memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups; memArchSpec.twoVoltageDomains = true; memArchSpec.dll = false; MemTimingSpec memTimingSpec; - //FIXME: memTimingSpec.FAWB = memSpec->tTAW / clk; - //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; - //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; - //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; - //FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk; - //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; - //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tTAW / memSpec->tCK; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / memSpec->tCK; + //FIXME: memTimingSpec.RCB = memSpec->tRC / memSpec->tCK; + //FIXME: memTimingSpec.RPB = memSpec->tRP / memSpec->tCK; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD / memSpec->tCK; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / memSpec->tCK; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / memSpec->tCK; memTimingSpec.AL = 0; - memTimingSpec.CCD = memSpec->BurstLength; - memTimingSpec.CCD_L = memSpec->BurstLength; - memTimingSpec.CCD_S = memSpec->BurstLength; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; + memTimingSpec.CCD = memSpec->burstLength; + memTimingSpec.CCD_L = memSpec->burstLength; + memTimingSpec.CCD_S = memSpec->burstLength; + memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK; + memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK; + memTimingSpec.clkMhz = memSpec->fCKMHz; // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tTAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD / clk; - memTimingSpec.RRD_L = memSpec->tRRD / clk; - memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->BurstLength; - memTimingSpec.TAW = memSpec->tTAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR / clk; - memTimingSpec.WTR_L = memSpec->tWTR / clk; - memTimingSpec.WTR_S = memSpec->tWTR / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXP / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXS / clk; + memTimingSpec.clkPeriod = 1000.0 / memSpec->fCKMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / memSpec->tCK; + memTimingSpec.FAW = memSpec->tTAW / memSpec->tCK; + memTimingSpec.RAS = memSpec->tRAS / memSpec->tCK; + memTimingSpec.RC = memSpec->tRC / memSpec->tCK; + memTimingSpec.RCD = memSpec->tRCD / memSpec->tCK; + memTimingSpec.REFI = memSpec->tREFI / memSpec->tCK; + memTimingSpec.RFC = memSpec->tRFC / memSpec->tCK; + memTimingSpec.RL = memSpec->tRL / memSpec->tCK; + memTimingSpec.RP = memSpec->tRP / memSpec->tCK; + memTimingSpec.RRD = memSpec->tRRD / memSpec->tCK; + memTimingSpec.RRD_L = memSpec->tRRD / memSpec->tCK; + memTimingSpec.RRD_S = memSpec->tRRD / memSpec->tCK; + memTimingSpec.RTP = memSpec->burstLength; + memTimingSpec.TAW = memSpec->tTAW / memSpec->tCK; + memTimingSpec.WL = memSpec->tWL / memSpec->tCK; + memTimingSpec.WR = memSpec->tWR / memSpec->tCK; + memTimingSpec.WTR = memSpec->tWTR / memSpec->tCK; + memTimingSpec.WTR_L = memSpec->tWTR / memSpec->tCK; + memTimingSpec.WTR_S = memSpec->tWTR / memSpec->tCK; + memTimingSpec.XP = memSpec->tXP / memSpec->tCK; + memTimingSpec.XPDLL = memSpec->tXP / memSpec->tCK; + memTimingSpec.XS = memSpec->tXS / memSpec->tCK; + memTimingSpec.XSDLL = memSpec->tXS / memSpec->tCK; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; @@ -136,18 +134,18 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memPowerSpec.vdd2 = memSpec->vDD2; MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; + powerSpec.id = memSpec->memoryId; + powerSpec.memoryType = memSpec->memoryType; powerSpec.memTimingSpec = memTimingSpec; powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; - libDRAMPower *DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, 0); // For each bank in a channel a error Model is created: - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) { - for (unsigned i = 0; i < memSpec->NumberOfBanks; i++) + for (unsigned i = 0; i < memSpec->numberOfBanks; i++) { errorModel *em; std::string errorModelStr = "errorModel_bank" + std::to_string(i); @@ -155,13 +153,11 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) ememory.push_back(em); } } - this->DRAMPower = DRAMPower; } else { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramWideIO", "Error modeling without power analysis is not supported"); - DRAMPower = new libDRAMPowerDummy(); } } @@ -173,137 +169,42 @@ DramWideIO::~DramWideIO() } tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay) + tlm_phase &phase, sc_time &) { - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + assert(phase >= 5 && phase <= 19); - // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); + if (Configuration::getInstance().powerAnalysis) + { + unsigned bank = DramExtension::getExtension(payload).getBank().ID(); + unsigned long long cycle = sc_time_stamp() / memSpec->tCK; + DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); + } - if (phase == BEGIN_PRE) + if (storeMode == StorageMode::Store) { - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); - } - else if (phase == BEGIN_PREA) - { - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - sendToController(payload, END_PREA, - delay + memSpec->getExecutionTime(Command::PREA, payload)); - } - else if (phase == BEGIN_ACT) - { - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->activate(row); - } - else if (phase == BEGIN_WR) - { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); - // save data: - if (StoreMode == StorageMode::Store) // Use Storage - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); - } - else if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model - { - ememory[bank]->store(payload); - } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); - } - else if (phase == BEGIN_RD) - { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); - // load data: - if (StoreMode == StorageMode::Store) // use StorageMode + if (phase == BEGIN_RD || phase == BEGIN_RDA) { unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel - { - ememory[bank]->load(payload); - } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); - } - else if (phase == BEGIN_WRA) - { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); - // save data: - if (StoreMode == StorageMode::Store) // Use Storage + else if (phase == BEGIN_WR || phase == BEGIN_WRA) { unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - else if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model - { - ememory[bank]->store(payload); - } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } - else if (phase == BEGIN_RDA) + else if (storeMode == StorageMode::ErrorModel) { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); - // Load data: - if (StoreMode == StorageMode::Store) // use StorageMode - { - unsigned char *phyAddr = memory + payload.get_address(); - memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); - } - else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel - { - ememory[bank]->load(payload); - } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); - } - else if (phase == BEGIN_REFA) - { - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA, payload)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); + unsigned bank = DramExtension::getExtension(payload).getBank().ID(); - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->refresh(row); - } - else if (phase == BEGIN_REFB) - { - DRAMPower->doCommand(MemCommand::REFB, bank, cycle); - sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFA, payload)); - } - // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length - else if (phase == BEGIN_PDNA) - { - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); - } - else if (phase == END_PDNA) - { - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); - } - else if (phase == BEGIN_PDNP) - { - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); - } - else if (phase == END_PDNP) - { - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); - } - else if (phase == BEGIN_SREF) - { - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); - } - else if (phase == END_SREF) - { - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); - } - else - { - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); + if (phase == BEGIN_ACT) + ememory[bank]->activate(DramExtension::getExtension(payload).getRow().ID()); + else if (phase == BEGIN_RD || phase == BEGIN_RDA) + ememory[bank]->load(payload); + else if (phase == BEGIN_WR || phase == BEGIN_WRA) + ememory[bank]->store(payload); + else if (phase == BEGIN_REFA) + ememory[bank]->refresh(DramExtension::getExtension(payload).getRow().ID()); } return TLM_ACCEPTED; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.h b/DRAMSys/library/src/simulation/dram/DramWideIO.h index 10aeb629..8f0ae6d5 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.h @@ -41,8 +41,6 @@ #include "Dram.h" #include "../../error/errormodel.h" -using namespace tlm; - class DramWideIO : public Dram { public: @@ -51,8 +49,8 @@ public: virtual ~DramWideIO(); protected: - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay) override; + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &delay) override; private: std::vector ememory; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp index dde791fa..8d2ac226 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp @@ -42,16 +42,9 @@ DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name) { - if (StoreMode == StorageMode::ErrorModel) + if (storeMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2"); - // Parameters for DRAMPower - MemSpecWideIO2 *memSpec = dynamic_cast(this->memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("DramWideIO2", "Wrong MemSpec chosen"); - - if (Configuration::getInstance().PowerAnalysis) - SC_REPORT_FATAL("DramWideIO2", "DRAMPower not supported for WideIO2"); - else - DRAMPower = new libDRAMPowerDummy(); + if (Configuration::getInstance().powerAnalysis) + SC_REPORT_FATAL("DramWideIO2", "DRAMPower does not support WideIO2"); } diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 0cd387ac..cf231c5f 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -44,11 +44,9 @@ #include "DRAMSys.h" #include "TraceSetup.h" -using namespace std; +std::string resources; -string resources; - -string pathOfFile(string file) +std::string pathOfFile(std::string file) { return file.substr(0, file.find_last_of('/')); } @@ -63,19 +61,19 @@ int sc_main(int argc, char **argv) sc_set_time_resolution(1, SC_PS); - string SimulationXML; + std::string SimulationXML; // Run only with default config (ddr-example.xml): if (argc == 1) { // Get path of resources: resources = pathOfFile(argv[0]) - + string("/../DRAMSys/library/resources/"); + + std::string("/../DRAMSys/library/resources/"); SimulationXML = resources + "simulations/ddr3-example.xml"; } // Run with specific config but default resource folders: else if (argc == 2) { // Get path of resources: resources = pathOfFile(argv[0]) - + string("/../DRAMSys/library/resources/"); + + std::string("/../DRAMSys/library/resources/"); SimulationXML = argv[1]; } // Run with spefific config and specific resource folder: @@ -90,13 +88,13 @@ int sc_main(int argc, char **argv) DRAMSys *dramSys = new DRAMSys("DRAMSys", SimulationXML, resources); // Instantiate STL Players: - traceSetup *ts = new traceSetup(SimulationXML, resources, &players); + TraceSetup *ts = new TraceSetup(SimulationXML, resources, &players); // Bind STL Players with DRAMSys: for (size_t i = 0; i < players.size(); i++) { - if(Configuration::getInstance().CheckTLM2Protocol) + if(Configuration::getInstance().checkTLM2Protocol) { - string str = "TLMCheckerPlayer" + std::to_string(i); + std::string str = "TLMCheckerPlayer" + std::to_string(i); tlm_utils::tlm2_base_protocol_checker<> *playerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str()); dramSys->playersTlmCheckers.push_back(playerTlmChecker);