diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
index 605f0176..785b790c 100644
--- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
+++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
@@ -283,7 +283,7 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
     }
 }
 
-bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
 {
     auto burstLength = ControllerExtension::getBurstLength(payload);
 
diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
index e09e5c44..dacc5ef1 100644
--- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
+++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
@@ -129,7 +129,7 @@ public:
     sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 
-    bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
+    bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys
diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
index b2400ef2..181409a5 100644
--- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
+++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
@@ -441,7 +441,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
             }
         }
 
-        if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW
+        if (memSpec->requiresReadModifyWrite(payload)) // second WR requires RMW
         {
             lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank];
             if (lastCommandStart != scMaxTime)
@@ -517,7 +517,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
             }
         }
 
-        if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW
+        if (memSpec->requiresReadModifyWrite(payload)) // second WR requires RMW
         {
             lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup];
             if (lastCommandStart != scMaxTime)
diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
index 431a011d..93ec43e1 100644
--- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
+++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
@@ -197,7 +197,7 @@ unsigned MemSpecHBM3::getRAAMMT() const
     return RAAMMT;
 }
 
-bool MemSpecHBM3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+bool MemSpecHBM3::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
 {
     bool maskedWrite = payload.get_byte_enable_ptr() != nullptr;
 
diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
index 8bf6abbd..852ac762 100644
--- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
+++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
@@ -101,7 +101,7 @@ public:
     sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 
-    bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
+    bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
index dd512c81..7fc5b70d 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
@@ -148,7 +148,7 @@ bool MemSpec::hasRasAndCasBus() const
     return false;
 }
 
-bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
 {
     return payload.get_byte_enable_ptr() != nullptr;
 }
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
index c2c91fff..7b28e7ac 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
@@ -102,7 +102,7 @@ public:
     virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
     virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
 
-    virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const;
+    virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
 
     sc_core::sc_time getCommandLength(Command) const;
     double getCommandLengthInCycles(Command) const;
diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp
index 85ec6098..95529068 100644
--- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp
+++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp
@@ -201,7 +201,7 @@ void BankMachineOpen::evaluate()
                         nextCommand = Command::RD;
                     else
                     {
-                        nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
+                        nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
                     }
                 }
                 else // row miss
@@ -247,7 +247,7 @@ void BankMachineClosed::evaluate()
                     nextCommand = Command::RDA;
                 else
                 {
-                    nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                    nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
                 }
             }
         }
@@ -295,7 +295,7 @@ void BankMachineOpenAdaptive::evaluate()
                             nextCommand = Command::RDA;
                         else
                         {
-                            nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
                         }
                     }
                     else
@@ -305,7 +305,7 @@ void BankMachineOpenAdaptive::evaluate()
                             nextCommand = Command::RD;
                         else
                         {
-                            nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
                         }
                     }
                 }
@@ -357,7 +357,7 @@ void BankMachineClosedAdaptive::evaluate()
                             nextCommand = Command::RD;
                         else
                         {
-                            nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
                         }
                     }
                     else
@@ -367,7 +367,7 @@ void BankMachineClosedAdaptive::evaluate()
                             nextCommand = Command::RDA;
                         else
                         {
-                            nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
                         }
                     }
                 }