From 3eb0d7eb8a9713ee1efca1037352e17acaa1cea5 Mon Sep 17 00:00:00 2001
From: Matthias Jung <jungma@eit.uni-kl.de>
Date: Wed, 23 Jul 2014 13:51:51 +0200
Subject: [PATCH] Fix for new DRAMPower library

---
 dram/src/simulation/Dram.h | 43 ++++++++++++++++++++------------------
 1 file changed, 23 insertions(+), 20 deletions(-)

diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h
index bf15a79d..11b5c43e 100644
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -31,21 +31,24 @@ template<unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = tr
 struct Dram: sc_module
 {
     tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
-    libDRAMPower DRAMPower;
-
+    libDRAMPower *DRAMPower;
 
     SC_CTOR(Dram) :
             tSocket("socket")
     {
         tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
+        MemorySpecification memSpec(MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri));
+        DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 );
     }
 
     ~Dram()
     {
-        MemorySpecification memSpec(MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri));
-        DRAMPower.getEnergy(memSpec);
-        cout << "Total Energy" << "\t" << DRAMPower.mpm.energy.total_energy << endl;
-        cout << "Average Power" << "\t" << DRAMPower.mpm.power.average_power << endl;
+
+
+
+        DRAMPower->getEnergy();
+        cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl;
+        cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl;
     }
 
     virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
@@ -58,42 +61,42 @@ struct Dram: sc_module
 
         if (phase == BEGIN_PRE)
         {
-            DRAMPower.doCommand(MemCommand::PRE, bank, cycle);
+            DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
             sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
         }
         else if (phase == BEGIN_PRE_ALL)
         {
-            DRAMPower.doCommand(MemCommand::PREA, bank, cycle);
+            DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
             sendToController(payload, END_PRE_ALL,delay +  getExecutionTime(Command::PrechargeAll, payload));
         }
         else if (phase == BEGIN_ACT)
         {
-            DRAMPower.doCommand(MemCommand::ACT, bank, cycle);
+            DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
             sendToController(payload, END_ACT, delay +  getExecutionTime(Command::Activate, payload));
         }
         else if (phase == BEGIN_WR)
         {
-            DRAMPower.doCommand(MemCommand::WR, bank, cycle);
+            DRAMPower->doCommand(MemCommand::WR, bank, cycle);
             sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
         }
         else if (phase == BEGIN_RD)
         {
-            DRAMPower.doCommand(MemCommand::RD, bank, cycle);
+            DRAMPower->doCommand(MemCommand::RD, bank, cycle);
             sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
         }
         else if (phase == BEGIN_WRA)
         {
-            DRAMPower.doCommand(MemCommand::WRA, bank, cycle);
+            DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
             sendToController(payload, END_WRA, delay +  getExecutionTime(Command::WriteA, payload));
         }
         else if (phase == BEGIN_RDA)
         {
-            DRAMPower.doCommand(MemCommand::RDA, bank, cycle);
+            DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
             sendToController(payload, END_RDA, delay +  getExecutionTime(Command::ReadA, payload));
         }
         else if (phase == BEGIN_AUTO_REFRESH)
         {
-            DRAMPower.doCommand(MemCommand::REF, bank, cycle);
+            DRAMPower->doCommand(MemCommand::REF, bank, cycle);
             sendToController(payload, END_AUTO_REFRESH, delay +  getExecutionTime(Command::AutoRefresh, payload));
         }
 
@@ -104,7 +107,7 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower.doCommand(MemCommand::PDN_S_PRE, bank, cycle);
+                    DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
                 }
             }
         }
@@ -114,7 +117,7 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle);
+                    DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
                 }
             }
         }
@@ -124,7 +127,7 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower.doCommand(MemCommand::PDN_S_ACT, bank, cycle);
+                    DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
                 }
             }
         }
@@ -134,17 +137,17 @@ struct Dram: sc_module
             {
                 if(bank == 0)
                 {
-                    DRAMPower.doCommand(MemCommand::PUP_ACT, bank, cycle);
+                    DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
                 }
             }
         }
         else if (phase == BEGIN_SREF)
         {
-            DRAMPower.doCommand(MemCommand::SREN, bank, cycle);
+            DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
         }
         else if (phase == END_SREF)
         {
-            DRAMPower.doCommand(MemCommand::SREX, bank, cycle);
+            DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
         }
         else
         {