diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp
index d9de822b..e7cf4209 100644
--- a/DRAMSys/library/src/configuration/Configuration.cpp
+++ b/DRAMSys/library/src/configuration/Configuration.cpp
@@ -285,8 +285,8 @@ void Configuration::setParameter(const std::string &name, const nlohmann::json &
     else if (name == "GeneratePowerMap")
         temperatureSim.generatePowerMap = value;
     else
-        SC_REPORT_FATAL("Configuration",
-                        ("Parameter " + name + " not defined in Configuration").c_str());
+        SC_REPORT_WARNING("Configuration",
+                ("Parameter " + name + " not defined in Configuration").c_str());
 }
 
 void Configuration::setPathToResources(const std::string &path)
diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
index 125c6cbf..f4bc9bfe 100644
--- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
@@ -75,6 +75,8 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, tlm_generic_paylo
 
     if (command == Command::RD || command == Command::RDA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL);
@@ -128,6 +130,8 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, tlm_generic_paylo
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL);
diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
index 47b151c7..ba0ad9a0 100644
--- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
@@ -79,6 +79,8 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, tlm_generic_paylo
 
     if (command == Command::RD || command == Command::RDA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL);
@@ -148,6 +150,8 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, tlm_generic_paylo
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL);
diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
index 8a433061..95dcdf4c 100644
--- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
@@ -131,6 +131,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo
     if (command == Command::RD || command == Command::RDA)
     {
         unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 16) || (burstLength == 32));
         assert(!(burstLength == 32) || (memSpec->bitWidth == 4));
 
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
@@ -316,6 +317,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo
     else if (command == Command::WR || command == Command::WRA)
     {
         unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 16) || (burstLength == 32));
         assert(!(burstLength == 32) || (memSpec->bitWidth == 4));
 
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
index eea58b9c..008ede01 100644
--- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
@@ -80,6 +80,8 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payl
 
     if (command == Command::RD || command == Command::RDA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD);
@@ -149,6 +151,8 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payl
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR);
diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
index 4f63a8da..9730d000 100644
--- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
@@ -80,6 +80,10 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, tlm_generic_pay
 
     if (command == Command::RD || command == Command::RDA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK)
+        assert(!(memSpec->dataRate == 8) || (burstLength == 16)); // QDR mode (ODR wrt CK)
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD);
@@ -149,6 +153,10 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, tlm_generic_pay
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK)
+        assert(!(memSpec->dataRate == 8) || (burstLength == 16)); // QDR mode (ODR wrt CK)
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR);
diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
index 212982a6..c098e7e8 100644
--- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
@@ -79,6 +79,8 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, tlm_generic_payl
 
     if (command == Command::RD || command == Command::RDA)
     {
+        assert(DramExtension::getBurstLength(payload) == 16);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD);
@@ -148,6 +150,8 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, tlm_generic_payl
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        assert(DramExtension::getBurstLength(payload) == 16);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR);
diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
index c5866453..ee22bbd0 100644
--- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
@@ -80,6 +80,10 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_paylo
 
     if (command == Command::RD || command == Command::RDA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert(!(memSpec->numberOfRanks == 1) || (burstLength == 2)); // Legacy mode
+        assert(!(memSpec->numberOfRanks == 2) || (burstLength == 4)); // Pseudo-channel mode
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK);
@@ -131,6 +135,10 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_paylo
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert(!(memSpec->numberOfRanks == 1) || (burstLength == 2)); // Legacy mode
+        assert(!(memSpec->numberOfRanks == 2) || (burstLength == 4)); // Pseudo-channel mode
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK);
diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
index 47cef996..74b55670 100644
--- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
@@ -81,6 +81,9 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_pay
 
     if (command == Command::RD || command == Command::RDA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 16) || (burstLength == 32)); // TODO: BL16/32 OTF
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
@@ -130,6 +133,9 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_pay
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 16) || (burstLength == 32));
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp
index f3d7ead3..8198ad2d 100644
--- a/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp
@@ -84,7 +84,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_pay
     {
         unsigned burstLength = DramExtension::getBurstLength(payload);
         assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32
-        assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16
+        assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32)
 
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
@@ -195,7 +195,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_pay
     {
         unsigned burstLength = DramExtension::getBurstLength(payload);
         assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32
-        assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16
+        assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16 (TODO: BL32)
 
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
index b572c4d3..8099d77f 100644
--- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
@@ -75,6 +75,8 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, tlm_generic_pa
 
     if (command == Command::RD || command == Command::RDA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL);
@@ -130,6 +132,8 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, tlm_generic_pa
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        assert(DramExtension::getBurstLength(payload) == 8);
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD - memSpec->tAL);
diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
index c7c526aa..4fff40d5 100644
--- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
@@ -75,6 +75,9 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_pay
 
     if (command == Command::RD || command == Command::RDA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 2) || (burstLength == 4));
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
@@ -124,6 +127,9 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_pay
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 2) || (burstLength == 4));
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
index 48cb04f6..8617b834 100644
--- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
+++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
@@ -76,6 +76,9 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_pa
 
     if (command == Command::RD || command == Command::RDA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 4) || (burstLength == 8)); // TODO: BL4/8 OTF
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
@@ -125,6 +128,9 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_pa
     }
     else if (command == Command::WR || command == Command::WRA)
     {
+        unsigned burstLength = DramExtension::getBurstLength(payload);
+        assert((burstLength == 4) || (burstLength == 8));
+
         lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != sc_max_time())
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);