gem5 information added to readme

2018-02-03 21:34:50 +01:00
parent ae8889fc8c
commit 3df37617f4
1 changed files with 151 additions and 1 deletions
--- a/README.md
+++ b/README.md
@@ -962,7 +962,155 @@ $ cd build/simulator/
 $ ./DRAMSys > output
 ```

-#### References
+## DRAMSys with gem5
+
+Install gem5 by following the instructions on the gem5 wiki
+http://gem5.org/Documentation#Getting_Started. In order to understand the
+SystemC coupling with gem5 it is recommended to study util/tlm/README and [11].
+The main steps for building gem5 with SystemC are:
+
+``` bash
+scons build/ARM/gem5.opt
+scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
+#for mac: scons --with-cxx-config --without-python build/ARM/libgem5_opt.dylib
+cd util/tlm
+```
+
+In order to use gem5 with DRAMSys set the GEM5 environment variable to the path
+to gem5, for example in the QtCreator under Projects > Build & Run > Build
+Environment:
+
+```
+GEM5=/path/to/gem5/
+```
+
+DRAMSys will detect gem5 and configures automatically the according compile
+target *gem5* for QtCreator.
+
+In order to run gem5 with DRAMSys its mandatory to run gem5 first without
+DRAMSys in order to generate an ini file which will be read by the DRAMSys_gem5
+binary. In the following several examples for DRAMSys gem5 bindings are shown.
+
+### DRAMSys with gem5 traffic generator
+
+In the following we will run a simple example with a gem5 traffic generator:
+
+```
+Base System Architecture:
+-------------+ +------+    ^
+| System Port | | TGEN |    |
+-------+-----+ +--+---+    |
+        |           |       | gem5 World
+        |      +----+       | (see this file)
+        |      |            |
+-------v------v-------+    |
+|        Membus        |    v
+---------------+------+    External Port (see sc_slave_port.*)
+                |           ^
+           +----v----+      | TLM World
+           | DRAMSys |      | (see sc_target.*)
+           +---------+      v
+
+```
+
+As mentioned before we first need to create a config.ini
+that represents the gem5 configuration. We do so by starting gem5 with the
+desired python configuration script.
+
+``` bash
+cd gem5/utils/tlm/
+../../build/ARM/gem5.opt conf/tlm_slave.py
+```
+
+The message
+```
+"fatal: Can't find port handler type 'tlm_slave'"
+```
+is totally okay. The configuration file config.ini will be stored in the m5out/
+directory.  Copy this configuration file to the building directory of DRAMSys:
+
+```
+dram.vp.system/build-DRAMSys-Desktop_Qt_5_7_0_clang_64bit-Debug/gem5
+```
+Also the traffic generatior configuration file (conf/tgen.cfg) must be stored
+in a conf directory of this building directory.
+
+Then the simulation can be started with:
+
+``` bash
+./DRAMSys_gem5 /path/to/dram.vp.system/DRAMSys/library/resources/simulations/ddr3-example.xml config.ini
+```
+
+Lets run the simulation for some seconds and then stop the simulation with
+ctrl+c.  Observe the output of the simulation in the trace analyzer. The trace
+database file is stored in the gem5 directory in the building directory.
+
+### Boot Linux with gem5 and DRAMSys
+
+The procedure is very similar to the traffic generator example above.
+
+First we have to generate the config.ini file by starting gem5 with the following configuration:
+
+``` bash
+build/ARM/gem5.opt configs/example/fs.py \
+  --tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \
+  --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
+  --l2cache --machine-type=VExpress_EMM \
+  --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
+  --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
+  --disk-image=linux-aarch32-ael.img
+```
+
+The config.ini should be copied again to the DRAMSys_gem5 build folder.
+
+The simconfig should be changed in order to support storage and address offsets:
+
+``` xml
+<simconfig>
+    <SimulationName value="ddr3" />
+    <Debug value="0" />
+    <DatabaseRecording value="1" />
+    <PowerAnalysis value="1" />
+    <EnableWindowing value = "1" />
+    <WindowSize value="1000" />
+    <ThermalSimulation value="0"/>
+    <SimulationProgressBar value="1"/>
+    <NumberOfMemChannels value="1"/>
+    <NumberOfDevicesOnDIMM value = "8" />
+    <CheckTLM2Protocol value = "0" />
+    <AddressOffset value = "0" />
+    <ECCControllerMode value = "Disabled" />
+    <ErrorChipSeed value="42" />
+    <ErrorCSVFile value="" />
+    <!-- Modes:
+	- NoStorage,
+	- Store (store data without errormodel),
+	- ErrorModel (store data with errormodel)
+    -->
+
+    <!-- Gem5 Related Configuration:
+    In the memory controller file the storage mode should be set to Store
+    E.g. the DRAM is located at 0x80000000 for gem5
+    -->
+    <StoreMode value="Store" />
+    <AddressOffset value = "2147483648" />
+</simconfig>
+```
+
+Then start DRAMSys_gem5 with the following command:
+
+``` bash
+./DRAMSys_gem5 /Users/myzinsky/EMS/Programming/dram.vp.system/DRAMSys/library/resources/simulations/ddr3-example.xml config.ini
+```
+
+For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp
+
+### DRAMSys with gem5 Elastic Traces
+
+Some predefined configs are stored in dram.vp.system/DRAMSys/gem5/configs and the related python files are stored here: dram.vp.system/DRAMSys/gem5/examples
+
+
+## References

 [1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
 M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
@@ -1002,3 +1150,5 @@ Thermal Investigations of ICs and Systems (THERMINIC'10), Barcelona, Spain,

 [11] http://esl.epfl.ch/3D-ICE

+[12] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
+C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.