diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 165a3e54..ada20041 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -52,7 +52,7 @@ add_subdirectory(src/common/third_party/nlohmann) if(DEFINED ENV{SYSTEMC_HOME}) find_library(SYSTEMC_LIBRARY NAMES systemc SnpsVP - PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/ + PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/lib64 $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/ ) message("== Building with external SystemC located in $ENV{SYSTEMC_HOME}") else() diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json index cd9bdced..6adb2a87 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json @@ -48,18 +48,18 @@ "FAW_dlr": 0, "WTR_L": 22, "WTR_S": 6, - "RFC_slr": 429, - "RFC_slr": 286, - "RFC_dlr": 0, - "RFC_dlr": 0, - "RFC_dpr": 0, - "RFC_dpr": 0, - "RFCsb_slr": 253, - "RFCsb_dlr": 0, - "REFI1": 8580, - "REFI2": 4290, + "RFC1_slr": 429, + "RFC2_slr": 286, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, + "RFCsb_slr": 253, + "RFCsb_dlr": 0, + "REFI1": 8580, + "REFI2": 4290, "REFISB": 2145, - "REFSBRD_slr": 66, + "REFSBRD_slr": 66, "REFSBRD_dlr": 0, "RTRS": 2, "CPDED": 11, diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp index cf93fdf6..807225c7 100644 --- a/DRAMSys/library/src/common/DebugManager.cpp +++ b/DRAMSys/library/src/common/DebugManager.cpp @@ -40,6 +40,8 @@ #include "../configuration/Configuration.h" +using namespace sc_core; + void DebugManager::printDebugMessage(const std::string &sender, const std::string &message) { if (Configuration::getInstance().debug) @@ -48,7 +50,7 @@ void DebugManager::printDebugMessage(const std::string &sender, const std::strin std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; if (writeToFile && debugFile) - debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message << "\n"; + debugFile << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; } } @@ -64,8 +66,8 @@ void DebugManager::openDebugFile(const std::string &filename) debugFile.open(filename); } -DebugManager::DebugManager() : - writeToConsole(false), writeToFile(false) +DebugManager::DebugManager() + : writeToConsole(false), writeToFile(false) { } diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index be07b261..64fcf6ce 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -50,10 +50,8 @@ #else #define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) -#include #include -#include -#include "utils.h" +#include class DebugManager { @@ -79,7 +77,7 @@ public: void openDebugFile(const std::string &filename); private: - ofstream debugFile; + std::ofstream debugFile; }; #endif diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index d8c39a26..9e29b936 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -36,13 +36,14 @@ * Eder F. Zulian */ -#include -#include +#include #include "TlmRecorder.h" -#include "dramExtensions.h" +#include "DebugManager.h" +#include "../controller/Command.h" #include "../configuration/Configuration.h" +using namespace sc_core; using namespace tlm; TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) : diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 73616695..553f35de 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -39,18 +39,15 @@ #ifndef TLMRECORDER_H #define TLMRECORDER_H -#include -#include #include #include -#include -#include -#include +#include #include -#include -#include + +#include +#include #include "sqlite3.h" -#include "DebugManager.h" +#include "dramExtensions.h" #include "utils.h" class TlmRecorder @@ -61,30 +58,30 @@ public: void recordMcConfig(std::string _mcconfig) { - mcconfig = _mcconfig; + mcconfig = std::move(_mcconfig); } void recordMemspec(std::string _memspec) { - memspec = _memspec; + memspec = std::move(_memspec); } void recordTraceNames(std::string _traces) { - traces = _traces; + traces = std::move(_traces); } - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &time); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &time); void recordPower(double timeInSeconds, double averagePower); void recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth); void recordBandwidth(double timeInSeconds, double averageBandwidth); - void recordDebugMessage(const std::string &message, const sc_time &time); - void updateDataStrobe(const sc_time &begin, const sc_time &end, + void recordDebugMessage(const std::string &message, const sc_core::sc_time &time); + void updateDataStrobe(const sc_core::sc_time &begin, const sc_core::sc_time &end, tlm::tlm_generic_payload &trans); void closeConnection(); private: struct Transaction { - Transaction() {} + Transaction() = default; Transaction(uint64_t id) : id(id) {} uint64_t id; @@ -92,12 +89,13 @@ private: unsigned int burstLength; char cmd; DramExtension dramExtension; - sc_time timeOfGeneration; + sc_core::sc_time timeOfGeneration; TimeInterval timeOnDataStrobe; struct Phase { - Phase(std::string name, sc_time begin): name(name), interval(begin, SC_ZERO_TIME) {} + Phase(std::string name, const sc_core::sc_time& begin): name(std::move(name)), + interval(begin, sc_core::SC_ZERO_TIME) {} std::string name; TimeInterval interval; }; @@ -122,10 +120,10 @@ private: void insertGeneralInfo(); void insertCommandLengths(); void insertTransactionInDB(Transaction &recordingData); - void insertRangeInDB(uint64_t id, const sc_time &begin, const sc_time &end); - void insertPhaseInDB(const std::string &phaseName, const sc_time &begin, const sc_time &end, + void insertRangeInDB(uint64_t id, const sc_core::sc_time &begin, const sc_core::sc_time &end); + void insertPhaseInDB(const std::string &phaseName, const sc_core::sc_time &begin, const sc_core::sc_time &end, uint64_t transactionID); - void insertDebugMessageInDB(const std::string &message, const sc_time &time); + void insertDebugMessageInDB(const std::string &message, const sc_core::sc_time &time); static constexpr unsigned transactionCommitRate = 8192; std::array, 2> recordingDataBuffer; @@ -136,7 +134,7 @@ private: std::unordered_map currentTransactionsInSystem; uint64_t totalNumTransactions; - sc_time simulationTimeCoveredByRecording; + sc_core::sc_time simulationTimeCoveredByRecording; sqlite3 *db = nullptr; sqlite3_stmt *insertTransactionStatement, *insertRangeStatement, diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index b951b6a9..38992599 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -37,9 +37,8 @@ #include "dramExtensions.h" #include "../configuration/Configuration.h" -#include "map" -#include "utils.h" +using namespace sc_core; using namespace tlm; DramExtension::DramExtension() : @@ -55,7 +54,7 @@ DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, row(row), column(column), burstLength(burstLength), threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} -void DramExtension::setExtension(tlm::tlm_generic_payload *payload, +void DramExtension::setExtension(tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, @@ -86,7 +85,7 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, } } -void DramExtension::setExtension(tlm::tlm_generic_payload &payload, +void DramExtension::setExtension(tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, BankGroup bankGroup, Bank bank, Row row, Column column, unsigned int burstLength, @@ -97,7 +96,7 @@ void DramExtension::setExtension(tlm::tlm_generic_payload &payload, threadPayloadID, channelPayloadID); } -void DramExtension::setPayloadIDs(tlm::tlm_generic_payload *payload, uint64_t threadPayloadID, uint64_t channelPayloadID) +void DramExtension::setPayloadIDs(tlm_generic_payload *payload, uint64_t threadPayloadID, uint64_t channelPayloadID) { DramExtension *extension; payload->get_extension(extension); @@ -105,7 +104,7 @@ void DramExtension::setPayloadIDs(tlm::tlm_generic_payload *payload, uint64_t th extension->channelPayloadID = channelPayloadID; } -void DramExtension::setPayloadIDs(tlm::tlm_generic_payload &payload, uint64_t threadPayloadID, uint64_t channelPayloadID) +void DramExtension::setPayloadIDs(tlm_generic_payload &payload, uint64_t threadPayloadID, uint64_t channelPayloadID) { DramExtension::setPayloadIDs(&payload, threadPayloadID, channelPayloadID); } @@ -310,7 +309,7 @@ void GenerationExtension::copy_from(const tlm_extension_base &ext) } -void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration) +void GenerationExtension::setExtension(tlm_generic_payload *payload, const sc_time &timeOfGeneration) { GenerationExtension *extension = nullptr; payload->get_extension(extension); @@ -326,7 +325,7 @@ void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, const } } -void GenerationExtension::setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration) +void GenerationExtension::setExtension(tlm_generic_payload &payload, const sc_time &timeOfGeneration) { GenerationExtension::setExtension(&payload, timeOfGeneration); } diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 0d5a9c14..f4a4a040 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -37,9 +37,10 @@ #ifndef DRAMEXTENSIONS_H #define DRAMEXTENSIONS_H -#include #include -#include + +#include +#include class Thread { @@ -100,19 +101,14 @@ private: class Bank { public: - Bank(unsigned int id) : id(id) {} + explicit Bank(unsigned int id) : id(id) {} unsigned int ID() const { return id; } - unsigned int getStartAddress() - { - return 0; - } - - std::string toString() + std::string toString() const { return std::to_string(id); } @@ -245,19 +241,19 @@ private: class GenerationExtension : public tlm::tlm_extension { public: - GenerationExtension(sc_time timeOfGeneration) + explicit GenerationExtension(const sc_core::sc_time &timeOfGeneration) : timeOfGeneration(timeOfGeneration) {} tlm::tlm_extension_base *clone() const override; void copy_from(const tlm::tlm_extension_base &ext) override; - static void setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration); - static void setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration); + static void setExtension(tlm::tlm_generic_payload *payload, const sc_core::sc_time &timeOfGeneration); + static void setExtension(tlm::tlm_generic_payload &payload, const sc_core::sc_time &timeOfGeneration); static GenerationExtension &getExtension(const tlm::tlm_generic_payload *payload); static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload); - static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload); - static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); + static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload); + static sc_core::sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); private: - sc_time timeOfGeneration; + sc_core::sc_time timeOfGeneration; }; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 71ab5ce3..c507aa2a 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -36,13 +36,12 @@ * Luiza Correa */ -#include "utils.h" -#include -#include -#include -#include "dramExtensions.h" #include +#include +#include "utils.h" + +using namespace sc_core; using namespace tlm; using json = nlohmann::json; @@ -141,7 +140,7 @@ std::string parseString(json &obj, const std::string &name) void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank) { - payload.set_address(bank.getStartAddress()); + payload.set_address(0); payload.set_command(TLM_IGNORE_COMMAND); payload.set_data_length(0); payload.set_response_status(TLM_OK_RESPONSE); diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index e91e2256..85fedc9d 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -39,26 +39,22 @@ #ifndef UTILS_H #define UTILS_H -#include -#include #include -#include -#include -#include + +#include +#include #include "dramExtensions.h" -#include -#include #include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class TimeInterval { public: - sc_time start, end; - TimeInterval() : start(SC_ZERO_TIME), end(SC_ZERO_TIME) {} - TimeInterval(sc_time start, sc_time end) : start(start), end(end) {} + sc_core::sc_time start, end; + TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {} + TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {} - sc_time getLength() const; - bool timeIsInInterval(const sc_time &time) const; + sc_core::sc_time getLength() const; + bool timeIsInInterval(const sc_core::sc_time &time) const; bool intersects(const TimeInterval &other) const; }; diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index a2e6293c..d0d85aa2 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -53,6 +53,7 @@ #include "memspec/MemSpecGDDR6.h" #include "memspec/MemSpecSTTMRAM.h" +using namespace sc_core; using json = nlohmann::json; std::string Configuration::memspecUri; diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index e272f5d7..e38bb95c 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -41,14 +41,12 @@ #ifndef CONFIGURATION_H #define CONFIGURATION_H -#include #include -#include -#include "memspec/MemSpec.h" -#include "TemperatureSimConfig.h" -#include "../common/utils.h" +#include +#include "memspec/MemSpec.h" #include "../error/eccbaseclass.h" +#include "TemperatureSimConfig.h" class Configuration { @@ -59,7 +57,7 @@ public: return _instance; } private: - Configuration() {} + Configuration() = default; Configuration(const Configuration &); Configuration &operator = (const Configuration &); @@ -82,12 +80,12 @@ public: enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy; unsigned int powerDownTimeout = 3; unsigned int maxActiveTransactions = 64; - sc_time arbitrationDelayFw = SC_ZERO_TIME; - sc_time arbitrationDelayBw = SC_ZERO_TIME; - sc_time thinkDelayFw = SC_ZERO_TIME; - sc_time thinkDelayBw = SC_ZERO_TIME; - sc_time phyDelayFw = SC_ZERO_TIME; - sc_time phyDelayBw = SC_ZERO_TIME; + sc_core::sc_time arbitrationDelayFw = sc_core::SC_ZERO_TIME; + sc_core::sc_time arbitrationDelayBw = sc_core::SC_ZERO_TIME; + sc_core::sc_time thinkDelayFw = sc_core::SC_ZERO_TIME; + sc_core::sc_time thinkDelayBw = sc_core::SC_ZERO_TIME; + sc_core::sc_time phyDelayFw = sc_core::SC_ZERO_TIME; + sc_core::sc_time phyDelayBw = sc_core::SC_ZERO_TIME; // SimConfig std::string simulationName = "default"; diff --git a/DRAMSys/library/src/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/configuration/TemperatureSimConfig.h index b7c8431a..48f0169e 100644 --- a/DRAMSys/library/src/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/configuration/TemperatureSimConfig.h @@ -38,11 +38,12 @@ #ifndef TEMPERATURESIMCONFIG_H #define TEMPERATURESIMCONFIG_H -#include -#include #include +#include + +#include +#include #include "../common/DebugManager.h" -#include "../common/utils.h" struct TemperatureSimConfig { @@ -52,7 +53,7 @@ struct TemperatureSimConfig void setPathToResources(std::string path) { - pathToResources = path; + pathToResources = std::move(path); } // Static Temperature Simulation parameters @@ -60,7 +61,7 @@ struct TemperatureSimConfig // Thermal Simulation parameters double thermalSimPeriod; - enum sc_time_unit thermalSimUnit; + enum sc_core::sc_time_unit thermalSimUnit; std::string iceServerIp; unsigned int iceServerPort; unsigned int simPeriodAdjustFactor; @@ -93,10 +94,10 @@ struct TemperatureSimConfig } else { - for (auto it : powInfoElem["powerInfo"].items()) + for (const auto& it : powInfoElem["powerInfo"].items()) { // Load initial power values for all devices - auto value= it.value(); + auto value = it.value(); float pow = value["init_pow"]; powerInitialValues.push_back(pow); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index cba95c58..b8638abc 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -35,11 +35,7 @@ #include "MemSpec.h" -#include -#include -#include "../../controller/Command.h" -#include "../Configuration.h" - +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index d8bdec44..b4bb0a09 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -38,12 +38,14 @@ #ifndef MEMSPEC_H #define MEMSPEC_H -#include #include -#include "../../common/dramExtensions.h" -#include "../../controller/Command.h" +#include + +#include +#include #include "../../common/utils.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" +#include "../../controller/Command.h" class MemSpec { @@ -66,7 +68,7 @@ public: // Clock const double fCKMHz; - const sc_time tCK; + const sc_core::sc_time tCK; const std::string memoryId; const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO, @@ -74,16 +76,16 @@ public: virtual ~MemSpec() = default; - virtual sc_time getRefreshIntervalAB() const; - virtual sc_time getRefreshIntervalPB() const; - virtual sc_time getRefreshIntervalSB() const; + virtual sc_core::sc_time getRefreshIntervalAB() const; + virtual sc_core::sc_time getRefreshIntervalPB() const; + virtual sc_core::sc_time getRefreshIntervalSB() const; virtual bool hasRasAndCasBus() const; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const = 0; + virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0; - sc_time getCommandLength(Command) const; + sc_core::sc_time getCommandLength(Command) const; uint64_t getSimMemSizeInBytes() const; protected: @@ -96,7 +98,7 @@ protected: // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; - sc_time burstDuration; + sc_core::sc_time burstDuration; uint64_t memorySizeBytes; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 5144172e..020b0b9f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecDDR3.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; @@ -139,7 +143,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index d238031b..711df6d5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -36,6 +36,7 @@ #ifndef MEMSPECDDR3_H #define MEMSPECDDR3_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,33 +46,33 @@ public: explicit MemSpecDDR3(nlohmann::json &memspec); // Memspec Variables: - const sc_time tCKE; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tRTP; - const sc_time tWL; - const sc_time tWR; - const sc_time tXP; - const sc_time tXS; - const sc_time tREFI; - const sc_time tRFC; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tCCD; - const sc_time tFAW; - const sc_time tRRD; - const sc_time tWTR; - const sc_time tXPDLL; - const sc_time tXSDLL; - const sc_time tAL; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tREFPDEN; - const sc_time tRTRS; + const sc_core::sc_time tCKE; + const sc_core::sc_time tPD; + const sc_core::sc_time tCKESR; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCD; + const sc_core::sc_time tRL; + const sc_core::sc_time tRTP; + const sc_core::sc_time tWL; + const sc_core::sc_time tWR; + const sc_core::sc_time tXP; + const sc_core::sc_time tXS; + const sc_core::sc_time tREFI; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRP; + const sc_core::sc_time tDQSCK; + const sc_core::sc_time tCCD; + const sc_core::sc_time tFAW; + const sc_core::sc_time tRRD; + const sc_core::sc_time tWTR; + const sc_core::sc_time tXPDLL; + const sc_core::sc_time tXSDLL; + const sc_core::sc_time tAL; + const sc_core::sc_time tACTPDEN; + const sc_core::sc_time tPRPDEN; + const sc_core::sc_time tREFPDEN; + const sc_core::sc_time tRTRS; // Currents and Voltages: const double iDD0; @@ -87,9 +88,9 @@ public: const double iDD3P0; const double iDD3P1; - sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 72dfffe7..25c5970a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -33,9 +33,12 @@ * Lukas Steiner */ -#include "MemSpecDDR4.h" -#include "../Configuration.h" +#include +#include "../../common/utils.h" +#include "MemSpecDDR4.h" + +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 85571ae7..14adddd7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -36,6 +36,7 @@ #ifndef MEMSPECDDR4_H #define MEMSPECDDR4_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,38 +46,38 @@ public: explicit MemSpecDDR4(nlohmann::json &memspec); // Memspec Variables: - const sc_time tCKE; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tRPRE; - const sc_time tRTP; - const sc_time tWL; - const sc_time tWPRE; - const sc_time tWR; - const sc_time tXP; - const sc_time tXS; - const sc_time tREFI; - const sc_time tRFC; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tCCD_S; - const sc_time tCCD_L; - const sc_time tFAW; - const sc_time tRRD_S; - const sc_time tRRD_L; - const sc_time tWTR_S; - const sc_time tWTR_L; - const sc_time tAL; - const sc_time tXPDLL; - const sc_time tXSDLL; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tREFPDEN; - const sc_time tRTRS; + const sc_core::sc_time tCKE; + const sc_core::sc_time tPD; + const sc_core::sc_time tCKESR; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCD; + const sc_core::sc_time tRL; + const sc_core::sc_time tRPRE; + const sc_core::sc_time tRTP; + const sc_core::sc_time tWL; + const sc_core::sc_time tWPRE; + const sc_core::sc_time tWR; + const sc_core::sc_time tXP; + const sc_core::sc_time tXS; + const sc_core::sc_time tREFI; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRP; + const sc_core::sc_time tDQSCK; + const sc_core::sc_time tCCD_S; + const sc_core::sc_time tCCD_L; + const sc_core::sc_time tFAW; + const sc_core::sc_time tRRD_S; + const sc_core::sc_time tRRD_L; + const sc_core::sc_time tWTR_S; + const sc_core::sc_time tWTR_L; + const sc_core::sc_time tAL; + const sc_core::sc_time tXPDLL; + const sc_core::sc_time tXSDLL; + const sc_core::sc_time tACTPDEN; + const sc_core::sc_time tPRPDEN; + const sc_core::sc_time tREFPDEN; + const sc_core::sc_time tRTRS; // Currents and Voltages: const double iDD0; @@ -95,9 +96,9 @@ public: const double iDD62; const double vDD2; - sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index a21699f5..4ddf7f33 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -33,9 +33,12 @@ * Lukas Steiner */ -#include "MemSpecDDR5.h" -#include "../Configuration.h" +#include +#include "../../common/utils.h" +#include "MemSpecDDR5.h" + +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index 62076591..f6daa0a0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -36,6 +36,7 @@ #ifndef MEMSPECDDR5_H #define MEMSPECDDR5_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -53,66 +54,66 @@ public: const unsigned refMode; // Memspec Variables: - const sc_time tRCD; - const sc_time tPPD; - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRL; - const sc_time tRTP; - const sc_time tRPRE; - const sc_time tRPST; - const sc_time tRDDQS; - const sc_time tWL; - const sc_time tWPRE; - const sc_time tWPST; - const sc_time tWR; - const sc_time tCCD_L_slr; - const sc_time tCCD_L_WR_slr; - const sc_time tCCD_L_WR2_slr; - const sc_time tCCD_S_slr; - const sc_time tCCD_S_WR_slr; - const sc_time tCCD_dlr; - const sc_time tCCD_WR_dlr; - const sc_time tCCD_WR_dpr; - const sc_time tRRD_L_slr; - const sc_time tRRD_S_slr; - const sc_time tRRD_dlr; - const sc_time tFAW_slr; - const sc_time tFAW_dlr; - const sc_time tWTR_L; - const sc_time tWTR_S; - const sc_time tRFC_slr; - const sc_time tRFC_dlr; - const sc_time tRFC_dpr; - const sc_time tRFCsb_slr; - const sc_time tRFCsb_dlr; - const sc_time tREFI; - const sc_time tREFIsb; - const sc_time tREFSBRD_slr; - const sc_time tREFSBRD_dlr; - const sc_time tRTRS; + const sc_core::sc_time tRCD; + const sc_core::sc_time tPPD; + const sc_core::sc_time tRP; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRL; + const sc_core::sc_time tRTP; + const sc_core::sc_time tRPRE; + const sc_core::sc_time tRPST; + const sc_core::sc_time tRDDQS; + const sc_core::sc_time tWL; + const sc_core::sc_time tWPRE; + const sc_core::sc_time tWPST; + const sc_core::sc_time tWR; + const sc_core::sc_time tCCD_L_slr; + const sc_core::sc_time tCCD_L_WR_slr; + const sc_core::sc_time tCCD_L_WR2_slr; + const sc_core::sc_time tCCD_S_slr; + const sc_core::sc_time tCCD_S_WR_slr; + const sc_core::sc_time tCCD_dlr; + const sc_core::sc_time tCCD_WR_dlr; + const sc_core::sc_time tCCD_WR_dpr; + const sc_core::sc_time tRRD_L_slr; + const sc_core::sc_time tRRD_S_slr; + const sc_core::sc_time tRRD_dlr; + const sc_core::sc_time tFAW_slr; + const sc_core::sc_time tFAW_dlr; + const sc_core::sc_time tWTR_L; + const sc_core::sc_time tWTR_S; + const sc_core::sc_time tRFC_slr; + const sc_core::sc_time tRFC_dlr; + const sc_core::sc_time tRFC_dpr; + const sc_core::sc_time tRFCsb_slr; + const sc_core::sc_time tRFCsb_dlr; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFIsb; + const sc_core::sc_time tREFSBRD_slr; + const sc_core::sc_time tREFSBRD_dlr; + const sc_core::sc_time tRTRS; - const sc_time tCPDED; - const sc_time tPD; - const sc_time tXP; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tREFPDEN; + const sc_core::sc_time tCPDED; + const sc_core::sc_time tPD; + const sc_core::sc_time tXP; + const sc_core::sc_time tACTPDEN; + const sc_core::sc_time tPRPDEN; + const sc_core::sc_time tREFPDEN; - const sc_time shortCmdOffset; - const sc_time longCmdOffset; + const sc_core::sc_time shortCmdOffset; + const sc_core::sc_time longCmdOffset; - const sc_time tBURST16; - const sc_time tBURST32; + const sc_core::sc_time tBURST16; + const sc_core::sc_time tBURST32; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalSB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalSB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 5de6bba8..83efd921 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecGDDR5.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index 2fe5a733..b66df343 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -36,6 +36,7 @@ #ifndef MEMSPECGDDR5_H #define MEMSPECGDDR5_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,50 +46,50 @@ public: explicit MemSpecGDDR5(nlohmann::json &memspec); // Memspec Variables: - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRTP; - const sc_time tRRDS; - const sc_time tRRDL; - const sc_time tCCDS; - const sc_time tCCDL; - const sc_time tCL; - const sc_time tWCK2CKPIN; - const sc_time tWCK2CK; - const sc_time tWCK2DQO; - const sc_time tRTW; - const sc_time tWL; - const sc_time tWCK2DQI; - const sc_time tWR; - const sc_time tWTRS; - const sc_time tWTRL; - const sc_time tCKE; - const sc_time tPD; - const sc_time tXPN; - const sc_time tREFI; - const sc_time tREFIPB; - const sc_time tRFC; - const sc_time tRFCPB; - const sc_time tRREFD; - const sc_time tXS; - const sc_time tFAW; - const sc_time t32AW; + const sc_core::sc_time tRP; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCDRD; + const sc_core::sc_time tRCDWR; + const sc_core::sc_time tRTP; + const sc_core::sc_time tRRDS; + const sc_core::sc_time tRRDL; + const sc_core::sc_time tCCDS; + const sc_core::sc_time tCCDL; + const sc_core::sc_time tCL; + const sc_core::sc_time tWCK2CKPIN; + const sc_core::sc_time tWCK2CK; + const sc_core::sc_time tWCK2DQO; + const sc_core::sc_time tRTW; + const sc_core::sc_time tWL; + const sc_core::sc_time tWCK2DQI; + const sc_core::sc_time tWR; + const sc_core::sc_time tWTRS; + const sc_core::sc_time tWTRL; + const sc_core::sc_time tCKE; + const sc_core::sc_time tPD; + const sc_core::sc_time tXPN; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFIPB; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRFCPB; + const sc_core::sc_time tRREFD; + const sc_core::sc_time tXS; + const sc_core::sc_time tFAW; + const sc_core::sc_time t32AW; // sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; // sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; - const sc_time tPPD; - const sc_time tLK; - const sc_time tRTRS; + const sc_core::sc_time tPPD; + const sc_core::sc_time tLK; + const sc_core::sc_time tRTRS; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalPB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index a00bcc26..3481c139 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -32,9 +32,12 @@ * Authors: * Lukas Steiner */ +#include +#include "../../common/utils.h" #include "MemSpecGDDR5X.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index ab9c0c5c..4d181f12 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -36,6 +36,7 @@ #ifndef MEMSPECGDDR5X_H #define MEMSPECGDDR5X_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,50 +46,50 @@ public: explicit MemSpecGDDR5X(nlohmann::json &memspec); // Memspec Variables: - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRTP; - const sc_time tRRDS; - const sc_time tRRDL; - const sc_time tCCDS; - const sc_time tCCDL; - const sc_time tRL; - const sc_time tWCK2CKPIN; - const sc_time tWCK2CK; - const sc_time tWCK2DQO; - const sc_time tRTW; - const sc_time tWL; - const sc_time tWCK2DQI; - const sc_time tWR; - const sc_time tWTRS; - const sc_time tWTRL; - const sc_time tCKE; - const sc_time tPD; - const sc_time tXP; - const sc_time tREFI; - const sc_time tREFIPB; - const sc_time tRFC; - const sc_time tRFCPB; - const sc_time tRREFD; - const sc_time tXS; - const sc_time tFAW; - const sc_time t32AW; + const sc_core::sc_time tRP; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCDRD; + const sc_core::sc_time tRCDWR; + const sc_core::sc_time tRTP; + const sc_core::sc_time tRRDS; + const sc_core::sc_time tRRDL; + const sc_core::sc_time tCCDS; + const sc_core::sc_time tCCDL; + const sc_core::sc_time tRL; + const sc_core::sc_time tWCK2CKPIN; + const sc_core::sc_time tWCK2CK; + const sc_core::sc_time tWCK2DQO; + const sc_core::sc_time tRTW; + const sc_core::sc_time tWL; + const sc_core::sc_time tWCK2DQI; + const sc_core::sc_time tWR; + const sc_core::sc_time tWTRS; + const sc_core::sc_time tWTRL; + const sc_core::sc_time tCKE; + const sc_core::sc_time tPD; + const sc_core::sc_time tXP; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFIPB; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRFCPB; + const sc_core::sc_time tRREFD; + const sc_core::sc_time tXS; + const sc_core::sc_time tFAW; + const sc_core::sc_time t32AW; // sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; // sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; - const sc_time tPPD; - const sc_time tLK; - const sc_time tRTRS; + const sc_core::sc_time tPPD; + const sc_core::sc_time tLK; + const sc_core::sc_time tRTRS; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalPB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index d305cf15..15748eda 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecGDDR6.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index e39165e8..a28308bb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -36,6 +36,7 @@ #ifndef MEMSPECGDDR6_H #define MEMSPECGDDR6_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,52 +46,52 @@ public: explicit MemSpecGDDR6(nlohmann::json &memspec); // Memspec Variables: - const sc_time tRP; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRTP; - const sc_time tRRDS; - const sc_time tRRDL; - const sc_time tCCDS; - const sc_time tCCDL; - const sc_time tRL; - const sc_time tWCK2CKPIN; - const sc_time tWCK2CK; - const sc_time tWCK2DQO; - const sc_time tRTW; - const sc_time tWL; - const sc_time tWCK2DQI; - const sc_time tWR; - const sc_time tWTRS; - const sc_time tWTRL; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tXP; - const sc_time tREFI; - const sc_time tREFIPB; - const sc_time tRFC; - const sc_time tRFCPB; - const sc_time tRREFD; - const sc_time tXS; - const sc_time tFAW; + const sc_core::sc_time tRP; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCDRD; + const sc_core::sc_time tRCDWR; + const sc_core::sc_time tRTP; + const sc_core::sc_time tRRDS; + const sc_core::sc_time tRRDL; + const sc_core::sc_time tCCDS; + const sc_core::sc_time tCCDL; + const sc_core::sc_time tRL; + const sc_core::sc_time tWCK2CKPIN; + const sc_core::sc_time tWCK2CK; + const sc_core::sc_time tWCK2DQO; + const sc_core::sc_time tRTW; + const sc_core::sc_time tWL; + const sc_core::sc_time tWCK2DQI; + const sc_core::sc_time tWR; + const sc_core::sc_time tWTRS; + const sc_core::sc_time tWTRL; + const sc_core::sc_time tPD; + const sc_core::sc_time tCKESR; + const sc_core::sc_time tXP; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFIPB; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRFCPB; + const sc_core::sc_time tRREFD; + const sc_core::sc_time tXS; + const sc_core::sc_time tFAW; // sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; // sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; - const sc_time tPPD; - const sc_time tLK; - const sc_time tACTPDE; - const sc_time tPREPDE; - const sc_time tREFPDE; - const sc_time tRTRS; + const sc_core::sc_time tPPD; + const sc_core::sc_time tLK; + const sc_core::sc_time tACTPDE; + const sc_core::sc_time tPREPDE; + const sc_core::sc_time tREFPDE; + const sc_core::sc_time tRTRS; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalPB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index a49a3c47..d6c28cf1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecHBM2.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 04ff4d81..5eeb6355 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -36,6 +36,7 @@ #ifndef MEMSPECHBM2_H #define MEMSPECHBM2_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,47 +46,47 @@ public: explicit MemSpecHBM2(nlohmann::json &memspec); // Memspec Variables: - const sc_time tDQSCK; + const sc_core::sc_time tDQSCK; // sc_time tDQSQ; // TODO: check actual value of this parameter - const sc_time tRC; - const sc_time tRAS; - const sc_time tRCDRD; - const sc_time tRCDWR; - const sc_time tRRDL; - const sc_time tRRDS; - const sc_time tFAW; - const sc_time tRTP; - const sc_time tRP; - const sc_time tRL; - const sc_time tWL; - const sc_time tPL; - const sc_time tWR; - const sc_time tCCDL; - const sc_time tCCDS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRCDRD; + const sc_core::sc_time tRCDWR; + const sc_core::sc_time tRRDL; + const sc_core::sc_time tRRDS; + const sc_core::sc_time tFAW; + const sc_core::sc_time tRTP; + const sc_core::sc_time tRP; + const sc_core::sc_time tRL; + const sc_core::sc_time tWL; + const sc_core::sc_time tPL; + const sc_core::sc_time tWR; + const sc_core::sc_time tCCDL; + const sc_core::sc_time tCCDS; // sc_time tCCDR; // TODO: consecutive reads to different stack IDs - const sc_time tWTRL; - const sc_time tWTRS; - const sc_time tRTW; - const sc_time tXP; - const sc_time tCKE; - const sc_time tPD; // = tCKE; - const sc_time tCKESR; // = tCKE + tCK; - const sc_time tXS; - const sc_time tRFC; - const sc_time tRFCSB; - const sc_time tRREFD; - const sc_time tREFI; - const sc_time tREFISB; + const sc_core::sc_time tWTRL; + const sc_core::sc_time tWTRS; + const sc_core::sc_time tRTW; + const sc_core::sc_time tXP; + const sc_core::sc_time tCKE; + const sc_core::sc_time tPD; // = tCKE; + const sc_core::sc_time tCKESR; // = tCKE + tCK; + const sc_core::sc_time tXS; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRFCSB; + const sc_core::sc_time tRREFD; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFISB; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalPB() const override; bool hasRasAndCasBus() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 2fe87bb7..8a21c901 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecLPDDR4.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 6e65d09f..129328ae 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -36,6 +36,7 @@ #ifndef MEMSPECLPDDR4_H #define MEMSPECLPDDR4_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,45 +46,45 @@ public: explicit MemSpecLPDDR4(nlohmann::json &memspec); // Memspec Variables: - const sc_time tREFI; - const sc_time tREFIpb; - const sc_time tRFCab; - const sc_time tRFCpb; - const sc_time tRAS; - const sc_time tRPab; - const sc_time tRPpb; - const sc_time tRCpb; - const sc_time tRCab; - const sc_time tPPD; - const sc_time tRCD; - const sc_time tFAW; - const sc_time tRRD; - const sc_time tCCD; - const sc_time tRL; - const sc_time tRPST; - const sc_time tDQSCK; - const sc_time tRTP; - const sc_time tWL; - const sc_time tDQSS; - const sc_time tDQS2DQ; - const sc_time tWR; - const sc_time tWPRE; - const sc_time tWTR; - const sc_time tXP; - const sc_time tSR; - const sc_time tXSR; - const sc_time tESCKE; - const sc_time tCKE; - const sc_time tCMDCKE; - const sc_time tRTRS; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFIpb; + const sc_core::sc_time tRFCab; + const sc_core::sc_time tRFCpb; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRPab; + const sc_core::sc_time tRPpb; + const sc_core::sc_time tRCpb; + const sc_core::sc_time tRCab; + const sc_core::sc_time tPPD; + const sc_core::sc_time tRCD; + const sc_core::sc_time tFAW; + const sc_core::sc_time tRRD; + const sc_core::sc_time tCCD; + const sc_core::sc_time tRL; + const sc_core::sc_time tRPST; + const sc_core::sc_time tDQSCK; + const sc_core::sc_time tRTP; + const sc_core::sc_time tWL; + const sc_core::sc_time tDQSS; + const sc_core::sc_time tDQS2DQ; + const sc_core::sc_time tWR; + const sc_core::sc_time tWPRE; + const sc_core::sc_time tWTR; + const sc_core::sc_time tXP; + const sc_core::sc_time tSR; + const sc_core::sc_time tXSR; + const sc_core::sc_time tESCKE; + const sc_core::sc_time tCKE; + const sc_core::sc_time tCMDCKE; + const sc_core::sc_time tRTRS; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalPB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp index 626e374a..d721fe7f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecSTTMRAM.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h index e4eddfce..e30b22b2 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h @@ -36,6 +36,7 @@ #ifndef MEMSPECSTTMRAM_H #define MEMSPECSTTMRAM_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,35 +46,35 @@ public: explicit MemSpecSTTMRAM(nlohmann::json &memspec); // Memspec Variables: - const sc_time tCKE; - const sc_time tPD; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tRTP; - const sc_time tWL; - const sc_time tWR; - const sc_time tXP; - const sc_time tXS; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tCCD; - const sc_time tFAW; - const sc_time tRRD; - const sc_time tWTR; - const sc_time tXPDLL; - const sc_time tXSDLL; - const sc_time tAL; - const sc_time tACTPDEN; - const sc_time tPRPDEN; - const sc_time tRTRS; + const sc_core::sc_time tCKE; + const sc_core::sc_time tPD; + const sc_core::sc_time tCKESR; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCD; + const sc_core::sc_time tRL; + const sc_core::sc_time tRTP; + const sc_core::sc_time tWL; + const sc_core::sc_time tWR; + const sc_core::sc_time tXP; + const sc_core::sc_time tXS; + const sc_core::sc_time tRP; + const sc_core::sc_time tDQSCK; + const sc_core::sc_time tCCD; + const sc_core::sc_time tFAW; + const sc_core::sc_time tRRD; + const sc_core::sc_time tWTR; + const sc_core::sc_time tXPDLL; + const sc_core::sc_time tXSDLL; + const sc_core::sc_time tAL; + const sc_core::sc_time tACTPDEN; + const sc_core::sc_time tPRPDEN; + const sc_core::sc_time tRTRS; // Currents and Voltages: // TODO: to be completed - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index fbd39ef7..7a7694d1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecWideIO.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index bf3b88b7..3b952621 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -36,6 +36,7 @@ #ifndef MEMSPECWIDEIO_H #define MEMSPECWIDEIO_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,27 +46,27 @@ public: explicit MemSpecWideIO(nlohmann::json &memspec); // Memspec Variables: - const sc_time tCKE; - const sc_time tCKESR; - const sc_time tRAS; - const sc_time tRC; - const sc_time tRCD; - const sc_time tRL; - const sc_time tWL; - const sc_time tWR; - const sc_time tXP; - const sc_time tXSR; - const sc_time tREFI; - const sc_time tRFC; - const sc_time tRP; - const sc_time tDQSCK; - const sc_time tAC; - const sc_time tCCD_R; - const sc_time tCCD_W; - const sc_time tRRD; - const sc_time tTAW; - const sc_time tWTR; - const sc_time tRTRS; + const sc_core::sc_time tCKE; + const sc_core::sc_time tCKESR; + const sc_core::sc_time tRAS; + const sc_core::sc_time tRC; + const sc_core::sc_time tRCD; + const sc_core::sc_time tRL; + const sc_core::sc_time tWL; + const sc_core::sc_time tWR; + const sc_core::sc_time tXP; + const sc_core::sc_time tXSR; + const sc_core::sc_time tREFI; + const sc_core::sc_time tRFC; + const sc_core::sc_time tRP; + const sc_core::sc_time tDQSCK; + const sc_core::sc_time tAC; + const sc_core::sc_time tCCD_R; + const sc_core::sc_time tCCD_W; + const sc_core::sc_time tRRD; + const sc_core::sc_time tTAW; + const sc_core::sc_time tWTR; + const sc_core::sc_time tRTRS; // Currents and Voltages: const double iDD0; @@ -93,9 +94,9 @@ public: const double iDD62; const double vDD2; - sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 1077d0b5..93ba82b5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -33,8 +33,12 @@ * Lukas Steiner */ +#include + +#include "../../common/utils.h" #include "MemSpecWideIO2.h" +using namespace sc_core; using namespace tlm; using json = nlohmann::json; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 6069e56a..e2fff51a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -36,6 +36,7 @@ #ifndef MEMSPECWIDEIO2_H #define MEMSPECWIDEIO2_H +#include #include "MemSpec.h" #include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" @@ -45,39 +46,39 @@ public: explicit MemSpecWideIO2(nlohmann::json &memspec); // Memspec Variables: - const sc_time tDQSCK; - const sc_time tDQSS; - const sc_time tCKE; - const sc_time tRL; - const sc_time tWL; - const sc_time tRCpb; - const sc_time tRCab; - const sc_time tCKESR; - const sc_time tXSR; - const sc_time tXP; - const sc_time tCCD; - const sc_time tRTP; - const sc_time tRCD; - const sc_time tRPpb; - const sc_time tRPab; - const sc_time tRAS; - const sc_time tWR; - const sc_time tWTR; - const sc_time tRRD; - const sc_time tFAW; - const sc_time tREFI; - const sc_time tREFIpb; - const sc_time tRFCab; - const sc_time tRFCpb; - const sc_time tRTRS; + const sc_core::sc_time tDQSCK; + const sc_core::sc_time tDQSS; + const sc_core::sc_time tCKE; + const sc_core::sc_time tRL; + const sc_core::sc_time tWL; + const sc_core::sc_time tRCpb; + const sc_core::sc_time tRCab; + const sc_core::sc_time tCKESR; + const sc_core::sc_time tXSR; + const sc_core::sc_time tXP; + const sc_core::sc_time tCCD; + const sc_core::sc_time tRTP; + const sc_core::sc_time tRCD; + const sc_core::sc_time tRPpb; + const sc_core::sc_time tRPab; + const sc_core::sc_time tRAS; + const sc_core::sc_time tWR; + const sc_core::sc_time tWTR; + const sc_core::sc_time tRRD; + const sc_core::sc_time tFAW; + const sc_core::sc_time tREFI; + const sc_core::sc_time tREFIpb; + const sc_core::sc_time tRFCab; + const sc_core::sc_time tRFCpb; + const sc_core::sc_time tRTRS; // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + sc_core::sc_time getRefreshIntervalAB() const override; + sc_core::sc_time getRefreshIntervalPB() const override; - sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index d94ffd03..6eb46c38 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -32,9 +32,12 @@ * Author: Lukas Steiner */ +#include + #include "BankMachine.h" #include "../configuration/Configuration.h" +using namespace sc_core; using namespace tlm; BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index fc409123..55f44340 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -35,9 +35,8 @@ #ifndef BANKMACHINE_H #define BANKMACHINE_H -#include -#include -#include +#include +#include #include "../common/dramExtensions.h" #include "Command.h" #include "scheduler/SchedulerIF.h" @@ -47,7 +46,7 @@ class BankMachine { public: virtual ~BankMachine() = default; - virtual sc_time start() = 0; + virtual sc_core::sc_time start() = 0; CommandTuple::Type getNextCommand(); void updateState(Command); void block(); @@ -69,7 +68,7 @@ protected: Command nextCommand = Command::NOP; State state = State::Precharged; Row openRow; - sc_time timeToSchedule = sc_max_time(); + sc_core::sc_time timeToSchedule = sc_core::sc_max_time(); Rank rank = Rank(0); BankGroup bankgroup = BankGroup(0); Bank bank; @@ -81,28 +80,28 @@ class BankMachineOpen final : public BankMachine { public: BankMachineOpen(SchedulerIF *, CheckerIF *, Bank); - sc_time start() override; + sc_core::sc_time start() override; }; class BankMachineClosed final : public BankMachine { public: BankMachineClosed(SchedulerIF *, CheckerIF *, Bank); - sc_time start() override; + sc_core::sc_time start() override; }; class BankMachineOpenAdaptive final : public BankMachine { public: BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank); - sc_time start() override; + sc_core::sc_time start() override; }; class BankMachineClosedAdaptive final : public BankMachine { public: BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank); - sc_time start() override; + sc_core::sc_time start() override; }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 39b17f74..0f6664df 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -35,8 +35,8 @@ * Matthias Jung */ +#include #include "Command.h" -#include using namespace tlm; using namespace DRAMPower; diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index db48cd85..bb5af1da 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -38,11 +38,10 @@ #include #include -#include -#include -#include -#include -#include +#include + +#include +#include #include "../common/third_party/DRAMPower/src/MemCommand.h" // DO NOT CHANGE THE ORDER! @@ -137,7 +136,7 @@ tlm::tlm_phase getEndPhase(tlm::tlm_phase); struct CommandTuple { - using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_time>; + using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_core::sc_time>; enum Accessor { Command = 0, diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index c0c116e5..772b9062 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -36,7 +36,7 @@ #include "../configuration/Configuration.h" #include "../common/dramExtensions.h" -#include "Command.h" + #include "checker/CheckerDDR3.h" #include "checker/CheckerDDR4.h" #include "checker/CheckerDDR5.h" @@ -62,6 +62,7 @@ #include "powerdown/PowerDownManagerStaggered.h" #include "powerdown/PowerDownManagerDummy.h" +using namespace sc_core; using namespace tlm; Controller::Controller(const sc_module_name &name) : diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index c6f268ec..198f7298 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -35,19 +35,14 @@ #ifndef CONTROLLER_H #define CONTROLLER_H -#include + #include -#include -#include -#include -#include -#include + +#include +#include #include "ControllerIF.h" -#include "../common/dramExtensions.h" -#include "BankMachine.h" +#include "Command.h" #include "cmdmux/CmdMuxIF.h" -#include "scheduler/SchedulerIF.h" -#include "../common/DebugManager.h" #include "checker/CheckerIF.h" #include "refresh/RefreshManagerIF.h" #include "powerdown/PowerDownManagerIF.h" @@ -60,27 +55,29 @@ class PowerDownManagerStaggered; class Controller : public ControllerIF { public: - explicit Controller(const sc_module_name &name); + explicit Controller(const sc_core::sc_module_name &name); SC_HAS_PROCESS(Controller); ~Controller() override; protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; unsigned int transport_dbg(tlm::tlm_generic_payload &trans) override; - virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time); - virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time); + virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_core::sc_time); + virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_core::sc_time); virtual void controllerMethod(); SchedulerIF *scheduler; const MemSpec *memSpec; - sc_time thinkDelayFw; - sc_time thinkDelayBw; - sc_time phyDelayFw; - sc_time phyDelayBw; + sc_core::sc_time thinkDelayFw; + sc_core::sc_time thinkDelayBw; + sc_core::sc_time phyDelayFw; + sc_core::sc_time phyDelayBw; private: unsigned totalNumberOfPayloads = 0; @@ -98,13 +95,13 @@ private: struct Transaction { tlm::tlm_generic_payload *payload = nullptr; - sc_time time = sc_max_time(); + sc_core::sc_time time = sc_core::sc_max_time(); } transToAcquire, transToRelease; void manageResponses(); - void manageRequests(const sc_time &delay); + void manageRequests(const sc_core::sc_time &delay); - sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; + sc_core::sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; }; #endif // CONTROLLER_H diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index ce9a191a..67c0c4a9 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -37,15 +37,17 @@ #ifndef CONTROLLERIF_H #define CONTROLLERIF_H -#include -#include +#include + +#include +#include #include #include #include "../configuration/Configuration.h" // Utiliy class to pass around the DRAMSys, without having to propagate the template defintions // throughout all classes -class ControllerIF : public sc_module +class ControllerIF : public sc_core::sc_module { public: // Already create and bind sockets to the virtual functions @@ -53,14 +55,14 @@ public: tlm_utils::simple_initiator_socket iSocket; // DRAM side // Destructor - virtual ~ControllerIF() + ~ControllerIF() override { - sc_time activeTime = numberOfBeatsServed - / Configuration::getInstance().memSpec->dataRate - * Configuration::getInstance().memSpec->tCK; + sc_core::sc_time activeTime = numberOfBeatsServed + / Configuration::getInstance().memSpec->dataRate + * Configuration::getInstance().memSpec->tCK; - double bandwidth = activeTime / sc_time_stamp(); - double bandwidthWoIdle = activeTime / (sc_time_stamp() - idleTimeCollector.getIdleTime()); + double bandwidth = activeTime / sc_core::sc_time_stamp(); + double bandwidthWoIdle = activeTime / (sc_core::sc_time_stamp() - idleTimeCollector.getIdleTime()); double maxBandwidth = ( // fCK in GHz e.g. 1 [GHz] (tCK in ps): @@ -73,28 +75,28 @@ public: * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM ); std::cout << name() << std::string(" Total Time: ") - << sc_time_stamp().to_string() - << std::endl; + << sc_core::sc_time_stamp().to_string() + << std::endl; std::cout << name() << std::string(" AVG BW: ") - << std::fixed << std::setprecision(2) - << (bandwidth * maxBandwidth) - << " Gb/s (" << (bandwidth * 100) << " %)" - << std::endl; + << std::fixed << std::setprecision(2) + << (bandwidth * maxBandwidth) + << " Gb/s (" << (bandwidth * 100) << " %)" + << std::endl; std::cout << name() << std::string(" AVG BW\\IDLE: ") - << std::fixed << std::setprecision(2) - << (bandwidthWoIdle * maxBandwidth) - << " Gb/s (" << (bandwidthWoIdle * 100) << " %)" - << endl; + << std::fixed << std::setprecision(2) + << (bandwidthWoIdle * maxBandwidth) + << " Gb/s (" << (bandwidthWoIdle * 100) << " %)" + << std::endl; std::cout << name() << std::string(" MAX BW: ") - << std::fixed << std::setprecision(2) - << maxBandwidth << " Gb/s" - << std::endl; + << std::fixed << std::setprecision(2) + << maxBandwidth << " Gb/s" + << std::endl; } protected: // Bind sockets with virtual functions - ControllerIF(const sc_module_name &name) : - sc_module(name), tSocket("tSocket"), iSocket("iSocket") + explicit ControllerIF(const sc_core::sc_module_name &name) + : sc_core::sc_module(name), tSocket("tSocket"), iSocket("iSocket") { tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw); tSocket.register_transport_dbg(this, &ControllerIF::transport_dbg); @@ -103,9 +105,9 @@ protected: SC_HAS_PROCESS(ControllerIF); // Virtual transport functions - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0; + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_core::sc_time &) = 0; virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) = 0; - virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0; + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_core::sc_time &) = 0; // Bandwidth related class IdleTimeCollector @@ -116,7 +118,7 @@ protected: if (!isIdle) { PRINTDEBUGMESSAGE("IdleTimeCollector", "IDLE start"); - idleStart = sc_time_stamp(); + idleStart = sc_core::sc_time_stamp(); isIdle = true; } } @@ -126,20 +128,20 @@ protected: if (isIdle) { PRINTDEBUGMESSAGE("IdleTimeCollector", "IDLE end"); - idleTime += sc_time_stamp() - idleStart; + idleTime += sc_core::sc_time_stamp() - idleStart; isIdle = false; } } - sc_time getIdleTime() + sc_core::sc_time getIdleTime() { return idleTime; } private: bool isIdle = false; - sc_time idleTime = SC_ZERO_TIME; - sc_time idleStart; + sc_core::sc_time idleTime = sc_core::SC_ZERO_TIME; + sc_core::sc_time idleStart; } idleTimeCollector; uint64_t numberOfBeatsServed = 0; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 5ea2751f..254155e3 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -34,7 +34,9 @@ #include "ControllerRecordable.h" #include "../configuration/Configuration.h" +#include "scheduler/SchedulerIF.h" +using namespace sc_core; using namespace tlm; ControllerRecordable::ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder) @@ -112,7 +114,7 @@ void ControllerRecordable::controllerMethod() lastTimeCalled = sc_time_stamp(); const std::vector &bufferDepth = scheduler->getBufferDepth(); - for (size_t index = 0; index < slidingAverageBufferDepth.size(); index++) + for (std::size_t index = 0; index < slidingAverageBufferDepth.size(); index++) slidingAverageBufferDepth[index] += bufferDepth[index] * timeDiff; if (sc_time_stamp() == nextWindowEventTime) @@ -120,7 +122,7 @@ void ControllerRecordable::controllerMethod() windowEvent.notify(windowSizeTime); nextWindowEventTime += windowSizeTime; - for (size_t index = 0; index < slidingAverageBufferDepth.size(); index++) + for (std::size_t index = 0; index < slidingAverageBufferDepth.size(); index++) { windowAverageBufferDepth[index] = slidingAverageBufferDepth[index] / windowSizeTime; slidingAverageBufferDepth[index] = SC_ZERO_TIME; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index efdc449c..d2300f71 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -35,40 +35,42 @@ #ifndef CONTROLLERRECORDABLE_H #define CONTROLLERRECORDABLE_H +#include +#include #include "Controller.h" #include "../common/TlmRecorder.h" class ControllerRecordable final : public Controller { public: - ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder); + ControllerRecordable(const sc_core::sc_module_name &name, TlmRecorder *tlmRecorder); ~ControllerRecordable() override = default; protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay) override; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; - void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time) override; - void sendToDram(Command, tlm::tlm_generic_payload *, sc_time) override; + void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_core::sc_time) override; + void sendToDram(Command, tlm::tlm_generic_payload *, sc_core::sc_time) override; void controllerMethod() override; private: - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay); TlmRecorder *tlmRecorder; - sc_event windowEvent; - sc_time windowSizeTime; - sc_time nextWindowEventTime; - std::vector slidingAverageBufferDepth; + sc_core::sc_event windowEvent; + sc_core::sc_time windowSizeTime; + sc_core::sc_time nextWindowEventTime; + std::vector slidingAverageBufferDepth; std::vector windowAverageBufferDepth; - sc_time lastTimeCalled = SC_ZERO_TIME; + sc_core::sc_time lastTimeCalled = sc_core::SC_ZERO_TIME; uint64_t lastNumberOfBeatsServed = 0; - sc_time activeTimeMultiplier = Configuration::getInstance().memSpec->tCK - / Configuration::getInstance().memSpec->dataRate; + sc_core::sc_time activeTimeMultiplier = Configuration::getInstance().memSpec->tCK + / Configuration::getInstance().memSpec->dataRate; }; #endif // CONTROLLERRECORDABLE_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 809f157e..1c8456f5 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerDDR3.h" +using namespace sc_core; using namespace tlm; CheckerDDR3::CheckerDDR3() diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 30eba198..1fef0f8c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -35,9 +35,10 @@ #ifndef CHECKERDDR3_H #define CHECKERDDR3_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecDDR3.h" #include "../../configuration/Configuration.h" @@ -45,29 +46,29 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR3 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; + std::vector> last4Activates; - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD; - sc_time tWRPRE; - sc_time tWRRD_R; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + sc_core::sc_time tBURST; + sc_core::sc_time tRDWR; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; }; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 19c929c5..b1646e43 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerDDR4.h" +using namespace sc_core; using namespace tlm; CheckerDDR4::CheckerDDR4() diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 967849ae..5323931f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -35,9 +35,10 @@ #ifndef CHECKERDDR4_H #define CHECKERDDR4_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecDDR4.h" #include "../../configuration/Configuration.h" @@ -45,33 +46,33 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR4 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; + std::vector> last4Activates; - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tRDAACT; - sc_time tWRPRE; - sc_time tWRAACT; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + sc_core::sc_time tBURST; + sc_core::sc_time tRDWR; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD_S; + sc_core::sc_time tWRRD_L; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tRDAACT; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRAACT; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; }; #endif // CHECKERDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index b567b9bf..d2de1321 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerDDR5.h" +using namespace sc_core; using namespace tlm; CheckerDDR5::CheckerDDR5() diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.h b/DRAMSys/library/src/controller/checker/CheckerDDR5.h index 5a15b314..27ec6294 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.h @@ -35,9 +35,10 @@ #ifndef CHECKERDDR5_H #define CHECKERDDR5_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecDDR5.h" #include "../../configuration/Configuration.h" #include "../../common/utils.h" @@ -46,25 +47,25 @@ class CheckerDDR5 final : public CheckerIF { public: CheckerDDR5(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecDDR5 *memSpec; - std::vector> lastScheduledByCommandAndDimmRank; - std::vector> lastScheduledByCommandAndPhysicalRank; - std::vector> lastScheduledByCommandAndLogicalRank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndBank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndDimmRank; + std::vector> lastScheduledByCommandAndPhysicalRank; + std::vector> lastScheduledByCommandAndLogicalRank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndBank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; TimeInterval dummyCommandOnBus; - std::vector> lastScheduledByCommandAndBankInGroup; + std::vector> lastScheduledByCommandAndBankInGroup; - std::vector> last4ActivatesPhysical; - std::vector> last4ActivatesLogical; + std::vector> last4ActivatesPhysical; + std::vector> last4ActivatesLogical; std::vector> lastBurstLengthByCommandAndDimmRank; std::vector> lastBurstLengthByCommandAndPhysicalRank; @@ -77,32 +78,32 @@ private: // TODO: store BL of last RD and WR globally or for each hierarchy? - sc_time cmdLengthDiff; + sc_core::sc_time cmdLengthDiff; - sc_time tBURST16; - sc_time tBURST32; - sc_time tWTRA; - sc_time tWRRDA; - sc_time tWRPRE; - sc_time tRDAACT; - sc_time tWRAACT; - sc_time tCCD_L_RTW_slr; - sc_time tCCD_S_RTW_slr; - sc_time tCCD_RTW_dlr; - sc_time tRDRD_dpr; - sc_time tRDRD_ddr; - sc_time tRDWR_dpr; - sc_time tRDWR_ddr; - sc_time tCCD_L_WTR_slr; - sc_time tCCD_S_WTR_slr; - sc_time tCCD_WTR_dlr; - sc_time tWRWR_dpr; - sc_time tWRWR_ddr; - sc_time tWRRD_dpr; - sc_time tWRRD_ddr; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + sc_core::sc_time tBURST16; + sc_core::sc_time tBURST32; + sc_core::sc_time tWTRA; + sc_core::sc_time tWRRDA; + sc_core::sc_time tWRPRE; + sc_core::sc_time tRDAACT; + sc_core::sc_time tWRAACT; + sc_core::sc_time tCCD_L_RTW_slr; + sc_core::sc_time tCCD_S_RTW_slr; + sc_core::sc_time tCCD_RTW_dlr; + sc_core::sc_time tRDRD_dpr; + sc_core::sc_time tRDRD_ddr; + sc_core::sc_time tRDWR_dpr; + sc_core::sc_time tRDWR_ddr; + sc_core::sc_time tCCD_L_WTR_slr; + sc_core::sc_time tCCD_S_WTR_slr; + sc_core::sc_time tCCD_WTR_dlr; + sc_core::sc_time tWRWR_dpr; + sc_core::sc_time tWRWR_ddr; + sc_core::sc_time tWRRD_dpr; + sc_core::sc_time tWRRD_ddr; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; }; #endif // CHECKERDDR5_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 6401f779..32844894 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerGDDR5.h" +using namespace sc_core; using namespace tlm; CheckerGDDR5::CheckerGDDR5() diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index 1cf50e9a..2db98cf1 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -35,9 +35,10 @@ #ifndef CHECKERGDDR5_H #define CHECKERGDDR5_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecGDDR5.h" #include "../../configuration/Configuration.h" @@ -45,33 +46,33 @@ class CheckerGDDR5 final : public CheckerIF { public: CheckerGDDR5(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR5 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + sc_core::sc_time lastCommandOnBus; // 4 and 32 activate window - std::vector> last4Activates; - std::vector> last32Activates; + std::vector> last4Activates; + std::vector> last32Activates; std::vector bankwiseRefreshCounter; - sc_time tBURST; - sc_time tRDSRE; - sc_time tWRSRE; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tWRPRE; + sc_core::sc_time tBURST; + sc_core::sc_time tRDSRE; + sc_core::sc_time tWRSRE; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD_S; + sc_core::sc_time tWRRD_L; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tWRPRE; }; #endif // CHECKERGDDR5_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 0c169f2d..3181b89b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerGDDR5X.h" +using namespace sc_core; using namespace tlm; CheckerGDDR5X::CheckerGDDR5X() diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 1ff2c756..88b8dca3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -35,9 +35,10 @@ #ifndef CHECKERGDDR5X_H #define CHECKERGDDR5X_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecGDDR5X.h" #include "../../configuration/Configuration.h" @@ -45,33 +46,33 @@ class CheckerGDDR5X final : public CheckerIF { public: CheckerGDDR5X(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR5X *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + sc_core::sc_time lastCommandOnBus; // 4 and 32 activate window - std::vector> last4Activates; - std::vector> last32Activates; + std::vector> last4Activates; + std::vector> last32Activates; std::vector bankwiseRefreshCounter; - sc_time tBURST; - sc_time tRDSRE; - sc_time tWRSRE; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tWRPRE; + sc_core::sc_time tBURST; + sc_core::sc_time tRDSRE; + sc_core::sc_time tWRSRE; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD_S; + sc_core::sc_time tWRRD_L; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tWRPRE; }; #endif // CHECKERGDDR5X_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index 1be693bb..a6c9a8c9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerGDDR6.h" +using namespace sc_core; using namespace tlm; CheckerGDDR6::CheckerGDDR6() diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index 16d89bd4..733a4bd7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -35,9 +35,10 @@ #ifndef CHECKERGDDR6_H #define CHECKERGDDR6_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecGDDR6.h" #include "../../configuration/Configuration.h" @@ -45,31 +46,31 @@ class CheckerGDDR6 final : public CheckerIF { public: CheckerGDDR6(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecGDDR6 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // four activate window - std::vector> last4Activates; + std::vector> last4Activates; std::vector bankwiseRefreshCounter; - sc_time tBURST; - sc_time tRDSRE; - sc_time tWRSRE; - sc_time tRDWR_R; - sc_time tWRRD_S; - sc_time tWRRD_L; - sc_time tWRRD_R; - sc_time tWRPRE; + sc_core::sc_time tBURST; + sc_core::sc_time tRDSRE; + sc_core::sc_time tWRSRE; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD_S; + sc_core::sc_time tWRRD_L; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tWRPRE; }; #endif // CHECKERGDDR6_H diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index f229c732..7f479656 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerHBM2.h" +using namespace sc_core; using namespace tlm; CheckerHBM2::CheckerHBM2() diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 674b69a4..833d3214 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -35,9 +35,10 @@ #ifndef CHECKERHBM2_H #define CHECKERHBM2_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecHBM2.h" #include "../../configuration/Configuration.h" @@ -45,34 +46,34 @@ class CheckerHBM2 final : public CheckerIF { public: CheckerHBM2(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecHBM2 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndBankGroup; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; - sc_time lastCommandOnRasBus; - sc_time lastCommandOnCasBus; + sc_core::sc_time lastCommandOnRasBus; + sc_core::sc_time lastCommandOnCasBus; // Four activate window - std::vector> last4Activates; + std::vector> last4Activates; std::vector bankwiseRefreshCounter; - sc_time tBURST; - sc_time tRDPDE; - sc_time tRDSRE; - sc_time tWRPRE; - sc_time tWRPDE; - sc_time tWRAPDE; - sc_time tRTWR; - sc_time tWRRDS; - sc_time tWRRDL; - sc_time tWRRDR; + sc_core::sc_time tBURST; + sc_core::sc_time tRDPDE; + sc_core::sc_time tRDSRE; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRPDE; + sc_core::sc_time tWRAPDE; + sc_core::sc_time tRTWR; + sc_core::sc_time tWRRDS; + sc_core::sc_time tWRRDL; + sc_core::sc_time tWRRDR; }; #endif // CHECKERHBM2_H diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 7b3e5eb7..d717a5d2 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -35,18 +35,15 @@ #ifndef CHECKERIF_H #define CHECKERIF_H -#include -#include +#include #include "../Command.h" -#include "../../common/dramExtensions.h" -#include "../../common/DebugManager.h" class CheckerIF { public: virtual ~CheckerIF() = default; - virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0; + virtual sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0; virtual void insert(Command command, tlm::tlm_generic_payload *payload) = 0; }; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 1ba29f76..54e6fdf2 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerLPDDR4.h" +using namespace sc_core; using namespace tlm; CheckerLPDDR4::CheckerLPDDR4() diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index d952162a..953450c6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -35,9 +35,10 @@ #ifndef CHECKERLPDDR4_H #define CHECKERLPDDR4_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecLPDDR4.h" #include "../../configuration/Configuration.h" @@ -45,37 +46,37 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecLPDDR4 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; + std::vector> last4Activates; - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD; - sc_time tWRRD_R; - sc_time tRDPRE; - sc_time tRDAPRE; - sc_time tRDAACT; - sc_time tWRPRE; - sc_time tWRAPRE; - sc_time tWRAACT; - sc_time tACTPDEN; - sc_time tPRPDEN; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; - sc_time tREFPDEN; + sc_core::sc_time tBURST; + sc_core::sc_time tRDWR; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tRDPRE; + sc_core::sc_time tRDAPRE; + sc_core::sc_time tRDAACT; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRAPRE; + sc_core::sc_time tWRAACT; + sc_core::sc_time tACTPDEN; + sc_core::sc_time tPRPDEN; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; + sc_core::sc_time tREFPDEN; }; #endif // CHECKERLPDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index 52cbdf18..623cd6b0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerSTTMRAM.h" +using namespace sc_core; using namespace tlm; CheckerSTTMRAM::CheckerSTTMRAM() diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h index 08a3d20c..44d4c888 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h @@ -35,9 +35,10 @@ #ifndef CHECKERSTTMRAM_H #define CHECKERSTTMRAM_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecSTTMRAM.h" #include "../../configuration/Configuration.h" @@ -45,29 +46,29 @@ class CheckerSTTMRAM final : public CheckerIF { public: CheckerSTTMRAM(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecSTTMRAM *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; + std::vector> last4Activates; - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRRD; - sc_time tWRPRE; - sc_time tWRRD_R; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + sc_core::sc_time tBURST; + sc_core::sc_time tRDWR; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRRD; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; }; #endif // CHECKERSTTMRAM_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 1e29b6ba..bae5a9fa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerWideIO.h" +using namespace sc_core; using namespace tlm; CheckerWideIO::CheckerWideIO() diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 22f0e85f..0bfe15e1 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -35,9 +35,10 @@ #ifndef CHECKERWIDEIO_H #define CHECKERWIDEIO_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecWideIO.h" #include "../../configuration/Configuration.h" @@ -45,29 +46,29 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecWideIO *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // Four activate window - std::vector> last2Activates; + std::vector> last2Activates; - sc_time tBURST; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRPRE; - sc_time tWRRD; - sc_time tWRRD_R; - sc_time tRDPDEN; - sc_time tWRPDEN; - sc_time tWRAPDEN; + sc_core::sc_time tBURST; + sc_core::sc_time tRDWR; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRRD; + sc_core::sc_time tWRRD_R; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; }; #endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index cd82c2bd..eee56d31 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -32,8 +32,11 @@ * Author: Lukas Steiner */ +#include + #include "CheckerWideIO2.h" +using namespace sc_core; using namespace tlm; CheckerWideIO2::CheckerWideIO2() diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index d7d31998..dba97dfa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -35,9 +35,10 @@ #ifndef CHECKERWIDEIO2_H #define CHECKERWIDEIO2_H -#include "CheckerIF.h" #include #include + +#include "CheckerIF.h" #include "../../configuration/memspec/MemSpecWideIO2.h" #include "../../configuration/Configuration.h" @@ -45,30 +46,30 @@ class CheckerWideIO2 final : public CheckerIF { public: CheckerWideIO2(); - sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; + sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override; void insert(Command command, tlm::tlm_generic_payload *payload) override; private: const MemSpecWideIO2 *memSpec; - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastCommandOnBus; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_core::sc_time lastCommandOnBus; // Four activate window - std::vector> last4Activates; + std::vector> last4Activates; - sc_time tBURST; - sc_time tRDPRE; - sc_time tRDPDEN; - sc_time tRDWR; - sc_time tRDWR_R; - sc_time tWRPRE; - sc_time tWRPDEN; - sc_time tWRAPDEN; - sc_time tWRRD; - sc_time tWRRD_R; + sc_core::sc_time tBURST; + sc_core::sc_time tRDPRE; + sc_core::sc_time tRDPDEN; + sc_core::sc_time tRDWR; + sc_core::sc_time tRDWR_R; + sc_core::sc_time tWRPRE; + sc_core::sc_time tWRPDEN; + sc_core::sc_time tWRAPDEN; + sc_core::sc_time tWRRD; + sc_core::sc_time tWRRD_R; }; #endif // CHECKERWIDEIO2_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h index 4e58935b..006c4e5d 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h @@ -35,10 +35,6 @@ #ifndef CMDMUXIF_H #define CMDMUXIF_H -#include -#include -#include -#include #include "../Command.h" class CmdMuxIF diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index f5e150ee..6d1d215c 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -32,11 +32,11 @@ * Author: Lukas Steiner */ +#include #include "CmdMuxOldest.h" - #include "../../common/dramExtensions.h" -using namespace tlm; +using namespace sc_core; CmdMuxOldest::CmdMuxOldest() : memSpec(Configuration::getInstance().memSpec) {} diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index 3749ce4e..0a6eaeff 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -32,11 +32,11 @@ * Author: Lukas Steiner */ +#include #include "CmdMuxStrict.h" - #include "../../common/dramExtensions.h" -using namespace tlm; +using namespace sc_core; CmdMuxStrict::CmdMuxStrict() : memSpec(Configuration::getInstance().memSpec) {} diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp index 8fcbe479..f81c8d45 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp @@ -32,8 +32,10 @@ * Author: Lukas Steiner */ +#include "../Command.h" #include "PowerDownManagerDummy.h" +using namespace sc_core; using namespace tlm; CommandTuple::Type PowerDownManagerDummy::getNextCommand() diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h index e8408dea..d28aa011 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h @@ -48,7 +48,7 @@ public: CommandTuple::Type getNextCommand() override; void updateState(Command) override {} - sc_time start() override; + sc_core::sc_time start() override; }; #endif // POWERDOWNMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h index fd038495..5e2fa4ba 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h @@ -35,9 +35,7 @@ #ifndef POWERDOWNMANAGERIF_H #define POWERDOWNMANAGERIF_H -#include -#include -#include +#include #include "../Command.h" class PowerDownManagerIF @@ -51,7 +49,7 @@ public: virtual CommandTuple::Type getNextCommand() = 0; virtual void updateState(Command) = 0; - virtual sc_time start() = 0; + virtual sc_core::sc_time start() = 0; }; #endif // POWERDOWNMANAGERIF_H diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index 7fb1fac9..665cec9e 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -35,6 +35,7 @@ #include "PowerDownManagerStaggered.h" #include "../../common/utils.h" +using namespace sc_core; using namespace tlm; PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector &bankMachinesOnRank, diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h index f79004a9..a2e3cb3e 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h @@ -35,6 +35,7 @@ #ifndef POWERDOWNMANAGERSTAGGERED_H #define POWERDOWNMANAGERSTAGGERED_H +#include #include "PowerDownManagerIF.h" #include "../BankMachine.h" #include "../checker/CheckerIF.h" @@ -50,7 +51,7 @@ public: CommandTuple::Type getNextCommand() override; void updateState(Command) override; - sc_time start() override; + sc_core::sc_time start() override; private: enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle; @@ -58,7 +59,7 @@ private: std::vector &bankMachinesOnRank; CheckerIF *checker; - sc_time timeToSchedule = sc_max_time(); + sc_core::sc_time timeToSchedule = sc_core::sc_max_time(); Command nextCommand = Command::NOP; bool controllerIdle = true; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp index 11978b82..85ce5a45 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp @@ -37,6 +37,7 @@ #include "../../configuration/Configuration.h" #include "../../common/utils.h" +using namespace sc_core; using namespace tlm; RefreshManagerAllBank::RefreshManagerAllBank(std::vector &bankMachinesOnRank, diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h index a9605e87..9671f059 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h @@ -35,6 +35,10 @@ #ifndef REFRESHMANAGERALLBANK_H #define REFRESHMANAGERALLBANK_H +#include + +#include +#include #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" @@ -47,7 +51,7 @@ public: RefreshManagerAllBank(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); CommandTuple::Type getNextCommand() override; - sc_time start() override; + sc_core::sc_time start() override; void updateState(Command) override; private: @@ -56,8 +60,8 @@ private: std::vector &bankMachinesOnRank; PowerDownManagerIF *powerDownManager; tlm::tlm_generic_payload refreshPayload; - sc_time timeForNextTrigger = sc_max_time(); - sc_time timeToSchedule = sc_max_time(); + sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time(); + sc_core::sc_time timeToSchedule = sc_core::sc_max_time(); CheckerIF *checker; Command nextCommand = Command::NOP; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp index bc69f0c9..1ae997ce 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -34,6 +34,7 @@ #include "RefreshManagerDummy.h" +using namespace sc_core; using namespace tlm; CommandTuple::Type RefreshManagerDummy::getNextCommand() diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 5b585700..05d127e7 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -35,17 +35,14 @@ #ifndef REFRESHMANAGERDUMMY_H #define REFRESHMANAGERDUMMY_H -#include -#include -#include +#include #include "RefreshManagerIF.h" -#include "../Command.h" class RefreshManagerDummy final : public RefreshManagerIF { public: CommandTuple::Type getNextCommand() override; - sc_time start() override; + sc_core::sc_time start() override; void updateState(Command) override {} }; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index 65421fa6..06bf7b63 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -35,9 +35,9 @@ #ifndef REFRESHMANAGERIF_H #define REFRESHMANAGERIF_H -#include -#include -#include +#include + +#include #include "../Command.h" #include "../../configuration/Configuration.h" @@ -47,11 +47,12 @@ public: virtual ~RefreshManagerIF() = default; virtual CommandTuple::Type getNextCommand() = 0; - virtual sc_time start() = 0; + virtual sc_core::sc_time start() = 0; virtual void updateState(Command) = 0; protected: - static sc_time getTimeForFirstTrigger(const sc_time &refreshInterval, Rank rank, unsigned numberOfRanks) + static sc_core::sc_time getTimeForFirstTrigger(const sc_core::sc_time &refreshInterval, + Rank rank, unsigned numberOfRanks) { // Calculate bit-reversal rank ID unsigned rankID = rank.ID(); @@ -72,8 +73,8 @@ protected: } // Use bit-reversal order for refreshes on ranks - sc_time timeForFirstTrigger = refreshInterval - reverseRankID * (refreshInterval / numberOfRanks); - sc_time tCK = Configuration::getInstance().memSpec->tCK; + sc_core::sc_time timeForFirstTrigger = refreshInterval - reverseRankID * (refreshInterval / numberOfRanks); + sc_core::sc_time tCK = Configuration::getInstance().memSpec->tCK; timeForFirstTrigger = std::ceil(timeForFirstTrigger / tCK) * tCK; return timeForFirstTrigger; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp index 0c692f0d..5f335097 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp @@ -37,6 +37,7 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" +using namespace sc_core; using namespace tlm; RefreshManagerPerBank::RefreshManagerPerBank(std::vector &bankMachinesOnRank, diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h index a0b619ee..c02a12ba 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h @@ -35,13 +35,15 @@ #ifndef REFRESHMANAGERPERBANK_H #define REFRESHMANAGERPERBANK_H +#include +#include + +#include +#include #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" #include "../powerdown/PowerDownManagerIF.h" -#include -#include -#include class RefreshManagerPerBank final : public RefreshManagerIF { @@ -49,7 +51,7 @@ public: RefreshManagerPerBank(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); CommandTuple::Type getNextCommand() override; - sc_time start() override; + sc_core::sc_time start() override; void updateState(Command) override; private: @@ -57,8 +59,8 @@ private: const MemSpec *memSpec; PowerDownManagerIF *powerDownManager; std::vector refreshPayloads; - sc_time timeForNextTrigger = sc_max_time(); - sc_time timeToSchedule = sc_max_time(); + sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time(); + sc_core::sc_time timeToSchedule = sc_core::sc_max_time(); CheckerIF *checker; Command nextCommand = Command::NOP; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp index 54c27299..0def8fd8 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp @@ -37,6 +37,7 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" +using namespace sc_core; using namespace tlm; RefreshManagerSameBank::RefreshManagerSameBank(std::vector &bankMachinesOnRank, diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h index 7260242f..5d1921f3 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h @@ -35,13 +35,15 @@ #ifndef REFRESHMANAGERSAMEBANK_H #define REFRESHMANAGERSAMEBANK_H +#include +#include + +#include +#include #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" #include "../powerdown/PowerDownManagerIF.h" -#include -#include -#include class RefreshManagerSameBank final : public RefreshManagerIF { @@ -49,7 +51,7 @@ public: RefreshManagerSameBank(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); CommandTuple::Type getNextCommand() override; - sc_time start() override; + sc_core::sc_time start() override; void updateState(Command) override; private: @@ -57,8 +59,8 @@ private: const MemSpec *memSpec; PowerDownManagerIF *powerDownManager; std::vector refreshPayloads; - sc_time timeForNextTrigger = sc_max_time(); - sc_time timeToSchedule = sc_max_time(); + sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time(); + sc_core::sc_time timeToSchedule = sc_core::sc_max_time(); CheckerIF *checker; Command nextCommand = Command::NOP; diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp index dffedaba..825efd13 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp +++ b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp @@ -34,6 +34,7 @@ #include "RespQueueFifo.h" +using namespace sc_core; using namespace tlm; void RespQueueFifo::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h index 82846be9..7c611d45 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueFifo.h @@ -35,21 +35,22 @@ #ifndef RESPQUEUEFIFO_H #define RESPQUEUEFIFO_H -#include -#include -#include "RespQueueIF.h" #include #include +#include +#include +#include "RespQueueIF.h" + class RespQueueFifo final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload *, sc_time) override; + void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override; tlm::tlm_generic_payload *nextPayload() override; - sc_time getTriggerTime() const override; + sc_core::sc_time getTriggerTime() const override; private: - std::queue> buffer; + std::queue> buffer; }; #endif // RESPQUEUEFIFO_H diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueIF.h b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h index 53cb3c04..9f566a78 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueIF.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueIF.h @@ -35,15 +35,15 @@ #ifndef RESPQUEUEIF_H #define RESPQUEUEIF_H -#include -#include +#include +#include class RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0; + virtual void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) = 0; virtual tlm::tlm_generic_payload *nextPayload() = 0; - virtual sc_time getTriggerTime() const = 0; + virtual sc_core::sc_time getTriggerTime() const = 0; virtual ~RespQueueIF() = default; }; diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp index c41c7d45..a1214ac6 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp @@ -35,6 +35,7 @@ #include "RespQueueReorder.h" #include "../../common/dramExtensions.h" +using namespace sc_core; using namespace tlm; void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd) diff --git a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h index 26ffa730..f236affe 100644 --- a/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h +++ b/DRAMSys/library/src/controller/respqueue/RespQueueReorder.h @@ -35,21 +35,22 @@ #ifndef RESPQUEUEREORDER_H #define RESPQUEUEREORDER_H -#include -#include -#include "RespQueueIF.h" #include +#include +#include +#include "RespQueueIF.h" + class RespQueueReorder final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload *, sc_time) override; + void insertPayload(tlm::tlm_generic_payload *, sc_core::sc_time) override; tlm::tlm_generic_payload *nextPayload() override; - sc_time getTriggerTime() const override; + sc_core::sc_time getTriggerTime() const override; private: uint64_t nextPayloadID = 1; - std::map> buffer; + std::map> buffer; }; #endif // RESPQUEUEREORDER_H diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp index f1c4f5f0..7acc2482 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp @@ -35,6 +35,8 @@ #include "BufferCounterBankwise.h" #include "../../common/dramExtensions.h" +using namespace tlm; + BufferCounterBankwise::BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks) : requestBufferSize(requestBufferSize) { @@ -46,13 +48,13 @@ bool BufferCounterBankwise::hasBufferSpace() const return (numRequestsOnBank[lastBankID] < requestBufferSize); } -void BufferCounterBankwise::storeRequest(tlm::tlm_generic_payload *payload) +void BufferCounterBankwise::storeRequest(tlm_generic_payload *payload) { lastBankID = DramExtension::getBank(payload).ID(); numRequestsOnBank[lastBankID]++; } -void BufferCounterBankwise::removeRequest(tlm::tlm_generic_payload *payload) +void BufferCounterBankwise::removeRequest(tlm_generic_payload *payload) { numRequestsOnBank[DramExtension::getBank(payload).ID()]--; } diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h index 079bb4c8..02725b81 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h @@ -37,6 +37,7 @@ #include +#include #include "BufferCounterIF.h" class BufferCounterBankwise final : public BufferCounterIF diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterIF.h b/DRAMSys/library/src/controller/scheduler/BufferCounterIF.h index 5deab172..38ca4340 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterIF.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterIF.h @@ -35,7 +35,9 @@ #ifndef BUFFERCOUNTERIF_H #define BUFFERCOUNTERIF_H -#include +#include + +#include class BufferCounterIF { diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.cpp b/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.cpp index a43b1241..3a036e0a 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.cpp +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.cpp @@ -34,6 +34,8 @@ #include "BufferCounterReadWrite.h" +using namespace tlm; + BufferCounterReadWrite::BufferCounterReadWrite(unsigned requestBufferSize) : requestBufferSize(requestBufferSize) { @@ -45,7 +47,7 @@ bool BufferCounterReadWrite::hasBufferSpace() const return (numReadWriteRequests[0] < requestBufferSize && numReadWriteRequests[1] < requestBufferSize); } -void BufferCounterReadWrite::storeRequest(tlm::tlm_generic_payload *payload) +void BufferCounterReadWrite::storeRequest(tlm_generic_payload *payload) { if (payload->is_read()) numReadWriteRequests[0]++; @@ -53,7 +55,7 @@ void BufferCounterReadWrite::storeRequest(tlm::tlm_generic_payload *payload) numReadWriteRequests[1]++; } -void BufferCounterReadWrite::removeRequest(tlm::tlm_generic_payload *payload) +void BufferCounterReadWrite::removeRequest(tlm_generic_payload *payload) { if (payload->is_read()) numReadWriteRequests[0]--; diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h b/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h index f12ebd7d..f0d28a90 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h @@ -35,6 +35,9 @@ #ifndef BUFFERCOUNTERREADWRITE_H #define BUFFERCOUNTERREADWRITE_H +#include + +#include #include "BufferCounterIF.h" class BufferCounterReadWrite final : public BufferCounterIF diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterShared.cpp b/DRAMSys/library/src/controller/scheduler/BufferCounterShared.cpp index 459a0078..a4b80ef1 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterShared.cpp +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterShared.cpp @@ -34,6 +34,8 @@ #include "BufferCounterShared.h" +using namespace tlm; + BufferCounterShared::BufferCounterShared(unsigned requestBufferSize) : requestBufferSize(requestBufferSize) { @@ -45,12 +47,12 @@ bool BufferCounterShared::hasBufferSpace() const return (numRequests[0] < requestBufferSize); } -void BufferCounterShared::storeRequest(tlm::tlm_generic_payload *) +void BufferCounterShared::storeRequest(tlm_generic_payload *) { numRequests[0]++; } -void BufferCounterShared::removeRequest(tlm::tlm_generic_payload *) +void BufferCounterShared::removeRequest(tlm_generic_payload *) { numRequests[0]--; } diff --git a/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h b/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h index dbfb0c7a..7e530579 100644 --- a/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h +++ b/DRAMSys/library/src/controller/scheduler/BufferCounterShared.h @@ -35,6 +35,9 @@ #ifndef BUFFERCOUNTERSHARED_H #define BUFFERCOUNTERSHARED_H +#include + +#include #include "BufferCounterIF.h" class BufferCounterShared final : public BufferCounterIF diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index 6cdeac00..b6c6f645 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -35,10 +35,10 @@ #ifndef SCHEDULERFIFO_H #define SCHEDULERFIFO_H -#include #include #include +#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" #include "../BankMachine.h" diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index c8a182c8..0f5bd219 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -35,10 +35,10 @@ #ifndef SCHEDULERFRFCFS_H #define SCHEDULERFRFCFS_H -#include #include #include +#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" #include "../BankMachine.h" diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h index 11cd2dae..7090b9cb 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h @@ -35,10 +35,10 @@ #ifndef SCHEDULERFRFCFSGRP_H #define SCHEDULERFRFCFSGRP_H -#include #include #include +#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" #include "../BankMachine.h" diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index fbde3fdb..a440f8bb 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -35,10 +35,10 @@ #ifndef SCHEDULERIF_H #define SCHEDULERIF_H -#include +#include +#include #include "../../common/dramExtensions.h" -#include "../../common/DebugManager.h" class BankMachine; diff --git a/DRAMSys/library/src/error/eccbaseclass.cpp b/DRAMSys/library/src/error/eccbaseclass.cpp index 1fae420f..3f266077 100644 --- a/DRAMSys/library/src/error/eccbaseclass.cpp +++ b/DRAMSys/library/src/error/eccbaseclass.cpp @@ -36,6 +36,7 @@ #include "eccbaseclass.h" +using namespace sc_core; using namespace tlm; tlm::tlm_sync_enum ECCBaseClass::nb_transport_fw( int id, diff --git a/DRAMSys/library/src/error/eccbaseclass.h b/DRAMSys/library/src/error/eccbaseclass.h index a231bee5..9a9d52bb 100644 --- a/DRAMSys/library/src/error/eccbaseclass.h +++ b/DRAMSys/library/src/error/eccbaseclass.h @@ -37,8 +37,8 @@ #ifndef ECCBASECLASS_H #define ECCBASECLASS_H -#include -#include +#include +#include #include #include @@ -46,7 +46,7 @@ #include "../common/DebugManager.h" -class ECCBaseClass : sc_module +class ECCBaseClass : sc_core::sc_module { public: struct DataStruct { @@ -68,16 +68,16 @@ protected: // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn // Result should be written in pDataOut, which has a size of nDataOut. // pDataOut is already allocated with a size given by function AllocationEncode - virtual void Encode(const unsigned char *pDataIn, const unsigned nDataIn, - unsigned char *pDataOut, const unsigned nDataOut) = 0; + virtual void Encode(const unsigned char *pDataIn, unsigned nDataIn, + unsigned char *pDataOut, unsigned nDataOut) = 0; // Function prototype for decoding data. // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn // Result should be written in pDataOut, which has a size of nDataOut. // pDataOut is already allocated with a size given by function AllocationDecode - virtual void Decode(const unsigned char *pDataIn, const unsigned nDataIn, - unsigned char *pDataOut, const unsigned nDataOut) = 0; + virtual void Decode(const unsigned char *pDataIn, unsigned nDataIn, + unsigned char *pDataOut, unsigned nDataOut) = 0; public: tlm_utils::multi_passthrough_target_socket t_socket; @@ -92,11 +92,11 @@ public: } // Forward interface tlm::tlm_sync_enum nb_transport_fw( int id, tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay ); + tlm::tlm_phase &phase, sc_core::sc_time &delay ); // Backward interface tlm::tlm_sync_enum nb_transport_bw( int id, tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay ); + tlm::tlm_phase &phase, sc_core::sc_time &delay ); }; #endif // ECCBASECLASS_H diff --git a/DRAMSys/library/src/error/ecchamming.cpp b/DRAMSys/library/src/error/ecchamming.cpp index 72d8063c..65255532 100644 --- a/DRAMSys/library/src/error/ecchamming.cpp +++ b/DRAMSys/library/src/error/ecchamming.cpp @@ -140,10 +140,10 @@ void ECCHamming::Decode(const unsigned char *pDataIn, const unsigned nDataIn, if (c == 0) { // Only Parity Bit broken - continue - cout << "Parity Bit error" << endl; + std::cout << "Parity Bit error" << std::endl; } else { // Data or Hamming Code Bit broken - cout << "Single Error Detected" << endl; + std::cout << "Single Error Detected" << std::endl; } } else { // No Parity Error @@ -152,7 +152,7 @@ void ECCHamming::Decode(const unsigned char *pDataIn, const unsigned nDataIn, // No error at all - continue } else { // Double error detected - cout << "Double Error Detected (Block " << i << ")." << endl; + std::cout << "Double Error Detected (Block " << i << ")." << std::endl; } } diff --git a/DRAMSys/library/src/error/ecchamming.h b/DRAMSys/library/src/error/ecchamming.h index 0a626416..14986cd7 100644 --- a/DRAMSys/library/src/error/ecchamming.h +++ b/DRAMSys/library/src/error/ecchamming.h @@ -63,16 +63,16 @@ protected: // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn // Result should be written in pDataOut, which has a size of nDataOut. // pDataOut is already allocated with a size given by function AllocationEncode - virtual void Encode(const unsigned char *pDataIn, const unsigned nDataIn, - unsigned char *pDataOut, const unsigned nDataOut); + virtual void Encode(const unsigned char *pDataIn, unsigned nDataIn, + unsigned char *pDataOut, unsigned nDataOut); // Function prototype for decoding data. // Data pointer is provided in pDataIn, length in Bytes provided in nDataIn // Result should be written in pDataOut, which has a size of nDataOut. // pDataOut is already allocated with a size given by function AllocationDecode - virtual void Decode(const unsigned char *pDataIn, const unsigned nDataIn, - unsigned char *pDataOut, const unsigned nDataOut); + virtual void Decode(const unsigned char *pDataIn, unsigned nDataIn, + unsigned char *pDataOut, unsigned nDataOut); public: ECCHamming(::sc_core::sc_module_name name) : ECCBaseClass(name) diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index 0195f194..b44b463d 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -43,6 +43,10 @@ #include #include #include +#include +#include + +using namespace sc_core; void errorModel::init() { @@ -114,13 +118,13 @@ void errorModel::init() markBitFlips(); } -errorModel::errorModel(sc_module_name name, libDRAMPower *dp) : sc_module(name) +errorModel::errorModel(const sc_module_name &name, libDRAMPower *dp) : sc_module(name) { this->DRAMPower = dp; init(); } -errorModel::errorModel(sc_module_name name) : sc_module(name) +errorModel::errorModel(const sc_module_name &name) : sc_module(name) { init(); } diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index 99fdd034..b5aadf16 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -37,18 +37,18 @@ #define ERRORMODEL_H #include -#include -#include + +#include #include "../configuration/Configuration.h" #include "../simulation/AddressDecoder.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -class errorModel : public sc_module +class errorModel : public sc_core::sc_module { public: - errorModel(sc_module_name, libDRAMPower *); - errorModel(sc_module_name); - ~errorModel(); + errorModel(const sc_core::sc_module_name &, libDRAMPower *); + explicit errorModel(const sc_core::sc_module_name &); + ~errorModel() override; // Access Methods: void store(tlm::tlm_generic_payload &trans); @@ -56,10 +56,10 @@ public: void refresh(unsigned int row); void activate(unsigned int row); void setTemperature(double t); - double getTemperature(void); + double getTemperature(); private: - void init(void); + void init(); bool powerAnalysis; libDRAMPower *DRAMPower; bool thermalSim; @@ -79,7 +79,7 @@ private: void parseInputData(); void prepareWeakCells(); void markBitFlips(); - unsigned int getNumberOfFlips(double temp, sc_time time); + unsigned int getNumberOfFlips(double temp, sc_core::sc_time time); void setContext(DecodedAddress addr); unsigned int getBit(DecodedAddress key, unsigned int byte, unsigned int bitInByte); @@ -94,12 +94,12 @@ private: // temperature time number of errors // | | | - std::map > errorMap; + std::map > errorMap; unsigned int maxNumberOfWeakCells; unsigned int maxNumberOfDepWeakCells; double maxTemperature; - sc_time maxTime; + sc_core::sc_time maxTime; // Storage of weak cells: struct weakCell { @@ -131,7 +131,7 @@ private: std::map dataMap; // An array to save when the last ACT/REF to a row happened: - sc_time *lastRowAccess; + sc_core::sc_time *lastRowAccess; // Context Variables (will be written by the first dram access) int myChannel; diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index 1f2cf405..864efebf 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -36,6 +36,8 @@ */ #include +#include +#include #include #include "AddressDecoder.h" diff --git a/DRAMSys/library/src/simulation/AddressDecoder.h b/DRAMSys/library/src/simulation/AddressDecoder.h index 4065a96c..4a971469 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.h +++ b/DRAMSys/library/src/simulation/AddressDecoder.h @@ -38,11 +38,8 @@ #ifndef ADDRESSDECODER_H #define ADDRESSDECODER_H -#include -#include -#include -#include #include +#include #include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index f8851bbf..9e973b37 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -40,6 +40,7 @@ #include "AddressDecoder.h" #include "../configuration/Configuration.h" +using namespace sc_core; using namespace tlm; Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping) : diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 3ff5370d..99f07323 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -39,12 +39,13 @@ #ifndef ARBITER_H #define ARBITER_H -#include -#include #include #include #include #include + +#include +#include #include #include #include @@ -54,7 +55,7 @@ DECLARE_EXTENDED_PHASE(REQ_ARBITRATION); DECLARE_EXTENDED_PHASE(RESP_ARBITRATION); -class Arbiter : public sc_module +class Arbiter : public sc_core::sc_module { public: tlm_utils::multi_passthrough_initiator_socket iSocket; @@ -63,7 +64,7 @@ public: ~Arbiter() override; protected: - Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping); + Arbiter(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(Arbiter); void end_of_elaboration() override; @@ -82,14 +83,14 @@ protected: std::vector nextChannelPayloadIDToAppend; tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &fwDelay); + tlm::tlm_phase &phase, sc_core::sc_time &fwDelay); tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &bwDelay); + tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans); - sc_time tCK; - sc_time arbitrationDelayFw; - sc_time arbitrationDelayBw; + sc_core::sc_time tCK; + sc_core::sc_time arbitrationDelayFw; + sc_core::sc_time arbitrationDelayBw; unsigned bytesPerBeat; }; @@ -97,7 +98,7 @@ protected: class ArbiterSimple final : public Arbiter { public: - ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping); + ArbiterSimple(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(ArbiterSimple); private: @@ -110,7 +111,7 @@ private: class ArbiterFifo final : public Arbiter { public: - ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping); + ArbiterFifo(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(ArbiterFifo); private: @@ -123,14 +124,14 @@ private: std::vector outstandingEndReq; std::vector> pendingResponses; - std::vector lastEndReq; - std::vector lastEndResp; + std::vector lastEndReq; + std::vector lastEndResp; }; class ArbiterReorder final : public Arbiter { public: - ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping); + ArbiterReorder(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(ArbiterReorder); private: @@ -151,8 +152,8 @@ private: std::vector outstandingEndReq; std::vector> pendingResponses; - std::vector lastEndReq; - std::vector lastEndResp; + std::vector lastEndReq; + std::vector lastEndResp; std::vector nextThreadPayloadIDToReturn; }; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index e93c5061..06f6415d 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -39,7 +39,6 @@ #include #include -#include #include #include @@ -62,13 +61,13 @@ #include "dram/DramSTTMRAM.h" #include "../controller/Controller.h" -DRAMSys::DRAMSys(const sc_module_name &name, +DRAMSys::DRAMSys(const sc_core::sc_module_name &name, const std::string &simulationToRun, const std::string &pathToResources) : DRAMSys(name, simulationToRun, pathToResources, true) {} -DRAMSys::DRAMSys(const sc_module_name &name, +DRAMSys::DRAMSys(const sc_core::sc_module_name &name, const std::string &simulationToRun, const std::string &pathToResources, bool initAndBind) @@ -201,7 +200,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create controllers and DRAMs MemSpec::MemoryType memoryType = config.memSpec->memoryType; - for (size_t i = 0; i < config.memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -262,7 +261,7 @@ void DRAMSys::bindSockets() if (config.checkTLM2Protocol) { - for (size_t i = 0; i < config.memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -271,7 +270,7 @@ void DRAMSys::bindSockets() } else { - for (size_t i = 0; i < config.memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index fd7883da..cb6063c9 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -41,8 +41,8 @@ #define DRAMSYS_H #include -#include +#include #include "dram/Dram.h" #include "Arbiter.h" #include "ReorderBuffer.h" @@ -52,7 +52,7 @@ #include "../error/eccbaseclass.h" #include "../controller/ControllerIF.h" -class DRAMSys : public sc_module +class DRAMSys : public sc_core::sc_module { public: tlm_utils::multi_passthrough_target_socket tSocket; @@ -61,14 +61,14 @@ public: playersTlmCheckers; SC_HAS_PROCESS(DRAMSys); - DRAMSys(const sc_module_name &name, + DRAMSys(const sc_core::sc_module_name &name, const std::string &simulationToRun, const std::string &pathToResources); ~DRAMSys() override; protected: - DRAMSys(const sc_module_name &name, + DRAMSys(const sc_core::sc_module_name &name, const std::string &simulationToRun, const std::string &pathToResources, bool initAndBind); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 43fea7a5..b8f9a8c8 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -51,6 +51,8 @@ #include "../simulation/TemperatureController.h" #include "../error/ecchamming.h" +using namespace sc_core; + DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name, const std::string &simulationToRun, const std::string &pathToResources) @@ -93,7 +95,7 @@ DRAMSysRecordable::~DRAMSysRecordable() void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName) { // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb"; @@ -144,7 +146,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create controllers and DRAMs MemSpec::MemoryType memoryType = config.memSpec->memoryType; - for (size_t i = 0; i < config.memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -205,7 +207,7 @@ void DRAMSysRecordable::bindSockets() if (config.checkTLM2Protocol) { - for (size_t i = 0; i < config.memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -214,7 +216,7 @@ void DRAMSysRecordable::bindSockets() } else { - for (size_t i = 0; i < config.memSpec->numberOfChannels; i++) + for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.h b/DRAMSys/library/src/simulation/DRAMSysRecordable.h index 98fcd31f..876b3d6f 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.h +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.h @@ -42,7 +42,7 @@ class DRAMSysRecordable : public DRAMSys { public: - DRAMSysRecordable(const sc_module_name &name, + DRAMSysRecordable(const sc_core::sc_module_name &name, const std::string &simulationToRun, const std::string &pathToResources); diff --git a/DRAMSys/library/src/simulation/ReorderBuffer.h b/DRAMSys/library/src/simulation/ReorderBuffer.h index b1f4718d..28e86492 100644 --- a/DRAMSys/library/src/simulation/ReorderBuffer.h +++ b/DRAMSys/library/src/simulation/ReorderBuffer.h @@ -40,13 +40,14 @@ #include #include -#include -#include + +#include +#include #include #include #include -struct ReorderBuffer : public sc_module +struct ReorderBuffer : public sc_core::sc_module { public: tlm_utils::simple_initiator_socket iSocket; @@ -70,7 +71,7 @@ private: // Initiated by dram side tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, - sc_time &bwDelay) + sc_core::sc_time &bwDelay) { payloadEventQueue.notify(payload, phase, bwDelay); return tlm::TLM_ACCEPTED; @@ -78,7 +79,7 @@ private: // Initiated by initator side (players) tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, - sc_time &fwDelay) + sc_core::sc_time &fwDelay) { if (phase == tlm::BEGIN_REQ) { payload.acquire(); @@ -95,7 +96,7 @@ private: //Phases initiated by initiator side if (phase == tlm::BEGIN_REQ) { pendingRequestsInOrder.push_back(&payload); - sendToTarget(payload, phase, SC_ZERO_TIME ); + sendToTarget(payload, phase, sc_core::SC_ZERO_TIME); } else if (phase == tlm::END_RESP) { @@ -107,9 +108,9 @@ private: //Phases initiated by dram side else if (phase == tlm::END_REQ) { - sendToInitiator(payload, phase, SC_ZERO_TIME); + sendToInitiator(payload, phase, sc_core::SC_ZERO_TIME); } else if (phase == tlm::BEGIN_RESP) { - sendToTarget(payload, tlm::END_RESP, SC_ZERO_TIME); + sendToTarget(payload, tlm::END_RESP, sc_core::SC_ZERO_TIME); receivedResponses.emplace(&payload); sendNextResponse(); } @@ -121,16 +122,14 @@ private: } } - void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, - const sc_time &delay) + void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_core::sc_time &delay) { tlm::tlm_phase TPhase = phase; - sc_time TDelay = delay; + sc_core::sc_time TDelay = delay; iSocket->nb_transport_fw(payload, TPhase, TDelay); } - void sendToInitiator(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, - const sc_time &delay) + void sendToInitiator(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, const sc_core::sc_time &delay) { @@ -139,7 +138,7 @@ private: && receivedResponses.count(&payload))); tlm::tlm_phase TPhase = phase; - sc_time TDelay = delay; + sc_core::sc_time TDelay = delay; tSocket->nb_transport_bw(payload, TPhase, TDelay); } @@ -151,7 +150,7 @@ private: && receivedResponses.count(pendingRequestsInOrder.front())) { tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; - sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, SC_ZERO_TIME); + sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, sc_core::SC_ZERO_TIME); } // else if(!responseIsPendingInInitator && receivedResponses.size()>0 && !receivedResponses.count(pendingRequestsInOrder.front())>0) // { diff --git a/DRAMSys/library/src/simulation/TemperatureController.cpp b/DRAMSys/library/src/simulation/TemperatureController.cpp index a350af2c..3aa92634 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.cpp +++ b/DRAMSys/library/src/simulation/TemperatureController.cpp @@ -39,6 +39,8 @@ #include "TemperatureController.h" #include "../configuration/Configuration.h" +using namespace sc_core; + double TemperatureController::temperatureConvert(double tKelvin) { if (temperatureScale == "Celsius") { @@ -55,7 +57,7 @@ double TemperatureController::getTemperature(int deviceId, float currentPower) PRINTDEBUGMESSAGE(name(), "Temperature requested by device " + std::to_string( deviceId) + " current power is " + std::to_string(currentPower)); - if (dynamicTempSimEnabled == true) { + if (dynamicTempSimEnabled) { currentPowerValues.at(deviceId) = currentPower; checkPowerThreshold(deviceId); @@ -135,7 +137,7 @@ double TemperatureController::adjustThermalSimPeriod() // again in steps of 'n/2' until it achieves the desired value given by // configuration or the described in 1.1 occurs. - if (decreaseSimPeriod == true) { + if (decreaseSimPeriod) { period = period / periodAdjustFactor; cyclesSinceLastPeriodAdjust = 0; decreaseSimPeriod = false; diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index a6408245..ac5e96e4 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -37,11 +37,9 @@ #ifndef TEMPERATURECONTROLLER_H #define TEMPERATURECONTROLLER_H -#include -#include #include -#include +#include #include "../common/DebugManager.h" #include "../common/utils.h" #include "../configuration/Configuration.h" @@ -50,7 +48,7 @@ #include "IceWrapper.h" #endif -SC_MODULE(TemperatureController) +class TemperatureController : sc_core::sc_module { public: static inline TemperatureController &getInstance() { @@ -58,7 +56,9 @@ public: return temperaturectrl; } - SC_CTOR(TemperatureController) { + SC_HAS_PROCESS(TemperatureController); + explicit TemperatureController(const sc_core::sc_module_name &name) : sc_core::sc_module(name) + { temperatureScale = Configuration::getInstance().temperatureSim.temperatureScale; dynamicTempSimEnabled = Configuration::getInstance().thermalSimulation; @@ -66,7 +66,7 @@ public: staticTemperature = Configuration::getInstance().temperatureSim.staticTemperatureDefaultValue; - if (dynamicTempSimEnabled == true) { + if (dynamicTempSimEnabled) { #ifdef THERMALSIM // Connect to the server std::string ip = Configuration::getInstance().temperatureSim.iceServerIp; @@ -75,7 +75,7 @@ public: PRINTDEBUGMESSAGE(name(), "Dynamic temperature simulation. Server @ " + ip + ":" + std::to_string(port)); #else - SC_REPORT_FATAL(name(), + SC_REPORT_FATAL(sc_module::name(), "DRAMSys was build without support to dynamic temperature simulation. Check the README file for further details."); #endif // Initial power dissipation values (got from config) @@ -107,7 +107,7 @@ public: SC_THREAD(temperatureThread); } else { - PRINTDEBUGMESSAGE(name(), "Static temperature simulation. Temperature set to " + + PRINTDEBUGMESSAGE(sc_module::name(), "Static temperature simulation. Temperature set to " + std::to_string(staticTemperature)); } } @@ -134,7 +134,7 @@ private: double targetPeriod; double period; - enum sc_time_unit t_unit; + enum sc_core::sc_time_unit t_unit; void temperatureThread(); void updateTemperatures(); double adjustThermalSimPeriod(); diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 73e13f2a..223e2754 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -37,30 +37,28 @@ * Felipe S. Prado */ -#include "Dram.h" - #ifdef _WIN32 #include #else #include #endif -#include -#include -#include + #include #include #include #include #include #include +#include + +#include "Dram.h" #include "../../common/DebugManager.h" #include "../../common/dramExtensions.h" -#include "../../configuration/Configuration.h" #include "../../common/utils.h" -#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../common/third_party/DRAMPower/src/MemCommand.h" #include "../../controller/Command.h" +using namespace sc_core; using namespace tlm; using namespace DRAMPower; diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 18e9162c..39613044 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -40,21 +40,21 @@ #ifndef DRAM_H #define DRAM_H -#include -#include +#include +#include #include #include "../../configuration/Configuration.h" #include "../../configuration/memspec/MemSpec.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -class Dram : public sc_module +class Dram : public sc_core::sc_module { private: unsigned int bytesPerBurst = Configuration::getInstance().memSpec->bytesPerBurst; bool powerReported = false; protected: - explicit Dram(const sc_module_name &name); + explicit Dram(const sc_core::sc_module_name &name); SC_HAS_PROCESS(Dram); const MemSpec *memSpec = Configuration::getInstance().memSpec; @@ -67,7 +67,7 @@ protected: libDRAMPower *DRAMPower; virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay); + tlm::tlm_phase &phase, sc_core::sc_time &delay); virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans); diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index de363dc9..4b1cf98d 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -34,12 +34,11 @@ */ #include "DramDDR3.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecDDR3.h" +using namespace sc_core; using namespace DRAMPower; DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name) diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.h b/DRAMSys/library/src/simulation/dram/DramDDR3.h index 2f75c328..e5111e3c 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.h @@ -36,13 +36,13 @@ #ifndef DRAMDDR3_H #define DRAMDDR3_H -#include +#include #include "Dram.h" class DramDDR3 : public Dram { public: - explicit DramDDR3(const sc_module_name&); + explicit DramDDR3(const sc_core::sc_module_name&); SC_HAS_PROCESS(DramDDR3); }; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 30c132f8..58b0970e 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -34,12 +34,11 @@ */ #include "DramDDR4.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecDDR4.h" +using namespace sc_core; using namespace DRAMPower; DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name) diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.h b/DRAMSys/library/src/simulation/dram/DramDDR4.h index 5c10f57a..d321425e 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.h @@ -36,13 +36,13 @@ #ifndef DRAMDDR4_H #define DRAMDDR4_H -#include +#include #include "Dram.h" class DramDDR4 : public Dram { public: - explicit DramDDR4(const sc_module_name &name); + explicit DramDDR4(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramDDR4); }; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramDDR5.cpp index f4d1f2be..aafe2520 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR5.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR5.cpp @@ -34,12 +34,11 @@ */ #include "DramDDR5.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecDDR5.h" +using namespace sc_core; using namespace DRAMPower; DramDDR5::DramDDR5(const sc_module_name &name) : Dram(name) diff --git a/DRAMSys/library/src/simulation/dram/DramDDR5.h b/DRAMSys/library/src/simulation/dram/DramDDR5.h index 4d7042ae..44858b89 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR5.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR5.h @@ -36,13 +36,13 @@ #ifndef DRAMDDR5_H #define DRAMDDR5_H -#include +#include #include "Dram.h" class DramDDR5 : public Dram { public: - explicit DramDDR5(const sc_module_name &name); + explicit DramDDR5(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramDDR5); }; diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp index 40f0c309..931cf3a2 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp @@ -34,12 +34,12 @@ */ #include "DramGDDR5.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecGDDR5.h" +using namespace sc_core; + DramGDDR5::DramGDDR5(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.h b/DRAMSys/library/src/simulation/dram/DramGDDR5.h index 979811de..836ebee5 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5.h +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.h @@ -36,13 +36,13 @@ #ifndef DRAMGDDR5_H #define DRAMGDDR5_H -#include +#include #include "Dram.h" class DramGDDR5 : public Dram { public: - explicit DramGDDR5(const sc_module_name &name); + explicit DramGDDR5(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramGDDR5); }; diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp index cabd8cfe..90d1d46a 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp @@ -34,12 +34,12 @@ */ #include "DramGDDR5X.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecGDDR5X.h" +using namespace sc_core; + DramGDDR5X::DramGDDR5X(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h index a8432bf6..15604def 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h @@ -36,13 +36,13 @@ #ifndef DRAMGDDR5X_H #define DRAMGDDR5X_H -#include +#include #include "Dram.h" class DramGDDR5X : public Dram { public: - explicit DramGDDR5X(const sc_module_name &name); + explicit DramGDDR5X(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramGDDR5X); }; diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp index 068bbf72..c4c01775 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp @@ -34,12 +34,12 @@ */ #include "DramGDDR6.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecGDDR6.h" +using namespace sc_core; + DramGDDR6::DramGDDR6(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.h b/DRAMSys/library/src/simulation/dram/DramGDDR6.h index 088b7acd..ccecd189 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR6.h +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.h @@ -36,13 +36,13 @@ #ifndef DRAMGDDR6_H #define DRAMGDDR6_H -#include +#include #include "Dram.h" class DramGDDR6 : public Dram { public: - explicit DramGDDR6(const sc_module_name &name); + explicit DramGDDR6(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramGDDR6); }; diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp index ef01f51d..144ee6d1 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp @@ -34,12 +34,12 @@ */ #include "DramHBM2.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecHBM2.h" +using namespace sc_core; + DramHBM2::DramHBM2(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.h b/DRAMSys/library/src/simulation/dram/DramHBM2.h index 05315d9a..b1fa263c 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.h +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.h @@ -36,13 +36,13 @@ #ifndef DRAMHBM2_H #define DRAMHBM2_H -#include +#include #include "Dram.h" class DramHBM2 : public Dram { public: - explicit DramHBM2(const sc_module_name &name); + explicit DramHBM2(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramHBM2); }; diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp index 716242f3..d70d48fb 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp @@ -34,12 +34,12 @@ */ #include "DramLPDDR4.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecLPDDR4.h" +using namespace sc_core; + DramLPDDR4::DramLPDDR4(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h index 611ea1aa..c78beb4e 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h @@ -36,13 +36,13 @@ #ifndef DRAMLPDDR4_H #define DRAMLPDDR4_H -#include +#include #include "Dram.h" class DramLPDDR4 : public Dram { public: - explicit DramLPDDR4(const sc_module_name &name); + explicit DramLPDDR4(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramLPDDR4); }; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index a533cfeb..283346aa 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -36,8 +36,6 @@ #include "DramRecordable.h" #include -#include -#include #include "../../common/TlmRecorder.h" #include "../../common/utils.h" #include "DramDDR3.h" @@ -52,6 +50,7 @@ #include "DramGDDR6.h" #include "DramSTTMRAM.h" +using namespace sc_core; using namespace tlm; template @@ -124,7 +123,7 @@ void DramRecordable::powerWindow() while (true) { // At the very beginning (zero clock cycles) the energy is 0, so we wait first - wait(powerWindowSize); + sc_module::wait(powerWindowSize); clkCycles = std::lround(sc_time_stamp() / this->memSpec->tCK); diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h index 66375203..4e456536 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -36,8 +36,8 @@ #ifndef DRAMRECORDABLE_H #define DRAMRECORDABLE_H -#include -#include +#include +#include #include "../../common/TlmRecorder.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" @@ -46,20 +46,20 @@ template class DramRecordable final : public BaseDram { public: - DramRecordable(const sc_module_name &name, TlmRecorder *); + DramRecordable(const sc_core::sc_module_name &name, TlmRecorder *); SC_HAS_PROCESS(DramRecordable); void reportPower() override; private: tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_phase &phase, sc_core::sc_time &delay) override; - void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay); TlmRecorder *tlmRecorder; - sc_time powerWindowSize = Configuration::getInstance().memSpec->tCK * + sc_core::sc_time powerWindowSize = Configuration::getInstance().memSpec->tCK * Configuration::getInstance().windowSize; // When working with floats, we have to decide ourselves what is an diff --git a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp index 5ecffd8e..f3e380ea 100644 --- a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp +++ b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp @@ -34,12 +34,11 @@ */ #include "DramSTTMRAM.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecSTTMRAM.h" +using namespace sc_core; using namespace DRAMPower; DramSTTMRAM::DramSTTMRAM(const sc_module_name &name) : Dram(name) diff --git a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h index 3df7ac11..dfc522ee 100644 --- a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h +++ b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h @@ -36,13 +36,13 @@ #ifndef DRAMSTTMRAM_H #define DRAMSTTMRAM_H -#include +#include #include "Dram.h" class DramSTTMRAM : public Dram { public: - explicit DramSTTMRAM(const sc_module_name &name); + explicit DramSTTMRAM(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramSTTMRAM); }; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 7b978695..1d1ec292 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -33,17 +33,15 @@ * Lukas Steiner */ -#include "DramWideIO.h" - #include -#include -#include -#include "Dram.h" + +#include "DramWideIO.h" #include "../../configuration/Configuration.h" #include "../../error/errormodel.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecWideIO.h" +using namespace sc_core; using namespace tlm; using namespace DRAMPower; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.h b/DRAMSys/library/src/simulation/dram/DramWideIO.h index d46b0867..7cb09e53 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.h @@ -36,21 +36,23 @@ #ifndef DRAMWIDEIO_H #define DRAMWIDEIO_H -#include -#include +#include + +#include +#include #include "Dram.h" #include "../../error/errormodel.h" class DramWideIO : public Dram { public: - explicit DramWideIO(const sc_module_name &name); + explicit DramWideIO(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramWideIO); ~DramWideIO() override; protected: tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_phase &phase, sc_core::sc_time &delay) override; private: std::vector ememory; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp index a5b33758..414bf5bd 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp @@ -34,12 +34,12 @@ */ #include "DramWideIO2.h" - -#include "Dram.h" #include "../../configuration/Configuration.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecWideIO2.h" +using namespace sc_core; + DramWideIO2::DramWideIO2(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.h b/DRAMSys/library/src/simulation/dram/DramWideIO2.h index aa26a175..9f39ca3a 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.h @@ -36,13 +36,13 @@ #ifndef DRAMWIDEIO2_H #define DRAMWIDEIO2_H -#include +#include #include "Dram.h" class DramWideIO2 : public Dram { public: - explicit DramWideIO2(const sc_module_name &name); + explicit DramWideIO2(const sc_core::sc_module_name &name); SC_HAS_PROCESS(DramWideIO2); }; diff --git a/DRAMSys/pct/SocketCoupler.h b/DRAMSys/pct/SocketCoupler.h index aebe9c82..2ae4b1f3 100644 --- a/DRAMSys/pct/SocketCoupler.h +++ b/DRAMSys/pct/SocketCoupler.h @@ -36,15 +36,15 @@ #ifndef SOCKETCOUPLER_H #define SOCKETCOUPLER_H -#include +#include #include #include template -class SocketCoupler : public sc_module +class SocketCoupler : public sc_core::sc_module { public: - SocketCoupler(sc_module_name name) : sc_module(name) + SocketCoupler(sc_core::sc_module_name name) : sc_core::sc_module(name) { for (unsigned i = 0; i < T; i++) { @@ -59,7 +59,7 @@ public: private: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) + tlm::tlm_phase &phase, sc_core::sc_time &delay) { return iSocket[id]->nb_transport_fw(payload, phase, delay); } @@ -70,7 +70,7 @@ private: } tlm::tlm_sync_enum nb_transport_bw(int id, tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) + tlm::tlm_phase &phase, sc_core::sc_time &delay) { return tSocket[id]->nb_transport_bw(payload, phase, delay); } diff --git a/DRAMSys/pct/dummy.h b/DRAMSys/pct/dummy.h index 2f4afec1..aacf50e9 100644 --- a/DRAMSys/pct/dummy.h +++ b/DRAMSys/pct/dummy.h @@ -49,23 +49,23 @@ * real module... */ -class DRAMSys : public sc_module +class DRAMSys : public sc_core::sc_module { public: tlm_utils::multi_passthrough_target_socket tSocket; - sc_event terminateSimulation; + sc_core::sc_event terminateSimulation; SC_HAS_PROCESS(DRAMSys); - DRAMSys(sc_module_name name, - string simulationToRun, - string pathToResources); + DRAMSys(sc_core::sc_module_name name, + std::string simulationToRun, + std::string pathToResources); }; class DRAMSysRecordable : public DRAMSys { public: - DRAMSysRecordable(sc_module_name name, + DRAMSysRecordable(sc_core::sc_module_name name, std::string simulationToRun, std::string pathToResources); }; diff --git a/DRAMSys/simulator/ExampleInitiator.h b/DRAMSys/simulator/ExampleInitiator.h index 57600565..8325f3ed 100644 --- a/DRAMSys/simulator/ExampleInitiator.h +++ b/DRAMSys/simulator/ExampleInitiator.h @@ -39,11 +39,12 @@ #include #include +#include #include "MemoryManager.h" #include "common/dramExtensions.h" #include "TracePlayer.h" -struct ExampleInitiator : sc_module +struct ExampleInitiator : sc_core::sc_module { // TLM-2 socket, defaults to 32-bits wide, base protocol tlm_utils::simple_initiator_socket socket; @@ -61,7 +62,7 @@ struct ExampleInitiator : sc_module { tlm::tlm_generic_payload *trans; tlm::tlm_phase phase; - sc_time delay; + sc_core::sc_time delay; dump_mem(); init_mem(); @@ -96,13 +97,13 @@ struct ExampleInitiator : sc_module phase = tlm::BEGIN_REQ; // Timing annotation models processing time of initiator prior to call - delay = sc_time(100000, SC_PS); + delay = sc_core::sc_time(100000, sc_core::SC_PS); - cout << "Address " << hex << adr << " new, cmd=" << (cmd ? "write" : "read") - << ", data=" << hex << data[0] << " at time " << sc_time_stamp() - << " in " << name() << endl; + std::cout << "Address " << std::hex << adr << " new, cmd=" << (cmd ? "write" : "read") + << ", data=" << std::hex << data[0] << " at time " << sc_core::sc_time_stamp() + << " in " << name() << std::endl; - GenerationExtension *genExtension = new GenerationExtension(sc_time_stamp()); + GenerationExtension *genExtension = new GenerationExtension(sc_core::sc_time_stamp()); trans->set_auto_extension(genExtension); @@ -125,13 +126,13 @@ struct ExampleInitiator : sc_module trans->release(); } - wait( sc_time(500, SC_NS) ); + sc_core::wait(sc_core::sc_time(500, sc_core::SC_NS)); dump_mem(); } - wait( sc_time(500, SC_NS) ); - sc_stop(); + sc_core::wait(sc_core::sc_time(500, sc_core::SC_NS)); + sc_core::sc_stop(); } static void init_mem() @@ -163,16 +164,16 @@ struct ExampleInitiator : sc_module socket->transport_dbg( trans ); - cout << "\nMemory dump\n"; + std::cout << "\nMemory dump\n"; for (int i = 0; i < 64; i++) - cout << "mem[" << addr + i << "] = " << hex << (int)buffer[i] << endl; + std::cout << "mem[" << addr + i << "] = " << std::hex << (int)buffer[i] << std::endl; } } // TLM-2 backward non-blocking transport method virtual tlm::tlm_sync_enum nb_transport_bw( tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, sc_time &delay ) + tlm::tlm_phase &phase, sc_core::sc_time &delay ) { m_peq.notify( trans, phase, delay ); return tlm::TLM_ACCEPTED; @@ -196,7 +197,7 @@ struct ExampleInitiator : sc_module // Send final phase transition to target tlm::tlm_phase fw_phase = tlm::END_RESP; - sc_time delay = sc_time(60000, SC_PS); + sc_core::sc_time delay = sc_core::sc_time(60000, sc_core::SC_PS); socket->nb_transport_fw( trans, fw_phase, delay ); // Ignore return value @@ -219,9 +220,9 @@ struct ExampleInitiator : sc_module uint64_t adr = trans.get_address(); int *ptr = reinterpret_cast( trans.get_data_ptr() ); - cout << hex << adr << " check, cmd=" << (cmd ? "write" : "read") - << ", data=" << hex << *ptr << " at time " << sc_time_stamp() - << " in " << name() << endl; + std::cout << std::hex << adr << " check, cmd=" << (cmd ? "write" : "read") + << ", data=" << std::hex << *ptr << " at time " << sc_core::sc_time_stamp() + << " in " << sc_core::name() << std::endl; if (cmd == tlm::TLM_READ_COMMAND) assert( *ptr == -int(adr) ); @@ -230,7 +231,7 @@ struct ExampleInitiator : sc_module MemoryManager m_mm; unsigned char data[64]; tlm::tlm_generic_payload *request_in_progress; - sc_event end_request_event; + sc_core::sc_event end_request_event; tlm_utils::peq_with_cb_and_phase m_peq; }; diff --git a/DRAMSys/simulator/MemoryManager.cpp b/DRAMSys/simulator/MemoryManager.cpp index bfb64e82..ad4036a3 100644 --- a/DRAMSys/simulator/MemoryManager.cpp +++ b/DRAMSys/simulator/MemoryManager.cpp @@ -37,7 +37,6 @@ #include "MemoryManager.h" #include "common/DebugManager.h" #include "configuration/Configuration.h" -#include using namespace tlm; diff --git a/DRAMSys/simulator/MemoryManager.h b/DRAMSys/simulator/MemoryManager.h index 5d154105..6a26bee8 100644 --- a/DRAMSys/simulator/MemoryManager.h +++ b/DRAMSys/simulator/MemoryManager.h @@ -37,9 +37,10 @@ #ifndef MEMORYMANAGER_H #define MEMORYMANAGER_H -#include #include +#include + class MemoryManager : public tlm::tlm_mm_interface { public: diff --git a/DRAMSys/simulator/StlPlayer.cpp b/DRAMSys/simulator/StlPlayer.cpp index 1b4ab693..7a1a3f5d 100644 --- a/DRAMSys/simulator/StlPlayer.cpp +++ b/DRAMSys/simulator/StlPlayer.cpp @@ -40,6 +40,7 @@ #include "StlPlayer.h" +using namespace sc_core; using namespace tlm; StlPlayer::StlPlayer(const sc_module_name &name, diff --git a/DRAMSys/simulator/StlPlayer.h b/DRAMSys/simulator/StlPlayer.h index 45c883a7..976ba318 100644 --- a/DRAMSys/simulator/StlPlayer.h +++ b/DRAMSys/simulator/StlPlayer.h @@ -45,12 +45,16 @@ #include #include #include +#include + +#include +#include #include "TraceSetup.h" #include "TrafficInitiator.h" struct LineContent { - sc_time sendingTime; + sc_core::sc_time sendingTime; tlm::tlm_command cmd; uint64_t addr; std::vector data; @@ -59,9 +63,9 @@ struct LineContent class StlPlayer : public TrafficInitiator { public: - StlPlayer(const sc_module_name &name, + StlPlayer(const sc_core::sc_module_name &name, const std::string &pathToTrace, - const sc_time &playerClk, + const sc_core::sc_time &playerClk, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, TraceSetup *setup, @@ -79,7 +83,7 @@ private: uint64_t lineCnt = 0; uint64_t numberOfLines = 0; - const sc_time playerClk; // May be different from the memory clock! + const sc_core::sc_time playerClk; // May be different from the memory clock! static constexpr unsigned lineBufferSize = 10000; diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index a9451174..06ab0ccd 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -35,10 +35,12 @@ * Derek Christ */ +#include #include "TraceSetup.h" #include "StlPlayer.h" #include "TrafficGenerator.h" +using namespace sc_core; using namespace tlm; TraceSetup::TraceSetup(const std::string &uri, diff --git a/DRAMSys/simulator/TraceSetup.h b/DRAMSys/simulator/TraceSetup.h index b2aab202..b5ad6435 100644 --- a/DRAMSys/simulator/TraceSetup.h +++ b/DRAMSys/simulator/TraceSetup.h @@ -39,7 +39,8 @@ #include #include -#include + +#include #include "MemoryManager.h" class TrafficInitiator; diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 0011b064..4d9936f8 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -38,6 +38,9 @@ #include "TrafficGenerator.h" +using namespace sc_core; +using namespace tlm; + TrafficGenerator::TrafficGenerator(const sc_module_name &name, const sc_time &generatorClk, uint64_t numRequests, @@ -63,14 +66,14 @@ void TrafficGenerator::sendNextPayload() return; } - tlm::tlm_generic_payload *payload = setup->allocatePayload(); + tlm_generic_payload *payload = setup->allocatePayload(); payload->acquire(); // TODO: column / burst breite uint64_t address = getNextAddress(); - tlm::tlm_command command; + tlm_command command; if (randomRwDistribution(randomGenerator) < rwRatio) { command = tlm::TLM_READ_COMMAND; diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index 16f574a4..6f8006e2 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -39,16 +39,16 @@ #ifndef TRAFFICGENERATOR_H #define TRAFFICGENERATOR_H +#include + #include "TrafficInitiator.h" #include "TraceSetup.h" -#include - class TrafficGenerator : public TrafficInitiator { protected: - TrafficGenerator(const sc_module_name &name, - const sc_time &generatorClk, + TrafficGenerator(const sc_core::sc_module_name &name, + const sc_core::sc_time &generatorClk, uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, @@ -62,7 +62,7 @@ protected: std::default_random_engine randomGenerator; private: - sc_time generatorClk; + sc_core::sc_time generatorClk; uint64_t numRequests; float rwRatio; @@ -73,8 +73,8 @@ private: class TrafficGeneratorRandom final : public TrafficGenerator { public: - TrafficGeneratorRandom(const sc_module_name &name, - const sc_time &generatorClk, + TrafficGeneratorRandom(const sc_core::sc_module_name &name, + const sc_core::sc_time &generatorClk, uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, @@ -91,8 +91,8 @@ private: class TrafficGeneratorSequential final : public TrafficGenerator { public: - TrafficGeneratorSequential(const sc_module_name &name, - const sc_time &generatorClk, + TrafficGeneratorSequential(const sc_core::sc_module_name &name, + const sc_core::sc_time &generatorClk, uint64_t numRequests, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, diff --git a/DRAMSys/simulator/TrafficInitiator.cpp b/DRAMSys/simulator/TrafficInitiator.cpp index ed54a77c..2a7c783e 100644 --- a/DRAMSys/simulator/TrafficInitiator.cpp +++ b/DRAMSys/simulator/TrafficInitiator.cpp @@ -40,6 +40,7 @@ #include "TrafficInitiator.h" #include "TraceSetup.h" +using namespace sc_core; using namespace tlm; TrafficInitiator::TrafficInitiator(const sc_module_name &name, TraceSetup *setup, diff --git a/DRAMSys/simulator/TrafficInitiator.h b/DRAMSys/simulator/TrafficInitiator.h index 1c10e04f..a53f91f0 100644 --- a/DRAMSys/simulator/TrafficInitiator.h +++ b/DRAMSys/simulator/TrafficInitiator.h @@ -41,21 +41,22 @@ #define TRAFFICINITIATOR_H #include -#include -#include -#include -#include #include #include + +#include +#include +#include +#include #include "configuration/Configuration.h" #include "common/DebugManager.h" #include "TraceSetup.h" -class TrafficInitiator : public sc_module +class TrafficInitiator : public sc_core::sc_module { public: tlm_utils::simple_initiator_socket iSocket; - TrafficInitiator(const sc_module_name &name, TraceSetup *setup, + TrafficInitiator(const sc_core::sc_module_name &name, TraceSetup *setup, unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests); SC_HAS_PROCESS(TrafficInitiator); virtual void sendNextPayload() = 0; @@ -66,7 +67,7 @@ protected: bool storageEnabled = false; TraceSetup *setup; void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase, - const sc_time &delay); + const sc_core::sc_time &delay); uint64_t transactionsReceived = 0; uint64_t transactionsSent = 0; @@ -82,7 +83,7 @@ protected: private: tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, - sc_time &bwDelay); + sc_core::sc_time &bwDelay); void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase); bool nextPayloadSendable() const; }; diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index f7d58020..6671baaf 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -38,11 +38,11 @@ #include #include -#include #include #include #include +#include #include "simulation/DRAMSys.h" #include "TraceSetup.h" #include "TrafficInitiator.h" @@ -54,6 +54,8 @@ using json = nlohmann::json; #endif +using namespace sc_core; + std::string pathOfFile(const std::string &file) { return file.substr(0, file.find_last_of('/')); diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index f58f88cb..1e11d963 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -91,8 +91,10 @@ add_executable(TraceAnalyzer presentation/tracemetrictreewidget.cpp businessObjects/phases/phase.cpp presentation/tracedrawingproperties.cpp - presentation/traceplotline.cpp + presentation/util/traceplotline.cpp + presentation/util/traceplotlinecache.cpp presentation/util/customlabelscaledraw.cpp + presentation/traceselector.cpp selectmetrics.ui preferences.ui diff --git a/DRAMSys/traceAnalyzer/businessObjects/comment.h b/DRAMSys/traceAnalyzer/businessObjects/comment.h index 9b6a8a9d..c52753f8 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/comment.h +++ b/DRAMSys/traceAnalyzer/businessObjects/comment.h @@ -33,6 +33,7 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #ifndef COMMENT_H @@ -54,6 +55,10 @@ public: { return text; } + void changeText(QString newText) + { + text = newText; + } }; #endif // COMMENT_H diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp index a5c6e5d3..c99e1788 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp @@ -37,6 +37,7 @@ */ #include "phase.h" +#include "presentation/util/traceplotline.h" #include "presentation/tracedrawing.h" #include "businessObjects/transaction.h" #include @@ -64,35 +65,29 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, painter->setPen(pen); } - if (!isCollapsed(drawingProperties)) + for (auto line : getTracePlotLines(drawingProperties)) { - if (getGranularity() == Granularity::Rankwise) - { - for (int i = getYVal(drawingProperties); i < (int)(getYVal(drawingProperties) + drawingProperties.banksPerRank); i++) - drawPhaseSymbol(span.Begin(), span.End(), i, drawingProperties.drawText, - getPhaseSymbol(), painter, xMap, yMap); - } - else if (getGranularity() == Granularity::Groupwise) - { - for (int i = getYVal(drawingProperties); i < (int)(getYVal(drawingProperties) + drawingProperties.banksPerRank); i += drawingProperties.banksPerGroup) - drawPhaseSymbol(span.Begin(), span.End(), i, drawingProperties.drawText, - getPhaseSymbol(), painter, xMap, yMap); - } - else // if (getGranularity() == Granularity::Bankwise) - drawPhaseSymbol(span.Begin(), span.End(), getYVal(drawingProperties), + if (!line->isCollapsed()) + drawPhaseSymbol(span.Begin(), span.End(), line->getYVal(), drawingProperties.drawText, getPhaseSymbol(), painter, xMap, yMap); } for (Timespan span : spansOnCommandBus) { - drawPhaseSymbol(span.Begin(), span.End(), drawingProperties.yValCommandBus, - false, PhaseSymbol::Hexagon, painter, xMap, yMap); + for (auto commandBusLine : drawingProperties.getCommandBusLines()) + { + drawPhaseSymbol(span.Begin(), span.End(), commandBusLine->getYVal(), + false, PhaseSymbol::Hexagon, painter, xMap, yMap); + } } if (spanOnDataBus) { - drawPhaseSymbol(spanOnDataBus->Begin(), spanOnDataBus->End(), drawingProperties.yValDataBus, - false, PhaseSymbol::Hexagon, painter, xMap, yMap); + for (auto dataBusLine : drawingProperties.getDataBusLines()) + { + drawPhaseSymbol(spanOnDataBus->Begin(), spanOnDataBus->End(), dataBusLine->getYVal(), + false, PhaseSymbol::Hexagon, painter, xMap, yMap); + } } } @@ -137,16 +132,6 @@ QColor Phase::getColor(const TraceDrawingProperties &drawingProperties) const } } -int Phase::getYVal(const TraceDrawingProperties &drawingProperties) const -{ - if (getGranularity() == Granularity::Bankwise) - return drawingProperties.getYValOfBank(transaction.lock()->bank); - else if (getGranularity() == Granularity::Groupwise) - return drawingProperties.getYValOfBankGroup(transaction.lock()->rank, transaction.lock()->bank); - else // if (getGranularity() == Granularity::Rankwise) - return drawingProperties.getYValOfRank(transaction.lock()->rank); -} - Qt::BrushStyle Phase::getBrushStyle() const { return Qt::SolidPattern; @@ -160,36 +145,31 @@ bool Phase::isSelected(traceTime time, double yVal, if (span.Begin() <= time && time <= (span.End() + offset)) { - if (getGranularity() == Granularity::Bankwise) + for (auto line : getTracePlotLines(drawingProperties)) { - if (fabs(yVal - getYVal(drawingProperties)) <= hexagonHeight) + if (!line->isCollapsed() && fabs(yVal - line->getYVal()) <= hexagonHeight) return true; } - else if (getGranularity() == Granularity::Groupwise) - { - for (int offset = 0; offset < drawingProperties.banksPerRank; offset += drawingProperties.banksPerGroup) - { - if (fabs(yVal - (getYVal(drawingProperties) + offset)) <= hexagonHeight) - return true; - } - } - else // if (getGranularity() == Granularity::Rankwise) - { - for (int offset = 0; offset < drawingProperties.banksPerRank; offset++) - { - if (fabs(yVal - (getYVal(drawingProperties) + offset)) <= hexagonHeight) - return true; - } - } } - if (spanOnDataBus && spanOnDataBus->contains(time) && fabs(yVal - drawingProperties.yValDataBus) <= hexagonHeight) - return true; + if (spanOnDataBus && spanOnDataBus->contains(time)) + { + for (auto dataBusLine : drawingProperties.getDataBusLines()) + { + if (fabs(yVal - dataBusLine->getYVal()) <= hexagonHeight) + return true; + } + } for (Timespan span : spansOnCommandBus) { - if (span.contains(time) - && fabs(yVal - drawingProperties.yValCommandBus) <= hexagonHeight) - return true; + if (span.contains(time)) + { + for (auto commandBusLine : drawingProperties.getCommandBusLines()) + { + if (fabs(yVal - commandBusLine->getYVal()) <= hexagonHeight) + return true; + } + } } return false; @@ -200,11 +180,23 @@ Phase::PhaseSymbol Phase::getPhaseSymbol() const return PhaseSymbol::Hexagon; } -bool Phase::isCollapsed(const TraceDrawingProperties &drawingProperties) const +std::vector> Phase::getTracePlotLines(const TraceDrawingProperties &drawingProperties) const { - // Never discard REQ and RESP phases - if (dynamic_cast(this) != nullptr || dynamic_cast(this) != nullptr) - return false; - - return drawingProperties.getRankCollapsedState(transaction.lock()->rank); + if (getGranularity() == Granularity::Rankwise) + { + return drawingProperties.getBankLinesFromRank(transaction.lock()->rank); + } + else if (getGranularity() == Granularity::Groupwise) + { + return drawingProperties.getBankLinesGroupwise(transaction.lock()->rank, + transaction.lock()->bank % drawingProperties.banksPerGroup); + } + else // if (getGranularity() == Granularity::Bankwise) + { + return drawingProperties.getBankLines(transaction.lock()->rank, + transaction.lock()->bankgroup % drawingProperties.groupsPerRank, + transaction.lock()->bank + % drawingProperties.banksPerRank + % drawingProperties.banksPerGroup); + } } diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index 8e1bb888..6dc97f9e 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -90,20 +90,20 @@ protected: virtual PhaseSymbol getPhaseSymbol() const; virtual Qt::BrushStyle getBrushStyle() const; virtual QColor getColor(const TraceDrawingProperties &drawingProperties) const; - virtual int getYVal(const TraceDrawingProperties &drawingProperties) const; + virtual QColor getPhaseColor() const = 0; virtual void drawPhaseSymbol(traceTime begin, traceTime end, double y, bool drawtext, PhaseSymbol symbol, QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap) const; + virtual std::vector> getTracePlotLines(const TraceDrawingProperties &drawingProperties) const; + enum class Granularity {Bankwise, Groupwise, Rankwise}; virtual Granularity getGranularity() const { return Granularity::Bankwise; } - - bool isCollapsed(const TraceDrawingProperties &drawingProperties) const; }; class REQ : public Phase @@ -119,10 +119,10 @@ protected: { return "REQ"; } - virtual int getYVal(const TraceDrawingProperties &drawingProperties) const + virtual std::vector> getTracePlotLines(const TraceDrawingProperties &drawingProperties) const override { - return drawingProperties.yValRequest; + return drawingProperties.getRequestLines(); } }; @@ -140,10 +140,10 @@ protected: { return "RESP"; } - virtual int getYVal(const TraceDrawingProperties &drawingProperties) const + virtual std::vector> getTracePlotLines(const TraceDrawingProperties &drawingProperties) const override { - return drawingProperties.yValResponse; + return drawingProperties.getResponseLines(); } }; diff --git a/DRAMSys/traceAnalyzer/presentation/commenttreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/commenttreewidget.cpp index 17fee5e5..519e04e4 100644 --- a/DRAMSys/traceAnalyzer/presentation/commenttreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/commenttreewidget.cpp @@ -33,12 +33,49 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #include "commenttreewidget.h" #include #include #include +#include +#include +#include + +CommentTreeWidget::CommentTreeWidget(QWidget *parent) : QTreeWidget(parent), + deleteComment(new QAction("Delete comment", this)), + changeCommentText(new QAction("Change comment text", this)) +{ + connect(deleteComment, &QAction::triggered, this, [this](){ + for (QTreeWidgetItem *item : selectedItems()) + { + CommentTreeItem *commentItem = static_cast(item); + navigator->removeCommentAtTime(commentItem->Time()); + } + }); + + connect(changeCommentText, &QAction::triggered, this, [this](){ + for (QTreeWidgetItem *item : selectedItems()) + { + CommentTreeItem *commentItem = static_cast(item); + + bool ok; + QString newText = QInputDialog::getText(this, QString("Change comment text"), + QString("Change comment text"), QLineEdit::Normal, + QString(), &ok); + + if (ok) + { + deleteComment->trigger(); + navigator->insertComment({commentItem->Time(), newText}); + } + + commentsChanged(); + } + }); +} void CommentTreeWidget::init(TraceNavigator *navigator) { @@ -54,7 +91,6 @@ void CommentTreeWidget::init(TraceNavigator *navigator) QObject::connect(this, SIGNAL(customContextMenuRequested(QPoint)), this, SLOT(ContextMenuRequested(QPoint))); setContextMenuPolicy(Qt::CustomContextMenu); - deleteComment = new QAction("Delete comment", this); printComments(); } @@ -82,16 +118,9 @@ void CommentTreeWidget::itemDoubleClicked(QTreeWidgetItem *item, int /*column*/) void CommentTreeWidget::ContextMenuRequested(QPoint point) { - QMenu contextMenu; - contextMenu.addActions({deleteComment}); - QAction *selectedItem = contextMenu.exec(mapToGlobal(point)); - - if (selectedItem) { - for (QTreeWidgetItem *item : selectedItems()) { - CommentTreeItem *commentItem = static_cast(item); - navigator->removeCommentAtTime(commentItem->Time()); - } - } + QMenu contextMenu(this); + contextMenu.addActions({deleteComment, changeCommentText}); + contextMenu.exec(mapToGlobal(point)); } @@ -101,3 +130,13 @@ CommentTreeWidget::CommentTreeItem::CommentTreeItem(QTreeWidget *parent, this->setText(0, prettyFormatTime(comment.Time())); this->setText(1, comment.Text()); } + +void CommentTreeWidget::keyPressEvent(QKeyEvent *event) +{ + if (event->key() == Qt::Key_Delete) + deleteComment->trigger(); + else if (event->key() == Qt::Key_F2) + changeCommentText->trigger(); + + QTreeWidget::keyPressEvent(event); +} diff --git a/DRAMSys/traceAnalyzer/presentation/commenttreewidget.h b/DRAMSys/traceAnalyzer/presentation/commenttreewidget.h index 8a9d1c48..7429f75e 100644 --- a/DRAMSys/traceAnalyzer/presentation/commenttreewidget.h +++ b/DRAMSys/traceAnalyzer/presentation/commenttreewidget.h @@ -33,6 +33,7 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #ifndef COMMENTTREEWIDGET_H @@ -48,20 +49,23 @@ class CommentTreeWidget : public QTreeWidget Q_OBJECT public: - CommentTreeWidget(QWidget *parent = 0) : QTreeWidget(parent), - isInitialized(false) {} + CommentTreeWidget(QWidget *parent = nullptr); void init(TraceNavigator *navigator); -public Q_SLOTS: +protected: + void keyPressEvent(QKeyEvent *event) override; + +private Q_SLOTS: void commentsChanged(); - void itemDoubleClicked(QTreeWidgetItem *item, int column); void ContextMenuRequested(QPoint point); + void itemDoubleClicked(QTreeWidgetItem *item, int column); private: - bool isInitialized; + bool isInitialized = false; TraceNavigator *navigator; void printComments(); QAction *deleteComment; + QAction *changeCommentText; class CommentTreeItem : public QTreeWidgetItem { @@ -69,10 +73,18 @@ private: Comment comment; public: CommentTreeItem(QTreeWidget *parent, const Comment &comment); + QString Text() + { + return comment.Text(); + } traceTime Time() { return comment.Time(); } + void changeText(QString newText) + { + comment.changeText(newText); + } }; }; diff --git a/DRAMSys/traceAnalyzer/presentation/tracePlotMouseLabel.cpp b/DRAMSys/traceAnalyzer/presentation/tracePlotMouseLabel.cpp index 7ef7271d..c77aea5c 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracePlotMouseLabel.cpp +++ b/DRAMSys/traceAnalyzer/presentation/tracePlotMouseLabel.cpp @@ -37,6 +37,7 @@ #include "tracePlotMouseLabel.h" #include "businessObjects/tracetime.h" +#include void TracePlotMouseLabel::setMode(MouseLabelMode mode) { diff --git a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.cpp b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.cpp index 7b9ef486..0ed8d044 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.cpp +++ b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.cpp @@ -34,60 +34,96 @@ */ #include "tracedrawingproperties.h" - -TraceDrawingProperties::TraceDrawingProperties() : - drawText(true), - drawBorder(true), - colorGrouping(ColorGrouping::PhaseType) -{ -} +#include "util/customlabelscaledraw.h" +#include "traceplot.h" +#include "util/traceplotline.h" +#include "util/traceplotlinecache.h" +#include "traceselector.h" TraceDrawingProperties::TraceDrawingProperties(bool drawText, bool drawBorder, ColorGrouping colorGrouping) : - drawText(drawText), - drawBorder(drawBorder), - colorGrouping(colorGrouping) + drawText(drawText), + drawBorder(drawBorder), + colorGrouping(colorGrouping) { } -void TraceDrawingProperties::setUpTracePlotLines() +TraceDrawingProperties::~TraceDrawingProperties() { - tracePlotLines.push_back(std::make_shared("REQ", collapsedRanks)); - tracePlotLines.push_back(std::make_shared("RESP", collapsedRanks)); + tracePlotLines->clear(); + tracePlotLineCache->clearCache(); +} - for (unsigned int rank = numberOfRanks; rank--;) +void TraceDrawingProperties::init(std::shared_ptr tracePlotLines, + std::shared_ptr tracePlotLineCache) +{ + this->tracePlotLines = tracePlotLines; + this->tracePlotLineCache = tracePlotLineCache; +} + +void TraceDrawingProperties::init(std::shared_ptr tracePlotLines, + std::shared_ptr tracePlotLineCache, + TracePlot *tracePlot) +{ + this->tracePlotLines = tracePlotLines; + this->tracePlotLineCache = tracePlotLineCache; + this->tracePlot = tracePlot; +} + +void TraceDrawingProperties::updateTracePlotLines(QTreeWidget *treeWidget) +{ + tracePlotLines->clear(); + tracePlot->getCustomLabelScaleDraw()->clearCache(); + clearCache(); + + for (int i = 0; i < treeWidget->topLevelItemCount(); i++) { - for (unsigned int group = groupsPerRank; group--;) - { - for (unsigned int bank = banksPerGroup; bank--;) - { - QString rankLabel = QString("RA") + QString::number(rank); - QString bankGroupLabel = QString("BG") + QString::number(group); - QString bankLabel = QString("BA") + QString::number(bank); + auto currentTreeItem = static_cast(treeWidget->topLevelItem(i)); - QString label = rankLabel + QString(" ") + bankGroupLabel + QString(" ") + bankLabel; - - std::shared_ptr line; - - if (bank == banksPerGroup - 1 && group == groupsPerRank - 1) - line = std::make_shared(label, rankLabel, rank, collapsedRanks); - else - line = std::make_shared(label, rank, collapsedRanks); - - tracePlotLines.push_back(line); - } - } + if (currentTreeItem->type == TraceSelectorTreeItem::Type::RequestLineItem) + tracePlotLines->push_back(std::make_shared()); + else if (currentTreeItem->type == TraceSelectorTreeItem::Type::ResponseLineItem) + tracePlotLines->push_back(std::make_shared()); + else if (currentTreeItem->type == TraceSelectorTreeItem::Type::CommandBusLineItem) + tracePlotLines->push_back(std::make_shared()); + else if (currentTreeItem->type == TraceSelectorTreeItem::Type::DataBusLineItem) + tracePlotLines->push_back(std::make_shared()); + else if (currentTreeItem->type == TraceSelectorTreeItem::Type::BankLineItem) + tracePlotLines->push_back(std::make_shared(currentTreeItem->rank, currentTreeItem->bankgroup, currentTreeItem->bank)); + else if (currentTreeItem->type == TraceSelectorTreeItem::Type::RankGroupItem) + addRankGroup(currentTreeItem->rank); } - tracePlotLines.push_back(std::make_shared("Command Bus", collapsedRanks)); - tracePlotLines.push_back(std::make_shared("Data Bus", collapsedRanks)); + updateLabels(); + tracePlot->updateScrollbar(); - // Collapse all ranks except the first one by default. - for (int i = 0; i < numberOfRanks; i++) - if (i == 0) - setRankCollapsedState(i, false); - else - setRankCollapsedState(i, true); + // This call is needed, otherwise the labels of the axis will not update properly. + tracePlot->update(); +} + +void TraceDrawingProperties::addRankGroup(unsigned int rank) +{ + std::shared_ptr firstRankLine; + + for (unsigned int group = groupsPerRank; group--;) + { + for (unsigned int bank = banksPerGroup; bank--;) + { + std::shared_ptr line; + + if (bank == banksPerGroup - 1 && group == groupsPerRank - 1) + { + firstRankLine = createFirstRankLine(rank, group, bank); + line = firstRankLine; + } + else + { + line = std::make_shared(rank, group, bank, firstRankLine); + } + + tracePlotLines->push_back(line); + } + } } void TraceDrawingProperties::updateLabels() @@ -95,39 +131,42 @@ void TraceDrawingProperties::updateLabels() // Clear hash table, because otherwise not all old values will be overwritten. labels->clear(); - // The data bus is defined to start at -4. - int i = -4; + // The lowest line starts at the y value of 0. + int i = 0; - for (auto it = tracePlotLines.rbegin(); it != tracePlotLines.rend(); it++) + for (auto it = tracePlotLines->rbegin(); it != tracePlotLines->rend(); it++) { // Don't add collapsed ranks, but always add the first rank line. auto bankLine = std::dynamic_pointer_cast(*it); auto firstRankLine = std::dynamic_pointer_cast(*it); - if (!firstRankLine && bankLine && (*collapsedRanks)[bankLine->rank]) + if (!firstRankLine && bankLine && bankLine->isCollapsed()) continue; (*labels)[i] = (*it)->getLabel(); (*it)->setYVal(i); - if (std::dynamic_pointer_cast(*it)) - yValRequest = i; - - if (std::dynamic_pointer_cast(*it)) - yValResponse = i; - - if (std::dynamic_pointer_cast(*it)) - yValDataBus = i; - - if (std::dynamic_pointer_cast(*it)) { - yValCommandBus = i; - - // Add two spaces. - i += 2; - } - i++; } + + Q_EMIT tracePlot->tracePlotLinesChanged(); +} + +std::shared_ptr TraceDrawingProperties::createFirstRankLine(unsigned int rank, unsigned int group, + unsigned int bank) const +{ + auto firstRankLine = std::make_shared(rank, group, bank, tracePlot); + + QObject::connect(firstRankLine.get(), &TracePlotFirstRankLine::collapsedStateChanged, + this, &TraceDrawingProperties::updateLabels); + + QObject::connect(firstRankLine.get(), &TracePlotFirstRankLine::collapsedStateChanged, + tracePlot, &TracePlot::updateScrollbar); + + QObject::connect(tracePlot->getCustomLabelScaleDraw(), &CustomLabelScaleDraw::scaleRedraw, + firstRankLine.get(), &TracePlotFirstRankLine::updateButtonPosition); + + return firstRankLine; } const std::shared_ptr> TraceDrawingProperties::getLabels() const @@ -135,68 +174,76 @@ const std::shared_ptr> TraceDrawingProperties::getLabels() c return labels; } -const std::vector> & TraceDrawingProperties::getTracePlotLines() const -{ - return tracePlotLines; -} - -const std::shared_ptr TraceDrawingProperties::getFirstRankLine(unsigned int rank) const -{ - // TODO: Maybe cache results? - Q_ASSERT(rank <= numberOfRanks - 1); - - std::shared_ptr firstRankLine; - - for (auto &line : tracePlotLines) - { - firstRankLine = std::dynamic_pointer_cast(line); - if (firstRankLine && firstRankLine->rank == rank) - break; - } - - return firstRankLine; -} - -void TraceDrawingProperties::setRankCollapsedState(unsigned int rank, bool collapse) -{ - Q_ASSERT(rank <= numberOfRanks - 1); - - (*collapsedRanks)[rank] = collapse; - - updateLabels(); -} - -bool TraceDrawingProperties::getRankCollapsedState(unsigned int rank) const -{ - return (*collapsedRanks)[rank]; -} - unsigned int TraceDrawingProperties::getNumberOfDisplayedLines() const { - return yValRequest + 6; + if (!tracePlotLines) + return 0; + + unsigned int max = 0; + + for (auto line : *tracePlotLines) + { + if (!line->isCollapsed() && max < line->getYVal()) + max = line->getYVal(); + } + + return max; } -unsigned int TraceDrawingProperties::getYValOfBank(unsigned int bank) const +void TraceDrawingProperties::clearCache() const { - unsigned int rank = bank / banksPerRank; - - return getYValOfRank(rank) + bank % banksPerRank; + tracePlotLineCache->clearCache(); } -unsigned int TraceDrawingProperties::getYValOfBankGroup(unsigned int rank, unsigned int bank) const +TracePlotLineVector TraceDrawingProperties::getRequestLines() const { - return getYValOfRank(rank) + bank % banksPerGroup; + return tracePlotLineCache->getRequestLines(); } -unsigned int TraceDrawingProperties::getYValOfRank(unsigned int rank) const +TracePlotLineVector TraceDrawingProperties::getResponseLines() const { - unsigned int i = 0; - - for (unsigned int j = 0; j < rank; j++) - if ((*collapsedRanks)[j]) - i += 1; - else - i += banksPerRank; - - return i; + return tracePlotLineCache->getResponseLines(); +} + +TracePlotLineVector TraceDrawingProperties::getCommandBusLines() const +{ + return tracePlotLineCache->getCommandBusLines(); +} + +TracePlotLineVector TraceDrawingProperties::getDataBusLines() const +{ + return tracePlotLineCache->getDataBusLines(); +} + +TracePlotLineVector TraceDrawingProperties::getFirstRankLines(unsigned int rank) const +{ + return tracePlotLineCache->getFirstRankLines(rank); +} + +TracePlotLineVector TraceDrawingProperties::getBankLines(unsigned int rank, unsigned int group, unsigned int bank) const +{ + return tracePlotLineCache->getBankLines(rank, group, bank); +} + +TracePlotLineVector TraceDrawingProperties::getBankLinesFromGroup(unsigned int rank, unsigned int group) const +{ + return tracePlotLineCache->getBankLinesFromGroup(rank, group); +} + +TracePlotLineVector TraceDrawingProperties::getBankLinesGroupwise(unsigned int rank, + unsigned int bank) const +{ + auto rankLines = tracePlotLineCache->getBankLinesFromRank(rank); + TracePlotLineVector groupwiseLines; + + std::copy_if(rankLines.begin(), rankLines.end(), std::back_inserter(groupwiseLines), + [bank](std::shared_ptr line) + { return std::static_pointer_cast(line)->bank == bank; }); + + return groupwiseLines; +} + +TracePlotLineVector TraceDrawingProperties::getBankLinesFromRank(unsigned int rank) const +{ + return tracePlotLineCache->getBankLinesFromRank(rank); } diff --git a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h index 37ff6564..f214c9ce 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h +++ b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h @@ -39,23 +39,33 @@ #ifndef TRACECOLLECTIONDRAWINGPROPERTIES_H #define TRACECOLLECTIONDRAWINGPROPERTIES_H +#include #include #include #include #include +#include +#include #include "tracedrawing.h" -#include "traceplotline.h" +#include "util/traceplotline.h" +#include "traceselector.h" enum class ColorGrouping {PhaseType, Transaction, Thread}; -struct TraceDrawingProperties { +class TracePlot; +class TracePlotLineCache; + +using TracePlotLineVector = std::vector>; + +class TraceDrawingProperties : public QObject +{ + Q_OBJECT + +public: bool drawText; bool drawBorder; ColorGrouping colorGrouping; - int yValResponse; - int yValRequest; - int yValCommandBus; - int yValDataBus; + unsigned int numberOfRanks; unsigned int numberOfBankgroups; unsigned int numberOfBanks; @@ -63,30 +73,46 @@ struct TraceDrawingProperties { unsigned int groupsPerRank; unsigned int banksPerGroup; - TraceDrawingProperties(); - TraceDrawingProperties(bool drawText, bool drawBorder, ColorGrouping colorGrouping); - void setUpTracePlotLines(); + TraceDrawingProperties(bool drawText = true, + bool drawBorder = true, + ColorGrouping colorGrouping = ColorGrouping::PhaseType); + ~TraceDrawingProperties(); - void setRankCollapsedState(unsigned int rank, bool collapse); - bool getRankCollapsedState(unsigned int rank) const; + void init(std::shared_ptr tracePlotLines, + std::shared_ptr tracePlotLineCache); + + void init(std::shared_ptr tracePlotLines, + std::shared_ptr tracePlotLineCache, TracePlot *tracePlot); unsigned int getNumberOfDisplayedLines() const; - unsigned int getYValOfBank(unsigned int bank) const; - unsigned int getYValOfBankGroup(unsigned int rank, unsigned int bank) const; - unsigned int getYValOfRank(unsigned int rank) const; + TracePlotLineVector getRequestLines() const; + TracePlotLineVector getResponseLines() const; + TracePlotLineVector getCommandBusLines() const; + TracePlotLineVector getDataBusLines() const; + TracePlotLineVector getFirstRankLines(unsigned int rank) const; + TracePlotLineVector getBankLines(unsigned int rank, unsigned int group, unsigned int bank) const; + TracePlotLineVector getBankLinesFromGroup(unsigned int rank, unsigned int group) const; + TracePlotLineVector getBankLinesGroupwise(unsigned int rank, unsigned int bank) const; + TracePlotLineVector getBankLinesFromRank(unsigned int rank) const; - - const std::vector> & getTracePlotLines() const; - const std::shared_ptr getFirstRankLine(unsigned int rank) const; - - void updateLabels(); const std::shared_ptr> getLabels() const; + void updateTracePlotLines(QTreeWidget *treeWidget); + private: + void updateLabels(); + void clearCache() const; + void addRankGroup(unsigned int rank); + std::shared_ptr createFirstRankLine(unsigned int rank, unsigned int group, + unsigned int bank) const; + std::shared_ptr> labels = std::make_shared>(); - std::shared_ptr> collapsedRanks = std::make_shared>(); - std::vector> tracePlotLines; + + std::shared_ptr tracePlotLines; + std::shared_ptr tracePlotLineCache; + + TracePlot *tracePlot; }; #endif // TRACECOLLECTIONDRAWINGPROPERTIES_H diff --git a/DRAMSys/traceAnalyzer/presentation/tracenavigator.cpp b/DRAMSys/traceAnalyzer/presentation/tracenavigator.cpp index 7ff82f87..86ea4bc1 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracenavigator.cpp +++ b/DRAMSys/traceAnalyzer/presentation/tracenavigator.cpp @@ -33,9 +33,11 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #include "tracenavigator.h" +#include "util/traceplotlinecache.h" #include "vector" using namespace std; @@ -44,10 +46,15 @@ TraceNavigator::TraceNavigator(QString path, QObject *parent) : QObject(parent), traceFile(path, true), changesToCommitExist(false) { getCommentsFromDB(); + + tracePlotLineCache = + std::make_shared(getTracePlotLines(), GeneralTraceInfo().numberOfRanks, + GeneralTraceInfo().groupsPerRank, GeneralTraceInfo().banksPerGroup); } TraceNavigator::~TraceNavigator() { + tracePlotLines->clear(); } /* Navigation @@ -317,3 +324,13 @@ Timespan TraceNavigator::getSpanCoveredBySelectedTransaction() return Timespan(begin, end); } + +std::shared_ptr TraceNavigator::getTracePlotLines() +{ + return tracePlotLines; +} + +std::shared_ptr TraceNavigator::getTracePlotLineCache() +{ + return tracePlotLineCache; +} diff --git a/DRAMSys/traceAnalyzer/presentation/tracenavigator.h b/DRAMSys/traceAnalyzer/presentation/tracenavigator.h index dd97db47..374c3f08 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracenavigator.h +++ b/DRAMSys/traceAnalyzer/presentation/tracenavigator.h @@ -33,6 +33,7 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #ifndef TRACENAVIGATOR_H @@ -45,6 +46,8 @@ #include "businessObjects/comment.h" #include "memory" +class TracePlotLineCache; + /* Class to navigate through a tracefile * * @@ -117,6 +120,9 @@ public: void commitChangesToDB(); void refreshData(); + std::shared_ptr getTracePlotLines(); + std::shared_ptr getTracePlotLineCache(); + Q_SIGNALS: void currentTraceTimeChanged(); void selectedTransactionsChanged(); @@ -133,6 +139,8 @@ private: void getCommentsFromDB(); bool changesToCommitExist; + std::shared_ptr tracePlotLines = std::make_shared(); + std::shared_ptr tracePlotLineCache; }; #endif // TRACENAVIGATOR_H diff --git a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp index caf99c8f..ebc67c39 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp +++ b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp @@ -63,7 +63,8 @@ using namespace std; TracePlot::TracePlot(QWidget *parent): - QwtPlot(parent), isInitialized(false) + QwtPlot(parent), isInitialized(false), + customLabelScaleDraw(new CustomLabelScaleDraw(drawingProperties.getLabels())) { canvas()->setCursor(Qt::ArrowCursor); setUpActions(); @@ -193,6 +194,9 @@ void TracePlot::init(TraceNavigator *navigator, QScrollBar *scrollBar) navigator->GeneralTraceInfo().clkPeriod, this->mouseDownData.zoomSpan); getAndDrawComments(); setZoomLevel(1000); + + updateScrollbar(); + replot(); } @@ -209,14 +213,14 @@ void TracePlot::connectNavigatorQ_SIGNALS() void TracePlot::setUpDrawingProperties() { + drawingProperties.init(navigator->getTracePlotLines(), navigator->getTracePlotLineCache(), this); + drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; drawingProperties.numberOfBankgroups = navigator->GeneralTraceInfo().numberOfBankgroups; drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; drawingProperties.banksPerRank = drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; drawingProperties.groupsPerRank = drawingProperties.numberOfBankgroups / drawingProperties.numberOfRanks; drawingProperties.banksPerGroup = drawingProperties.numberOfBanks / drawingProperties.numberOfBankgroups; - - drawingProperties.setUpTracePlotLines(); } void TracePlot::setUpQueryEditor() @@ -257,33 +261,33 @@ void TracePlot::setUpZoom() void TracePlot::updateScrollbar() { - const unsigned int pageStep = scrollBar->pageStep(); + // The maximum number of displayed lines determined by the pageStep of the scroll bar. + const unsigned int maxDisplayedLines = scrollBar->pageStep(); - const int maximum = drawingProperties.getNumberOfDisplayedLines() - pageStep; + const int maximum = drawingProperties.getNumberOfDisplayedLines() - maxDisplayedLines; if (maximum >= 0) { - scrollBar->setMaximum(drawingProperties.getNumberOfDisplayedLines() - pageStep); + scrollBar->setMaximum(maximum); scrollBar->show(); } else scrollBar->hide(); + + verticalScrollbarChanged(scrollBar->value()); } void TracePlot::verticalScrollbarChanged(int value) { - const int yValRequest = drawingProperties.yValRequest; + const int yMax = drawingProperties.getNumberOfDisplayedLines(); - // The maximum number of displayed lines determined by the pageStep of the scroll bar. - const int maxDisplayedLines = scrollBar->pageStep(); - - if (drawingProperties.getNumberOfDisplayedLines() <= maxDisplayedLines) + if (scrollBar->isHidden()) { - setAxisScale(yLeft, -5, yValRequest + 1, 1.0); + setAxisScale(yLeft, -1, yMax + 1, 1.0); } else { - setAxisScale(yLeft, yValRequest - maxDisplayedLines + 1 - value, yValRequest + 1 - value, 1.0); + setAxisScale(yLeft, scrollBar->maximum() - 1 - value, yMax + 1 - value, 1.0); } replot(); @@ -291,65 +295,20 @@ void TracePlot::verticalScrollbarChanged(int value) void TracePlot::setUpAxis() { - CustomLabelScaleDraw *customLabelScaleDraw = new CustomLabelScaleDraw(drawingProperties.getLabels()); - customLabelScaleDraw->setMinimumExtent(135.0); - - auto positionButton = [&](const TracePlotFirstRankLine &firstRankLine, RankButton &rankButton) { - QPointF point = this->axisScaleDraw(yLeft)->labelPosition(firstRankLine.getYVal()); - rankButton.setGeometry(point.x(), point.y() - 4, 25, 25); - }; - - QObject::connect(customLabelScaleDraw, &CustomLabelScaleDraw::scaleRedraw, this, [=]() { - for (auto rankButton : rankCollapseButtons) - { - auto firstRankLine = drawingProperties.getFirstRankLine(rankButton->rank); - positionButton(*firstRankLine, *rankButton); - } - }); - - updateScrollbar(); - // Set up y axis. - verticalScrollbarChanged(scrollBar->value()); setAxisScaleDraw(yLeft, customLabelScaleDraw); - - // Add push buttons - for (auto line : drawingProperties.getTracePlotLines()) - { - auto firstRankLine = std::dynamic_pointer_cast(line); - if (firstRankLine) - { - auto button = new RankButton(firstRankLine->rank, this); - if (drawingProperties.getRankCollapsedState(firstRankLine->rank)) - button->setText("+"); - else - button->setText("-"); - - positionButton(*firstRankLine, *button); - - QObject::connect(button, &QPushButton::pressed, this, [=]() { - bool wasCollapsed = drawingProperties.getRankCollapsedState(button->rank); - drawingProperties.setRankCollapsedState(button->rank, !wasCollapsed); - - if (wasCollapsed) - button->setText("-"); - else - button->setText("+"); - - updateScrollbar(); - - emit scrollBar->valueChanged(scrollBar->value()); - }); - - rankCollapseButtons.push_back(button); - } - } + customLabelScaleDraw->setMinimumExtent(135.0); // Set up x axis. setAxisTitle(xBottom, "Time in ns"); setAxisScaleDraw(xBottom, new EngineeringScaleDraw); } +void TracePlot::updateTracePlotLines(QTreeWidget *treeWidget) +{ + drawingProperties.updateTracePlotLines(treeWidget); +} + Timespan TracePlot::GetCurrentTimespan() { Timespan span(navigator->CurrentTraceTime() - zoomLevel / 2, @@ -376,6 +335,16 @@ void TracePlot::getAndDrawComments() } } +CustomLabelScaleDraw *TracePlot::getCustomLabelScaleDraw() const +{ + return customLabelScaleDraw; +} + +const TraceDrawingProperties &TracePlot::getDrawingProperties() const +{ + return drawingProperties; +} + void TracePlot::enterZoomMode() { mouseDownData.mouseIsDownForZooming = true; diff --git a/DRAMSys/traceAnalyzer/presentation/traceplot.h b/DRAMSys/traceAnalyzer/presentation/traceplot.h index 5f40a4eb..3b2f9dc7 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplot.h +++ b/DRAMSys/traceAnalyzer/presentation/traceplot.h @@ -61,14 +61,7 @@ */ class TracePlotMouseLabel; - -class RankButton : public QPushButton -{ - Q_OBJECT -public: - explicit RankButton(unsigned int rank, QWidget *parent = nullptr) : QPushButton(parent), rank(rank) {} - const unsigned int rank; -}; +class CustomLabelScaleDraw; class TracePlot : public QwtPlot { @@ -87,15 +80,20 @@ public: void setUpActions(); void setUpContextMenu(); + + CustomLabelScaleDraw *getCustomLabelScaleDraw() const; + const TraceDrawingProperties &getDrawingProperties() const; public Q_SLOTS: void currentTraceTimeChanged(); void selectedTransactionsChanged(); void commentsChanged(); void verticalScrollbarChanged(int value); - + void updateScrollbar(); + void updateTracePlotLines(QTreeWidget *treeWidget); Q_SIGNALS: void tracePlotZoomChanged(); + void tracePlotLinesChanged(); void colorGroupingChanged(ColorGrouping colorgrouping); private Q_SLOTS: @@ -126,6 +124,7 @@ private: QueryEditor *queryEditor; QMenu *contextMenu; QScrollBar *scrollBar; + CustomLabelScaleDraw *customLabelScaleDraw; void setUpTracePlotItem(); void setUpDrawingProperties(); @@ -137,9 +136,6 @@ private: void getAndDrawComments(); - void updateScrollbar(); - - /* zooming * */ @@ -205,8 +201,6 @@ private: MouseDownData mouseDownData; KeyPressData keyPressData; - - std::vector rankCollapseButtons; }; diff --git a/DRAMSys/traceAnalyzer/presentation/traceplotline.cpp b/DRAMSys/traceAnalyzer/presentation/traceplotline.cpp deleted file mode 100644 index 10834fb9..00000000 --- a/DRAMSys/traceAnalyzer/presentation/traceplotline.cpp +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2021, Technische Universität Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: - * Derek Christ - */ - -#include "traceplotline.h" - - -TracePlotLine::TracePlotLine(const QString &label, const std::shared_ptr> collapsedRanks) : - label(label), - collapsedRanks(collapsedRanks) -{ -} - -TracePlotLine::~TracePlotLine() {} - -const QString & TracePlotLine::getLabel() const -{ - return label; -} - -bool TracePlotLine::isCollapsed() const -{ - return false; -} - -void TracePlotLine::setYVal (int yVal) -{ - this->yVal = yVal; -} - - -int TracePlotLine::getYVal() const -{ - return yVal; -} - - -TracePlotBankLine::TracePlotBankLine(const QString &label, unsigned int rank, - const std::shared_ptr> collapsedRanks) : - TracePlotLine(label, collapsedRanks), - rank(rank) -{ -} - -bool TracePlotBankLine::isCollapsed() const -{ - return (*collapsedRanks)[rank]; -} - - -TracePlotFirstRankLine::TracePlotFirstRankLine(const QString &label, const QString &collapsedLabel, - unsigned int rank, const std::shared_ptr> collapsedRanks) : - TracePlotBankLine(label, rank, collapsedRanks), - collapsedLabel(collapsedLabel) -{ -} - -const QString & TracePlotFirstRankLine::getLabel() const -{ - if (isCollapsed()) - return collapsedLabel; - else - return TracePlotLine::getLabel(); -} diff --git a/DRAMSys/traceAnalyzer/presentation/tracescroller.cpp b/DRAMSys/traceAnalyzer/presentation/tracescroller.cpp index 1090bd45..ae9906a1 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracescroller.cpp +++ b/DRAMSys/traceAnalyzer/presentation/tracescroller.cpp @@ -33,6 +33,7 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #include @@ -61,9 +62,12 @@ void TraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot) this -> navigator = navigator; connectNavigatorQ_SIGNALS(); - setUpAxis(); setUpDrawingProperties(); + setUpAxis(); setUpTracePlotItem(); + + updateAxis(); + getAndDrawComments(); this->tracePlot = tracePlot; @@ -73,6 +77,8 @@ void TraceScroller::init(TraceNavigator *navigator, TracePlot *tracePlot) QObject::connect(tracePlot, SIGNAL(colorGroupingChanged(ColorGrouping)), this, SLOT(colorGroupingChanged(ColorGrouping))); + + QObject::connect(tracePlot, SIGNAL(tracePlotLinesChanged()), this, SLOT(updateAxis())); } @@ -86,26 +92,29 @@ void TraceScroller::setUpTracePlotItem() void TraceScroller::setUpDrawingProperties() { + drawingProperties.init(navigator->getTracePlotLines(), navigator->getTracePlotLineCache()); + drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; drawingProperties.numberOfBankgroups = navigator->GeneralTraceInfo().numberOfBankgroups; drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; drawingProperties.banksPerRank = drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; drawingProperties.groupsPerRank = drawingProperties.numberOfBankgroups / drawingProperties.numberOfRanks; drawingProperties.banksPerGroup = drawingProperties.numberOfBanks / drawingProperties.numberOfBankgroups; - drawingProperties.yValResponse = drawingProperties.numberOfBanks; - drawingProperties.yValRequest = drawingProperties.numberOfBanks + 1; - drawingProperties.yValCommandBus = -3; - drawingProperties.yValDataBus = -4; } void TraceScroller::setUpAxis() { - setAxisScale(yLeft, -1, navigator->GeneralTraceInfo().numberOfBanks + 2, 1.0); axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Labels, false ); axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Ticks, false ); } +void TraceScroller::updateAxis() +{ + setAxisScale(yLeft, -1, drawingProperties.getNumberOfDisplayedLines() + 1, 1.0); + replot(); +} + void TraceScroller::connectNavigatorQ_SIGNALS() { QObject::connect(navigator, SIGNAL(currentTraceTimeChanged()), this, diff --git a/DRAMSys/traceAnalyzer/presentation/tracescroller.h b/DRAMSys/traceAnalyzer/presentation/tracescroller.h index 485af8a6..8a5d8583 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracescroller.h +++ b/DRAMSys/traceAnalyzer/presentation/tracescroller.h @@ -33,6 +33,7 @@ * Janik Schlemminger * Robert Gernhardt * Matthias Jung + * Derek Christ */ #ifndef TRACESCROLLER_H @@ -78,6 +79,9 @@ public Q_SLOTS: void selectedTransactionsChanged(); void colorGroupingChanged(ColorGrouping colorgrouping); +private Q_SLOTS: + void updateAxis(); + }; #endif // TraceScroller_H diff --git a/DRAMSys/traceAnalyzer/presentation/traceselector.cpp b/DRAMSys/traceAnalyzer/presentation/traceselector.cpp new file mode 100644 index 00000000..9ca682fb --- /dev/null +++ b/DRAMSys/traceAnalyzer/presentation/traceselector.cpp @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "traceselector.h" +#include "traceplot.h" + +#include +#include +#include +#include +#include +#include +#include + +QMimeData *TraceAvailableTree::mimeData(const QList items) const +{ + QByteArray traceLineData; + QDataStream dataStream(&traceLineData, QIODevice::WriteOnly); + + for (QTreeWidgetItem *item : items) + { + TraceSelectorTreeItem *treeSelectorItem = static_cast(item); + + dataStream << static_cast(treeSelectorItem->type) + << treeSelectorItem->rank + << treeSelectorItem->bankgroup + << treeSelectorItem->bank; + } + + QMimeData *mimeData = new QMimeData; + mimeData->setData("application/x-tracelinedata", traceLineData); + + return mimeData; +} + +QStringList TraceAvailableTree::mimeTypes() const +{ + QStringList types = QTreeWidget::mimeTypes(); + types << "application/x-tracelinedata"; + + return types; +} + +void TraceAvailableTree::keyPressEvent(QKeyEvent *event) +{ + if(event->key() == Qt::Key_Return) + { + for (unsigned int i = 0; i < topLevelItemCount(); i++) + { + auto currentItem = static_cast(topLevelItem(i)); + + if (currentItem->isSelected()) + { + auto clonedItem = new TraceSelectorTreeItem(*currentItem); + + for (int i = 0; i < currentItem->childCount(); i++) + { + auto child = static_cast(currentItem->child(i)); + clonedItem->addChild(new TraceSelectorTreeItem(*child)); + } + + selectedTree->addTopLevelItem(clonedItem); + } + + // Also add child items that could be selected. + for (unsigned int i = 0; i < currentItem->childCount(); i++) + { + auto currentChildItem = static_cast(currentItem->child(i)); + + if (currentChildItem->isSelected()) + { + auto clonedItem = new TraceSelectorTreeItem(*currentChildItem); + selectedTree->addTopLevelItem(clonedItem); + } + } + } + + Q_EMIT selectedTree->itemsChanged(); + } + + QTreeWidget::keyPressEvent(event); +} + +TraceSelectedTree::TraceSelectedTree(QWidget *parent) : + QTreeWidget(parent) +{ +} + +void TraceSelectedTree::init(unsigned int groupsPerRank, unsigned int banksPerGroup) +{ + this->groupsPerRank = groupsPerRank; + this->banksPerGroup = banksPerGroup; +} + +QMimeData *TraceSelectedTree::mimeData(const QList items) const +{ + QByteArray traceLineData; + QDataStream dataStream(&traceLineData, QIODevice::WriteOnly); + + for (QTreeWidgetItem *item : items) + { + TraceSelectorTreeItem *treeSelectorItem = static_cast(item); + + dataStream << static_cast(treeSelectorItem->type) + << treeSelectorItem->rank + << treeSelectorItem->bankgroup + << treeSelectorItem->bank; + } + + QMimeData *mimeData = new QMimeData; + mimeData->setData("application/x-tracelinedata", traceLineData); + + return mimeData; +} + +QStringList TraceSelectedTree::mimeTypes() const +{ + QStringList types = QTreeWidget::mimeTypes(); + types << "application/x-tracelinedata"; + + return types; +} + +Qt::DropActions TraceSelectedTree::supportedDropActions() const +{ + return (Qt::MoveAction | Qt::CopyAction); +} + +bool TraceSelectedTree::dropMimeData(QTreeWidgetItem *parent, int index, const QMimeData *data, Qt::DropAction action) +{ + bool dropHandled = false; + + if (action == Qt::CopyAction && data->hasFormat("application/x-tracelinedata")) + { + dropHandled = true; + + QByteArray traceLineData = data->data("application/x-tracelinedata"); + QDataStream dataStream(&traceLineData, QIODevice::ReadOnly); + + QList droppedItems; + + while (!dataStream.atEnd()) + { + TraceSelectorTreeItem::Type currentType; + int currentTypeNum; + unsigned int currentRank, currentBankGroup, currentBank; + + dataStream >> currentTypeNum + >> currentRank + >> currentBankGroup + >> currentBank; + + currentType = static_cast(currentTypeNum); + + QTreeWidgetItem *droppedItem; + + switch (currentType) + { + case TraceSelectorTreeItem::Type::RequestLineItem: + case TraceSelectorTreeItem::Type::ResponseLineItem: + case TraceSelectorTreeItem::Type::CommandBusLineItem: + case TraceSelectorTreeItem::Type::DataBusLineItem: + droppedItem = new TraceSelectorTreeItem(currentType); + break; + + case TraceSelectorTreeItem::Type::BankLineItem: + droppedItem = new TraceSelectorTreeItem(currentType, currentRank, currentBankGroup, currentBank); + break; + + case TraceSelectorTreeItem::Type::RankGroupItem: + droppedItem = TraceSelectorTreeItem::createRankParentItem(currentRank, groupsPerRank, banksPerGroup); + break; + } + + droppedItems.append(droppedItem); + } + + insertTopLevelItems(index, droppedItems); + } + else + dropHandled = QTreeWidget::dropMimeData(parent, index, data, action); + + return dropHandled; +} + +void TraceSelectedTree::dropEvent(QDropEvent *event) +{ + if (event->source() == this) + event->setDropAction(Qt::MoveAction); + else + event->setDropAction(Qt::CopyAction); + + QTreeWidget::dropEvent(event); + + Q_EMIT itemsChanged(); +} + +void TraceSelectedTree::keyPressEvent(QKeyEvent *event) +{ + if(event->key() == Qt::Key_Delete) + { + for (unsigned int i = topLevelItemCount(); i--;) + { + if (topLevelItem(i)->isSelected()) + takeTopLevelItem(i); + } + + Q_EMIT itemsChanged(); + } + + QTreeWidget::keyPressEvent(event); +} + +TraceSelector::TraceSelector(QWidget *parent) : + QWidget(parent), layout(new QVBoxLayout(this)), + selectedTree(new TraceSelectedTree(this)), + availableTree(new TraceAvailableTree(selectedTree, this)) +{ + QLabel *descriptionLabel = new QLabel(); + descriptionLabel->setText( + "To customize the displayed rows double click or " + "drag and drop items from the upper list to the lower list." + ); + descriptionLabel->setWordWrap(true); + descriptionLabel->setAlignment(Qt::AlignCenter); + + layout->addWidget(descriptionLabel); + layout->addWidget(availableTree); + layout->addWidget(selectedTree); + + availableTree->setHeaderLabel("Available Items"); + availableTree->setDragEnabled(true); + availableTree->setExpandsOnDoubleClick(false); + availableTree->setSelectionMode(QAbstractItemView::ExtendedSelection); + + selectedTree->setHeaderLabel("Selected Items"); + selectedTree->setDragEnabled(true); + selectedTree->setAcceptDrops(true); + selectedTree->setDropIndicatorShown(true); + selectedTree->setExpandsOnDoubleClick(false); + selectedTree->setSelectionMode(QAbstractItemView::ExtendedSelection); + + connect(selectedTree, &TraceSelectedTree::itemsChanged, this, [=](){ + Q_EMIT selectedTreeChanged(selectedTree); + }); + + connect(availableTree, &QTreeWidget::itemDoubleClicked, this, [=](QTreeWidgetItem *item, int column) { + Q_UNUSED(column) + + auto traceSelectorItem = static_cast(item); + auto clonedItem = new TraceSelectorTreeItem(*traceSelectorItem); + + for (int i = 0; i < traceSelectorItem->childCount(); i++) + { + auto child = static_cast(traceSelectorItem->child(i)); + clonedItem->addChild(new TraceSelectorTreeItem(*child)); + } + + selectedTree->addTopLevelItem(clonedItem); + + Q_EMIT selectedTreeChanged(selectedTree); + }); + + connect(selectedTree, &QTreeWidget::itemDoubleClicked, this, [=](QTreeWidgetItem *item, int column) { + Q_UNUSED(column) + + int index = selectedTree->indexOfTopLevelItem(item); + selectedTree->takeTopLevelItem(index); + + Q_EMIT selectedTreeChanged(selectedTree); + }); +} + +void TraceSelector::init(TracePlot *traceplot) +{ + this->traceplot = traceplot; + numberOfRanks = traceplot->getDrawingProperties().numberOfRanks; + groupsPerRank = traceplot->getDrawingProperties().groupsPerRank; + banksPerGroup = traceplot->getDrawingProperties().banksPerGroup; + selectedTree->init(groupsPerRank, banksPerGroup); + + setUpTreeWidget(availableTree); + + // By default, all available items will also be in the selectedTree. + setUpTreeWidget(selectedTree); + + Q_EMIT selectedTreeChanged(selectedTree); +} + +void TraceSelector::setUpTreeWidget(QTreeWidget *treeWidget) +{ + treeWidget->addTopLevelItem( + new TraceSelectorTreeItem(TraceSelectorTreeItem::Type::RequestLineItem) + ); + + treeWidget->addTopLevelItem( + new TraceSelectorTreeItem(TraceSelectorTreeItem::Type::ResponseLineItem) + ); + + for (unsigned int rank = numberOfRanks; rank--;) + { + TraceSelectorTreeItem *rankItem = + TraceSelectorTreeItem::createRankParentItem(rank, groupsPerRank, banksPerGroup); + + treeWidget->addTopLevelItem(rankItem); + } + + treeWidget->addTopLevelItem( + new TraceSelectorTreeItem(TraceSelectorTreeItem::Type::CommandBusLineItem) + ); + + treeWidget->addTopLevelItem( + new TraceSelectorTreeItem(TraceSelectorTreeItem::Type::DataBusLineItem) + ); +} + +TraceSelectorTreeItem *TraceSelectorTreeItem::createRankParentItem(unsigned int rank,unsigned int groupsPerRank, + unsigned int banksPerGroup) +{ + TraceSelectorTreeItem *rankItem = new TraceSelectorTreeItem(TraceSelectorTreeItem::Type::RankGroupItem, rank); + + for (unsigned int group = groupsPerRank; group--;) + { + for (unsigned int bank = banksPerGroup; bank--;) + { + rankItem->addChild( + new TraceSelectorTreeItem(TraceSelectorTreeItem::Type::BankLineItem, rank, group, bank) + ); + } + } + + return rankItem; +} + +TraceSelectorTreeItem::TraceSelectorTreeItem(TraceSelectorTreeItem::Type type) : + QTreeWidgetItem({getLabel(type)}), type(type) +{ + setFlags(flags() & ~Qt::ItemIsDropEnabled); +} + +TraceSelectorTreeItem::TraceSelectorTreeItem(TraceSelectorTreeItem::Type type, + unsigned int rank) : + QTreeWidgetItem({getLabel(rank)}), type(type), rank(rank) +{ + setFlags(flags() & ~Qt::ItemIsDropEnabled); +} + +TraceSelectorTreeItem::TraceSelectorTreeItem(TraceSelectorTreeItem::Type type, + unsigned int rank, unsigned int bankgroup, unsigned int bank) : + QTreeWidgetItem({getLabel(rank, bankgroup, bank)}), type(type), rank(rank), bankgroup(bankgroup), bank(bank) +{ + setFlags(flags() & ~Qt::ItemIsDropEnabled); +} + +QString TraceSelectorTreeItem::getLabel(Type type) +{ + switch (type) { + case Type::RequestLineItem: + return "REQ"; + case Type::ResponseLineItem: + return "RESP"; + case Type::CommandBusLineItem: + return "Command Bus"; + case Type::DataBusLineItem: + return "Data Bus"; + default: + return ""; + } +} + +QString TraceSelectorTreeItem::getLabel(unsigned int rank) +{ + return "RA" + QString::number(rank); +} + +QString TraceSelectorTreeItem::getLabel(unsigned int rank, unsigned int bankgroup, unsigned int bank) +{ + return "RA" + QString::number(rank) + " BG" + QString::number(bankgroup) + " BA" + QString::number(bank); +} diff --git a/DRAMSys/traceAnalyzer/presentation/traceselector.h b/DRAMSys/traceAnalyzer/presentation/traceselector.h new file mode 100644 index 00000000..7d120da2 --- /dev/null +++ b/DRAMSys/traceAnalyzer/presentation/traceselector.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef TRACESELECTOR_H +#define TRACESELECTOR_H + +#include +#include +#include +#include + +class TracePlot; +class TracePlotLine; +class TraceSelectedTree; +class QVBoxLayout; + +class TraceAvailableTree : public QTreeWidget +{ + Q_OBJECT +public: + explicit TraceAvailableTree(TraceSelectedTree* selectedTree, QWidget *parent = nullptr) : + QTreeWidget(parent), selectedTree(selectedTree) {} + +protected: + void keyPressEvent(QKeyEvent *event) override; + + QMimeData *mimeData(const QList items) const override; + QStringList mimeTypes() const override; + +private: + TraceSelectedTree *selectedTree; +}; + +class TraceSelectedTree : public QTreeWidget +{ + Q_OBJECT +public: + explicit TraceSelectedTree(QWidget *parent = nullptr); + void init(unsigned int groupsPerRank, unsigned int banksPerGroup); + +Q_SIGNALS: + void itemsChanged(); + +protected: + void keyPressEvent(QKeyEvent *event) override; + + void dropEvent(QDropEvent *event) override; + bool dropMimeData(QTreeWidgetItem *parent, int index, const QMimeData *data, Qt::DropAction action) override; + Qt::DropActions supportedDropActions() const override; + QMimeData *mimeData(const QList items) const override; + QStringList mimeTypes() const override; + +private: + unsigned int groupsPerRank; + unsigned int banksPerGroup; +}; + +class TraceSelectorTreeItem : public QTreeWidgetItem +{ +public: + enum class Type { + RequestLineItem, ResponseLineItem, + CommandBusLineItem, DataBusLineItem, + RankGroupItem, BankLineItem + } const type; + + TraceSelectorTreeItem(Type type); + TraceSelectorTreeItem(Type type, unsigned int rank); + TraceSelectorTreeItem(Type type, unsigned int rank, unsigned int bankgroup, unsigned int bank); + + static TraceSelectorTreeItem *createRankParentItem(unsigned int rank, unsigned int groupsPerRank, + unsigned int banksPerGroup); + + static QString getLabel(Type type); + static QString getLabel(unsigned int rank); + static QString getLabel(unsigned int rank, unsigned int bankgroup, unsigned int bank); + + const unsigned int rank = 0, bankgroup = 0, bank = 0; +}; + +class TraceSelector : public QWidget +{ + Q_OBJECT + +public: + explicit TraceSelector(QWidget *parent = nullptr); + void init(TracePlot *traceplot); + +signals: + void selectedTreeChanged(QTreeWidget *treeWidget); + +private: + void setUpTreeWidget(QTreeWidget *treeWidget); + + unsigned int numberOfRanks; + unsigned int groupsPerRank; + unsigned int banksPerGroup; + + TracePlot *traceplot; + QVBoxLayout *layout; + TraceSelectedTree *selectedTree; + TraceAvailableTree *availableTree; +}; + +#endif //TRACESELECTOR_H diff --git a/DRAMSys/traceAnalyzer/presentation/util/clkgrid.cpp b/DRAMSys/traceAnalyzer/presentation/util/clkgrid.cpp index f4bb4af8..81b12f58 100644 --- a/DRAMSys/traceAnalyzer/presentation/util/clkgrid.cpp +++ b/DRAMSys/traceAnalyzer/presentation/util/clkgrid.cpp @@ -36,6 +36,8 @@ */ #include "clkgrid.h" +#include +#include #include using namespace std; diff --git a/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.cpp b/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.cpp index 3d31e243..0129c5b4 100644 --- a/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.cpp +++ b/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.cpp @@ -42,8 +42,13 @@ QwtText CustomLabelScaleDraw::label(double v) const return QwtText((*labels)[static_cast(v)]); } -void CustomLabelScaleDraw::drawLabel(QPainter *painter, double value) const +void CustomLabelScaleDraw::draw(QPainter *painter, const QPalette &palette) const { emit scaleRedraw(); - QwtScaleDraw::drawLabel(painter, value); + QwtScaleDraw::draw(painter, palette); +} + +void CustomLabelScaleDraw::clearCache() +{ + invalidateCache(); } diff --git a/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.h b/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.h index 3218a21a..31745754 100644 --- a/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.h +++ b/DRAMSys/traceAnalyzer/presentation/util/customlabelscaledraw.h @@ -40,6 +40,7 @@ #define CUSTOMLABELSCALEDRAW_H #include #include +#include #include #include @@ -56,7 +57,8 @@ public: virtual QwtText label(double v) const override; - void drawLabel(QPainter *painter, double value) const override; + void draw(QPainter *painter, const QPalette &palette) const override; + void clearCache(); Q_SIGNALS: void scaleRedraw() const; diff --git a/DRAMSys/traceAnalyzer/presentation/util/engineeringScaleDraw.h b/DRAMSys/traceAnalyzer/presentation/util/engineeringScaleDraw.h index 45f8fb59..6d5503bc 100644 --- a/DRAMSys/traceAnalyzer/presentation/util/engineeringScaleDraw.h +++ b/DRAMSys/traceAnalyzer/presentation/util/engineeringScaleDraw.h @@ -38,6 +38,7 @@ #ifndef ENGINEERINGSCALEDRAW_H #define ENGINEERINGSCALEDRAW_H #include +#include #include #include "businessObjects/tracetime.h" diff --git a/DRAMSys/traceAnalyzer/presentation/util/traceplotline.cpp b/DRAMSys/traceAnalyzer/presentation/util/traceplotline.cpp new file mode 100644 index 00000000..dd9dfba2 --- /dev/null +++ b/DRAMSys/traceAnalyzer/presentation/util/traceplotline.cpp @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: + * Derek Christ + */ + +#include "traceplotline.h" +#include "../traceplot.h" + +#include +#include + +TracePlotLine::TracePlotLine(QString label) : + label(label) +{ +} + +TracePlotLine::TracePlotLine() +{ +} + +TracePlotLine::~TracePlotLine() {} + +QString TracePlotLine::getLabel() const +{ + return label; +} + +bool TracePlotLine::isCollapsed() const +{ + return false; +} + +void TracePlotLine::setYVal (int yVal) +{ + this->yVal = yVal; +} + +int TracePlotLine::getYVal() const +{ + return yVal; +} + + +TracePlotBankLine::TracePlotBankLine(unsigned int rank, unsigned int group, unsigned int bank, + std::shared_ptr firstRankLine) : + TracePlotBankLine(rank, group, bank) +{ + this->firstRankLine = firstRankLine; +} + +TracePlotBankLine::TracePlotBankLine(unsigned int rank, unsigned int group, unsigned int bank) : + rank(rank), group(group), bank(bank) +{ + QString rankLabel = QString("RA") + QString::number(rank); + QString bankGroupLabel = QString("BG") + QString::number(group); + QString bankLabel = QString("BA") + QString::number(bank); + + label = rankLabel + QString(" ") + bankGroupLabel + QString(" ") + bankLabel; +} + +bool TracePlotBankLine::isCollapsed() const +{ + if (!firstRankLine.lock()) + return false; + + return firstRankLine.lock()->isCollapsed(); +} + + +TracePlotFirstRankLine::TracePlotFirstRankLine(unsigned int rank, unsigned int group, unsigned int bank, + TracePlot *tracePlot) : + TracePlotBankLine(rank, group, bank), + collapseButton(new QPushButton(tracePlot)), tracePlot(tracePlot) +{ + collapsedLabel = QString("RA") + QString::number(rank); + + collapseButton->setText(collapsed ? "+" : "-"); + collapseButton->show(); + + QObject::connect(collapseButton, &QPushButton::pressed, this, [=](){ + collapsed = !collapsed; + collapseButton->setText(collapsed ? "+" : "-"); + Q_EMIT collapsedStateChanged(); + }); +} + +TracePlotFirstRankLine::~TracePlotFirstRankLine() +{ + // Delete the collapseButton because its parent will still exist. + collapseButton->deleteLater(); +} + +void TracePlotFirstRankLine::updateButtonPosition() +{ + QPointF point = tracePlot->axisScaleDraw(QwtPlot::yLeft)->labelPosition(getYVal()); + collapseButton->setGeometry(point.x(), point.y() - 4, 25, 25); +} + +bool TracePlotFirstRankLine::isCollapsed() const +{ + return collapsed; +} + +QString TracePlotFirstRankLine::getLabel() const +{ + if (collapsed) + return collapsedLabel; + else + return TracePlotLine::getLabel(); +} + +QString TracePlotFirstRankLine::getFullLabel() const +{ + return TracePlotLine::getLabel(); +} diff --git a/DRAMSys/traceAnalyzer/presentation/traceplotline.h b/DRAMSys/traceAnalyzer/presentation/util/traceplotline.h similarity index 64% rename from DRAMSys/traceAnalyzer/presentation/traceplotline.h rename to DRAMSys/traceAnalyzer/presentation/util/traceplotline.h index be93d6b4..2d947f76 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplotline.h +++ b/DRAMSys/traceAnalyzer/presentation/util/traceplotline.h @@ -36,81 +36,122 @@ #ifndef TRACELOTLINE_H #define TRACELOTLINE_H +#include #include #include #include -class TracePlotLine +class QPushButton; +class TracePlot; +class TracePlotFirstRankLine; + +class TracePlotLine : public QObject { + Q_OBJECT + public: - TracePlotLine(const QString &label, const std::shared_ptr> collapsedRanks); + TracePlotLine(QString label); virtual ~TracePlotLine() = 0; - virtual const QString & getLabel() const; + virtual QString getLabel() const; virtual bool isCollapsed() const; void setYVal(int yVal); int getYVal() const; protected: + TracePlotLine(); + QString label; int yVal; - const std::shared_ptr> collapsedRanks; }; - class TracePlotBankLine : public TracePlotLine { + Q_OBJECT + public: - TracePlotBankLine(const QString &label, unsigned int rank, const std::shared_ptr> collapsedRanks); + TracePlotBankLine(unsigned int rank, unsigned int group, unsigned int bank, + std::shared_ptr firstRankLine); + + TracePlotBankLine(unsigned int rank, unsigned int group, unsigned int bank); ~TracePlotBankLine() = default; - void setCollapsed(bool value); - bool isCollapsed() const override; + + virtual bool isCollapsed() const override; + std::shared_ptr getFirstRankLine() const { + return firstRankLine.lock(); + } const unsigned int rank; + const unsigned int group; + const unsigned int bank; + +private: + std::weak_ptr firstRankLine; }; class TracePlotFirstRankLine final : public TracePlotBankLine { + Q_OBJECT + public: - TracePlotFirstRankLine(const QString &label, const QString &collapsedLabel, - unsigned int rank, const std::shared_ptr> collapsedRanks); + TracePlotFirstRankLine(unsigned int rank, unsigned int group, unsigned int bank, + TracePlot *tracePlot); - ~TracePlotFirstRankLine() = default; + ~TracePlotFirstRankLine(); - const QString & getLabel() const override; + bool isCollapsed() const override; + QString getLabel() const override; + QString getFullLabel() const; + +public Q_SLOTS: + void updateButtonPosition(); + +Q_SIGNALS: + void collapsedStateChanged(); private: QString collapsedLabel; + QPushButton *collapseButton; + bool collapsed = false; + TracePlot *tracePlot; }; class TracePlotRequestLine final : public TracePlotLine { + Q_OBJECT + public: - using TracePlotLine::TracePlotLine; + TracePlotRequestLine() : TracePlotLine("REQ") {} ~TracePlotRequestLine() = default; }; class TracePlotResponseLine final : public TracePlotLine { + Q_OBJECT + public: - using TracePlotLine::TracePlotLine; + TracePlotResponseLine() : TracePlotLine("RESP") {} ~TracePlotResponseLine() = default; }; class TracePlotDataBusLine final : public TracePlotLine { + Q_OBJECT + public: - using TracePlotLine::TracePlotLine; + TracePlotDataBusLine() : TracePlotLine("Data Bus") {} ~TracePlotDataBusLine() = default; }; class TracePlotCommandBusLine final : public TracePlotLine { + Q_OBJECT + public: - using TracePlotLine::TracePlotLine; + TracePlotCommandBusLine() : TracePlotLine("Command Bus") {} ~TracePlotCommandBusLine() = default; }; diff --git a/DRAMSys/traceAnalyzer/presentation/util/traceplotlinecache.cpp b/DRAMSys/traceAnalyzer/presentation/util/traceplotlinecache.cpp new file mode 100644 index 00000000..09c1d790 --- /dev/null +++ b/DRAMSys/traceAnalyzer/presentation/util/traceplotlinecache.cpp @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: + * Derek Christ + */ + +#include "traceplotlinecache.h" +#include "../tracedrawingproperties.h" +#include "traceplotline.h" + +TracePlotLineCache::TracePlotLineCache(std::shared_ptr tracePlotLines, unsigned int numberOfRanks, + unsigned int groupsPerRank, unsigned int banksPerGroup) : + tracePlotLines(tracePlotLines), numberOfRanks(numberOfRanks), + groupsPerRank(groupsPerRank), banksPerGroup(banksPerGroup) +{ +} + +void TracePlotLineCache::clearCache() const +{ + bankLinesCache.clear(); + bankLinesFromGroupCache.clear(); + bankLinesFromRankCache.clear(); + firstRankLinesCache.clear(); + requestLinesCache.clear(); + responseLinesCache.clear(); + commandBusLinesCache.clear(); + dataBusLinesCache.clear(); +} + +TracePlotLineVector TracePlotLineCache::getCommandBusLines() const +{ + if (commandBusLinesCache.size() != 0) + return commandBusLinesCache; + + std::vector> commandBusLines; + for (auto line : *tracePlotLines) + { + auto commandBusLine = std::dynamic_pointer_cast(line); + if (commandBusLine) + commandBusLines.push_back(commandBusLine); + } + + commandBusLinesCache = commandBusLines; + + return commandBusLines; +} + +TracePlotLineVector TracePlotLineCache::getDataBusLines() const +{ + if (dataBusLinesCache.size() != 0) + return dataBusLinesCache; + + std::vector> dataBusLines; + for (auto line : *tracePlotLines) + { + auto dataBusLine = std::dynamic_pointer_cast(line); + if (dataBusLine) + dataBusLines.push_back(dataBusLine); + } + + dataBusLinesCache = dataBusLines; + + return dataBusLines; +} + +TracePlotLineVector TracePlotLineCache::getRequestLines() const +{ + if (requestLinesCache.size() != 0) + return requestLinesCache; + + std::vector> requestLines; + for (auto line : *tracePlotLines) + { + auto requestLine = std::dynamic_pointer_cast(line); + if (requestLine) + requestLines.push_back(requestLine); + } + + requestLinesCache = requestLines; + + return requestLines; +} + +TracePlotLineVector TracePlotLineCache::getResponseLines() const +{ + if (responseLinesCache.size() != 0) + return responseLinesCache; + + std::vector> responseLines; + for (auto line : *tracePlotLines) + { + auto responseLine = std::dynamic_pointer_cast(line); + if (responseLine) + responseLines.push_back(responseLine); + } + + responseLinesCache = responseLines; + + return responseLines; +} + +TracePlotLineVector TracePlotLineCache::getFirstRankLines(unsigned int rank) const +{ + Q_ASSERT(rank <= numberOfRanks - 1); + + if (firstRankLinesCache.find(rank) != firstRankLinesCache.end()) + return firstRankLinesCache[rank]; + + std::vector> firstRankLines; + + for (auto line : *tracePlotLines) + { + auto firstRankLine = std::dynamic_pointer_cast(line); + if (firstRankLine && firstRankLine->rank == rank) + firstRankLines.push_back(firstRankLine); + } + + firstRankLinesCache[rank] = firstRankLines; + + return firstRankLines; +} + +TracePlotLineVector TracePlotLineCache::getBankLinesFromRank(unsigned int rank) const +{ + Q_ASSERT(rank <= numberOfRanks - 1); + + if (bankLinesFromRankCache.find(rank) != bankLinesFromRankCache.end()) + return bankLinesFromRankCache[rank]; + + std::vector> bankLines; + for (auto line : *tracePlotLines) + { + auto bankLine = std::dynamic_pointer_cast(line); + + if (bankLine && bankLine->rank == rank) + bankLines.push_back(bankLine); + } + + bankLinesFromRankCache[rank] = bankLines; + + return bankLines; +} + +TracePlotLineVector TracePlotLineCache::getBankLinesFromGroup(unsigned int rank, unsigned int group) const +{ + Q_ASSERT(rank <= numberOfRanks - 1); + Q_ASSERT(group <= groupsPerRank - 1); + + std::tuple bankLinesTuple {rank, group}; + + if (bankLinesFromGroupCache.find(bankLinesTuple) != bankLinesFromGroupCache.end()) + return bankLinesFromGroupCache[bankLinesTuple]; + + std::vector> bankLines; + + for (auto line : *tracePlotLines) + { + auto bankLine = std::dynamic_pointer_cast(line); + + if (bankLine && bankLine->rank == rank && bankLine->group == group) + bankLines.push_back(bankLine); + } + + bankLinesFromGroupCache[bankLinesTuple] = bankLines; + + return bankLines; +} + +TracePlotLineVector TracePlotLineCache::getBankLines(unsigned int rank, unsigned int group, + unsigned int bank) const +{ + Q_ASSERT(rank <= numberOfRanks - 1); + Q_ASSERT(group <= groupsPerRank - 1); + Q_ASSERT(bank <= banksPerGroup - 1); + + std::tuple bankLinesTuple {rank, group, bank}; + + if (bankLinesCache.find(bankLinesTuple) != bankLinesCache.end()) + return bankLinesCache[bankLinesTuple]; + + std::vector> bankLines; + + for (auto line : *tracePlotLines) + { + auto bankLine = std::dynamic_pointer_cast(line); + + if (bankLine && bankLine->rank == rank && bankLine->group == group && bankLine->bank == bank) + bankLines.push_back(bankLine); + } + + bankLinesCache[bankLinesTuple] = bankLines; + + return bankLines; +} diff --git a/DRAMSys/traceAnalyzer/presentation/util/traceplotlinecache.h b/DRAMSys/traceAnalyzer/presentation/util/traceplotlinecache.h new file mode 100644 index 00000000..e7b8d833 --- /dev/null +++ b/DRAMSys/traceAnalyzer/presentation/util/traceplotlinecache.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: + * Derek Christ + */ + +#ifndef TRACELOTLINECACHE_H +#define TRACELOTLINECACHE_H + +#include +#include +#include + +class TracePlotLine; + +using TracePlotLineVector = std::vector>; + +struct TracePlotLineCache +{ + TracePlotLineCache(std::shared_ptr tracePlotLines, unsigned int numberOfRanks, + unsigned int groupsPerRank, unsigned int banksPerGroup); + + TracePlotLineVector getRequestLines() const; + TracePlotLineVector getResponseLines() const; + TracePlotLineVector getCommandBusLines() const; + TracePlotLineVector getDataBusLines() const; + TracePlotLineVector getFirstRankLines(unsigned int rank) const; + TracePlotLineVector getBankLines(unsigned int rank, unsigned int group, unsigned int bank) const; + TracePlotLineVector getBankLinesFromGroup(unsigned int rank, unsigned int group) const; + TracePlotLineVector getBankLinesFromRank(unsigned int rank) const; + + void clearCache() const; + +private: + std::shared_ptr tracePlotLines; + + unsigned int numberOfRanks; + unsigned int groupsPerRank; + unsigned int banksPerGroup; + + mutable std::map, std::vector>> bankLinesCache; + mutable std::map, std::vector>> bankLinesFromGroupCache; + mutable std::map>> bankLinesFromRankCache; + mutable std::map>> firstRankLinesCache; + mutable std::vector> requestLinesCache; + mutable std::vector> responseLinesCache; + mutable std::vector> commandBusLinesCache; + mutable std::vector> dataBusLinesCache; +}; + +#endif // TRACELOTLINECACHE_H diff --git a/DRAMSys/traceAnalyzer/tracefiletab.cpp b/DRAMSys/traceAnalyzer/tracefiletab.cpp index f7c9be1e..842c1760 100644 --- a/DRAMSys/traceAnalyzer/tracefiletab.cpp +++ b/DRAMSys/traceAnalyzer/tracefiletab.cpp @@ -48,6 +48,8 @@ #include #include #include +#include +#include #include "qwt_plot_histogram.h" #include "qwt_plot_curve.h" #include "qwt_plot_layout.h" @@ -56,6 +58,7 @@ #include "qwt_legend.h" #include "qwt_plot_magnifier.h" #include "qwt_plot_panner.h" +#include "presentation/traceselector.h" #include @@ -71,6 +74,7 @@ TraceFileTab::TraceFileTab(QWidget *parent, const QString &path) : initNavigatorAndItsDependentWidgets(path); setUpFileWatcher(path); setUpTraceplotScrollbar(); + setUpTraceSelector(); ui->fileDescriptionEdit->setPlainText( navigator->GeneralTraceInfo().description); @@ -138,6 +142,14 @@ void TraceFileTab::setUpFileWatcher(QString path) SLOT(tracefileChanged())); } +void TraceFileTab::setUpTraceSelector() +{ + TraceSelector *selector = ui->tabCustomizePlot; + connect(selector, &TraceSelector::selectedTreeChanged, + ui->traceplot, &TracePlot::updateTracePlotLines); + selector->init(ui->traceplot); +} + void TraceFileTab::tracefileChanged() { if (savingChangesToDB == true) { diff --git a/DRAMSys/traceAnalyzer/tracefiletab.h b/DRAMSys/traceAnalyzer/tracefiletab.h index 9316f66e..25fa915c 100644 --- a/DRAMSys/traceAnalyzer/tracefiletab.h +++ b/DRAMSys/traceAnalyzer/tracefiletab.h @@ -60,6 +60,7 @@ public: void setUpFileWatcher(QString filename); void setUpTraceplotScrollbar(); + void setUpTraceSelector(); void initNavigatorAndItsDependentWidgets(QString path); QString getPathToTraceFile() { diff --git a/DRAMSys/traceAnalyzer/tracefiletab.ui b/DRAMSys/traceAnalyzer/tracefiletab.ui index c3a29753..cd45bbef 100644 --- a/DRAMSys/traceAnalyzer/tracefiletab.ui +++ b/DRAMSys/traceAnalyzer/tracefiletab.ui @@ -120,6 +120,11 @@ 0 + + + Customize Plot + + Selected Transaction @@ -374,6 +379,12 @@ QTreeWidget
presentation/selectedtransactiontreewidget.h
+ + TraceSelector + QWidget +
presentation/traceselector.h
+ 1 + diff --git a/DRAMSys/unitTests/main.cpp b/DRAMSys/unitTests/main.cpp index 6912b12c..42f2dbbe 100644 --- a/DRAMSys/unitTests/main.cpp +++ b/DRAMSys/unitTests/main.cpp @@ -34,7 +34,7 @@ */ #include -#include +#include #include "Testfile.h" int sc_main(int argc, char **argv)