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Lukas Steiner
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14
DRAMSys/gem5/README.md
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@@ -4,7 +4,7 @@ Install gem5 by following the instructions on the [gem5 wiki](http://gem5.org/Do
Optionally, use the scripts from [gem5.TnT] to install gem5, build it, get some benchmark programs and learn more about gem5. Optionally, use the scripts from [gem5.TnT] to install gem5, build it, get some benchmark programs and learn more about gem5.
In order to understand the SystemC coupling with gem5 it is recommended to In order to understand the SystemC coupling with gem5 it is recommended to
read the documentation in the gem5 repository *util/tlm/README* and [12]. read the documentation in the gem5 repository *util/tlm/README* and [1].
The main steps for building gem5 and libgem5 follow: The main steps for building gem5 and libgem5 follow:
@@ -393,7 +393,7 @@ Wait some minutes for the Linux boot process to complete then login. Username is
### DRAMSys with gem5 Elastic Traces ### DRAMSys with gem5 Elastic Traces
For understanding elastic traces and their generation, study the [gem5 For understanding elastic traces and their generation, study the [gem5
wiki](http://gem5.org/TraceCPU) and the paper [13]. wiki](http://gem5.org/TraceCPU) and the paper [2].
Some predefined configs are stored [here](DRAMSys/gem5/configs) and the related Some predefined configs are stored [here](DRAMSys/gem5/configs) and the related
python files are stored [here](DRAMSys/gem5/examples). python files are stored [here](DRAMSys/gem5/examples).
@@ -670,6 +670,16 @@ Note: the port may vary, gem5 prints it during initialization. Example:
system.terminal: Listening for connections on port 3456 system.terminal: Listening for connections on port 3456
``` ```
[1] System Simulation with gem5 and SystemC: The Keystone for Full
Interoperability C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International
Conference on Embedded Computer Systems Architectures Modeling and Simulation
(SAMOS), July, 2017, Samos Island, Greece.
[2] Exploring System Performance using Elastic Traces: Fast, Accurate and
Portable Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung
and Norbert Wehn, IEEE International Conference on Embedded Computer Systems
Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece.
[gem5.TnT]: https://github.com/tukl-msd/gem5.TnT [gem5.TnT]: https://github.com/tukl-msd/gem5.TnT
[gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh [gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh
[gem5ilva_fs.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva_fs.sh [gem5ilva_fs.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva_fs.sh

56
README.md
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@@ -1,20 +1,19 @@
DRAMSys4.0 DRAMSys4.0
=========== ===========
**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework that consists of models reflecting the DRAM functionality, power consumption, temperature behavior and retention time errors. **DRAMSys4.0** [1] [2] [3] is a flexible DRAM subsystem design space exploration framework that consists of models reflecting the DRAM functionality, power consumption, temperature behavior and retention time errors.
Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
[![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) [![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
## Basic Setup ## Basic Setup
Start using DRAMSys by cloning the repository. Start using DRAMSys by cloning the repository.
Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower** [2], **SystemC** and **nlohmann json**. Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower** [4], **SystemC** and **nlohmann json**.
### Dependencies ### Dependencies
DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version you have to export the environment variables *SYSTEMC_HOME* (SystemC root directory), *SYSTEMC_TARGET_ARCH* (e.g. linux64) and add the path of the library to *LD_LIBRARY_PATH*. DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version you have to export the environment variables `SYSTEMC_HOME` (SystemC root directory), `SYSTEMC_TARGET_ARCH` (e.g. linux64) and add the path of the library to `LD_LIBRARY_PATH`.
### Building DRAMSys ### Building DRAMSys
DRAMSys uses CMake for the build process, the minimum required version is **CMake 3.10**. DRAMSys uses CMake for the build process, the minimum required version is **CMake 3.10**.
@@ -486,47 +485,18 @@ $ ./DRAMSys ../../DRAMSys/library/resources/simulations/wideio-thermal.json
[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration [1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin. M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
[2] DRAMPower: Open-source DRAM Power & Energy Estimation Tool [2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
[3] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece.
[4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
K. Chandrasekar, C. Weis, Y. Li, S. Goossens, M. Jung, O. Naji, B. Akesson, N. Wehn, K. Goossens
URL: http://www.drampower.info URL: http://www.drampower.info
[3] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
[4] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
M. Jung, C. Weis, N. Wehn. Accepted for publication, IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs [5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico. M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs [6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. Accepted for publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France
[7] http://www.uni-kl.de/3d-dram/publications/
[8] A Sridhar, A Vincenzi, D Atienza, T Brunschwiler, 3D-ICE: a compact
thermal model for early-stage design of liquid-cooled ICs, IEEE Transactions
on Computers (TC 2013, accepted for publication).
[9] A Sridhar, A Vincenzi, M Ruggiero, T Brunschwiler, D Atienza, 3D-ICE: Fast
compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling,
Proceedings of the 2010 International Conference on Computer-Aided Design
(ICCAD 2010), San Jose, CA, USA, November 7-11 2010.
[10] A Sridhar, A Vincenzi, M Ruggiero, T Brunschwiler, D Atienza, Compact
transient thermal model for 3D ICs with liquid cooling via enhanced heat
transfer cavity geometries, Proceedings of the 16th International Workshop on
Thermal Investigations of ICs and Systems (THERMINIC'10), Barcelona, Spain,
6-8 October, 2010.
[11] http://esl.epfl.ch/3D-ICE
[12] System Simulation with gem5 and SystemC: The Keystone for Full
Interoperability C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International
Conference on Embedded Computer Systems Architectures Modeling and Simulation
(SAMOS), July, 2017, Samos Island, Greece.
[13] Exploring System Performance using Elastic Traces: Fast, Accurate and
Portable Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung
and Norbert Wehn, IEEE International Conference on Embedded Computer Systems
Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece.