From 3b7d4bf601e0de9d072d6f4a3893256124a284ef Mon Sep 17 00:00:00 2001 From: Iron Prando da Silva Date: Thu, 12 May 2022 11:32:27 +0200 Subject: [PATCH] Added burst length filter for DDR5 dependencies. --- .../common/timedependency.h | 4 +- .../specialized/DDR5Configuration.cpp | 2 +- .../dbEntries/dbphaseentryBase.h | 4 +- .../specialized/DDR3dbphaseentry.cpp | 2 +- .../dbEntries/specialized/DDR3dbphaseentry.h | 2 +- .../specialized/DDR4dbphaseentry.cpp | 2 +- .../dbEntries/specialized/DDR4dbphaseentry.h | 2 +- .../specialized/DDR5dbphaseentry.cpp | 6 +- .../dbEntries/specialized/DDR5dbphaseentry.h | 3 +- .../specialized/HBM2dbphaseentry.cpp | 2 +- .../dbEntries/specialized/HBM2dbphaseentry.h | 2 +- .../specialized/LPDDR4dbphaseentry.cpp | 2 +- .../specialized/LPDDR4dbphaseentry.h | 2 +- .../specialized/LPDDR5dbphaseentry.cpp | 4 +- .../specialized/LPDDR5dbphaseentry.h | 2 +- .../specialized/TimeDependenciesInfoDDR5.cpp | 322 +++++++++--------- .../specialized/TimeDependenciesInfoDDR5.h | 1 + .../TimeDependenciesInfoLPDDR5.cpp | 4 +- 18 files changed, 193 insertions(+), 175 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h index b1c686fe..708f737f 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h @@ -40,9 +40,9 @@ #include "StringMapper.h" class DBPhaseEntryBase; -typedef bool (*PassFunction)(const DBPhaseEntryBase* thisPhase, const std::shared_ptr& otherPhase); +#define PASSFUNCTIONDECL (const std::shared_ptr thisPhase, const std::shared_ptr otherPhase) +typedef bool (*PassFunction)PASSFUNCTIONDECL; -#define PASSFUNCTIONDECL [](const DBPhaseEntryBase* thisPhase, const std::shared_ptr& otherPhase) class TimeDependency { public: diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp index 6dc968e1..29710b86 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp @@ -42,7 +42,7 @@ DDR5Configuration::DDR5Configuration(const TraceDB& tdb) { } QString DDR5Configuration::getQueryStr(const std::vector& commands) const { - QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank " + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank, Transactions.BurstLength " " FROM Phases " " INNER JOIN Transactions " " ON Phases.Transact=Transactions.ID " diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h index 81f82a22..f96997e6 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h @@ -40,12 +40,12 @@ #include "businessObjects/phases/phasedependency.h" #include "businessObjects/dramTimeDependencies/common/common.h" -class DBPhaseEntryBase { +class DBPhaseEntryBase : public std::enable_shared_from_this{ public: DBPhaseEntryBase() = default; virtual ~DBPhaseEntryBase() = default; - virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { return false; } + virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { return false; } size_t id; StringMapper phaseName; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp index 7aedb3f7..a08356ef 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp @@ -45,7 +45,7 @@ DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(6).toLongLong(); } -bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h index 44c76547..d2e3e256 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h @@ -43,5 +43,5 @@ class DDR3DBPhaseEntry : public DBPhaseEntryBase { size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp index ce79d097..2f1d7630 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp @@ -46,7 +46,7 @@ DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(7).toLongLong(); } -bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h index ddf19e90..1adaecbf 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h @@ -44,5 +44,5 @@ class DDR4DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp index adeee0d8..10c3c517 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp @@ -44,12 +44,16 @@ DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) { tBank = query.value(5).toLongLong(); tBankgroup = query.value(6).toLongLong(); tRank = query.value(7).toLongLong(); + tBurstLength = query.value(8).toLongLong(); + } -bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; + if (dep.passFunction && !dep.passFunction(shared_from_this(), other)) return false; + bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; bool const skipOnIntraBankAndDifferentBanks = { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h index cf94e903..14be429d 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h @@ -44,10 +44,11 @@ class DDR5DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tBankInGroup; size_t tRank; + size_t tBurstLength; size_t tLogicalRank; size_t tPhysicalRank; size_t tDIMMRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp index 6403f9bf..79c30240 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp @@ -46,7 +46,7 @@ HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(7).toLongLong(); } -bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h index 476f9e99..34dc25bb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h @@ -44,5 +44,5 @@ class HBM2DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp index 93e46fcf..d5f9bdef 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp @@ -45,7 +45,7 @@ LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(6).toLongLong(); } -bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h index f3faad70..2d2aa9ee 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h @@ -44,5 +44,5 @@ class LPDDR4DBPhaseEntry : public DBPhaseEntryBase { size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp index 9543681b..62ec2975 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp @@ -47,11 +47,11 @@ LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) { tBurstLength = query.value(8).toLongLong(); } -bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; - if (dep.passFunction && !dep.passFunction(this, other)) return false; + if (dep.passFunction && !dep.passFunction(shared_from_this(), other)) return false; bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h index 4019ee03..c7c4bc90 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h @@ -46,5 +46,5 @@ class LPDDR5DBPhaseEntry : public DBPhaseEntryBase { size_t tBurstLength; size_t bankOffsetREFP2B; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp index c36b40b5..11b62f2b 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -236,6 +236,17 @@ const std::vector TimeDependenciesInfoDDR5::getPossiblePhases() { DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { DependencyMap dmap; + auto passBurstLength16 = [] PASSFUNCTIONDECL { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + return other->tBurstLength == 16; + }; + auto passBurstLength32 = [] PASSFUNCTIONDECL { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + return other->tBurstLength == 32; + }; + dmap.emplace( piecewise_construct, forward_as_tuple("ACT"), @@ -246,8 +257,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"}, {tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"}, {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, - {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, - {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"}, + {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT", passBurstLength16}, + {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16", passBurstLength32}, {tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"}, {tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"}, @@ -274,40 +285,40 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, - {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, - {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -319,43 +330,44 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, - {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, - {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16}, + {tCCD_L_WR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32}, {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, - {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, - {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"}, + {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16}, + {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32}, {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, + {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -368,8 +380,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"}, @@ -386,42 +398,42 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, - {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA"}, - {tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16"}, - {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, - {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, + {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA", passBurstLength16}, + {tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -433,43 +445,43 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, - {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, + {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, - {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, - {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"}, + {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16}, + {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32}, {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, + {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -482,8 +494,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, - {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"}, - {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"}, + {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16}, + {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -504,8 +516,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, - {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"}, - {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"}, + {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16}, + {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -527,8 +539,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"}, {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK"}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16"}, + {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK", passBurstLength16}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"}, {tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -556,8 +568,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"}, {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"}, + {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK", passBurstLength16}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"}, {tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -585,10 +597,10 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"}, {tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"}, {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32}, + {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, @@ -604,10 +616,10 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"}, {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"}, {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32}, + {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h index f17513ab..69f1d73a 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h @@ -36,6 +36,7 @@ #pragma once #include "../dramtimedependenciesbase.h" +#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h" class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { public: diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp index b1d081fb..98fef2dd 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp @@ -142,12 +142,12 @@ const std::vector TimeDependenciesInfoLPDDR5::getPossiblePhases() { DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { DependencyMap dmap; - auto passBurstLength16 = PASSFUNCTIONDECL { + auto passBurstLength16 = [] PASSFUNCTIONDECL { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; return other->tBurstLength == 16; }; - auto passBurstLength32 = PASSFUNCTIONDECL { + auto passBurstLength32 = [] PASSFUNCTIONDECL { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; return other->tBurstLength == 32;