From 85e0e2a43f3f8803d19ea476f385cba9d4ce908b Mon Sep 17 00:00:00 2001 From: "Felipe S. Prado" Date: Fri, 14 Oct 2016 17:10:56 +0200 Subject: [PATCH 1/2] PDNP-SREF Transition --- DRAMSys/analyzer/scripts/tests.py | 4 ++-- .../src/controller/core/ControllerCore.cpp | 14 +++++++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/DRAMSys/analyzer/scripts/tests.py b/DRAMSys/analyzer/scripts/tests.py index 7823da5a..a7e26334 100755 --- a/DRAMSys/analyzer/scripts/tests.py +++ b/DRAMSys/analyzer/scripts/tests.py @@ -259,7 +259,7 @@ def phase_transitions_are_valid(connection): validTransitions['REFB'] = set(['ACT', 'REFB', 'PDNPB', 'SREFB']) validTransitions['PDNAB'] = set(['PRE', 'RD', 'RDA', 'WR', 'WRA', 'REFB']) - validTransitions['PDNPB'] = set(['ACT', 'REFB']) + validTransitions['PDNPB'] = set(['ACT', 'REFB', 'SREFB']) validTransitions['SREFB'] = set(['ACT']) else: validTransitions['PRE'] = set(['ACT', 'PRE_ALL']) @@ -274,7 +274,7 @@ def phase_transitions_are_valid(connection): validTransitions['REFA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) validTransitions['PDNA'] = set(['PRE', 'PRE_ALL', 'ACT', 'RD', 'RDA', 'WR', 'WRA', 'REFA', 'PDNA', 'PDNP']) - validTransitions['PDNP'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) + validTransitions['PDNP'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) validTransitions['SREF'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) if (dramconfig.bankwiseLogic == "1"): diff --git a/DRAMSys/simulator/src/controller/core/ControllerCore.cpp b/DRAMSys/simulator/src/controller/core/ControllerCore.cpp index 57233afd..8de6d3f5 100644 --- a/DRAMSys/simulator/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/simulator/src/controller/core/ControllerCore.cpp @@ -134,11 +134,19 @@ void ControllerCore::triggerRefresh(tlm::tlm_generic_payload& payload) state->cleanUp(time); - if (!refreshManager->isInvalidated(payload, time) && !powerDownManager->isInSelfRefresh(bank)) - { + if (!refreshManager->isInvalidated(payload, time) && !powerDownManager->isInSelfRefresh(bank)) { printDebugMessage("Triggering refresh on bank " + to_string(bank.ID())); powerDownManager->wakeUpForRefresh(bank, time); //expects PDNA and PDNP to exit without delay - refreshManager->scheduleRefresh(payload, time); + bool pdnpToSrefTransition = false; + if (config.PowerDownMode == EPowerDownMode::Staggered) { + pdnpToSrefTransition = state->getLastCommand(Command::PDNPX,bank).getStart() >= time; + } + if (pdnpToSrefTransition) { + powerDownManager->sleep(bank,time); + } + else { + refreshManager->scheduleRefresh(payload, time); + } } } } From a8bd6eaecd6e01d0c8fd33ba8523566c88577784 Mon Sep 17 00:00:00 2001 From: sprado Date: Mon, 17 Oct 2016 23:50:21 +0200 Subject: [PATCH 2/2] Update ControllerCore.cpp --- DRAMSys/simulator/src/controller/core/ControllerCore.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/simulator/src/controller/core/ControllerCore.cpp b/DRAMSys/simulator/src/controller/core/ControllerCore.cpp index 8de6d3f5..da9df026 100644 --- a/DRAMSys/simulator/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/simulator/src/controller/core/ControllerCore.cpp @@ -139,7 +139,7 @@ void ControllerCore::triggerRefresh(tlm::tlm_generic_payload& payload) powerDownManager->wakeUpForRefresh(bank, time); //expects PDNA and PDNP to exit without delay bool pdnpToSrefTransition = false; if (config.PowerDownMode == EPowerDownMode::Staggered) { - pdnpToSrefTransition = state->getLastCommand(Command::PDNPX,bank).getStart() >= time; + pdnpToSrefTransition = state->getLastCommand(Command::PDNPX,bank).getStart() >= time; } if (pdnpToSrefTransition) { powerDownManager->sleep(bank,time);