diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h index 6b673bbf..00518eb5 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h @@ -64,4 +64,4 @@ struct DBDependencyEntry { QString timeDependency; size_t dependencyPhaseID; QString dependencyPhaseName; -}; \ No newline at end of file +}; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h index 7fd828fc..3a4e081c 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h @@ -36,20 +36,34 @@ #pragma once #include +#include #include "StringMapper.h" +class DBPhaseEntryBase; + +#define PASSFUNCTIONDECL (const std::shared_ptr thisPhase, const std::shared_ptr otherPhase) +struct PassFunction { + using Fn = std::function; + PassFunction(Fn passFunction) : mPassFn{std::move(passFunction)} {} + + bool execute PASSFUNCTIONDECL { return mPassFn(thisPhase, otherPhase); } + + Fn mPassFn; +}; + class TimeDependency { public: TimeDependency() = default; TimeDependency(size_t timeValue, QString phaseDep, DependencyType depType, - QString timeDepName, bool considerIntraRank = false) + QString timeDepName, std::shared_ptr pass=nullptr) : timeValue{timeValue}, phaseDep{phaseDep}, depType{depType}, - timeDepName{timeDepName} {} + timeDepName{timeDepName}, passFunction{pass} {} size_t timeValue; StringMapper phaseDep; DependencyType depType; QString timeDepName; + std::shared_ptr passFunction; bool isPool() { return phaseDep.isPool(); } }; \ No newline at end of file diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h index a9eb54e7..9ac9efc7 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h @@ -41,23 +41,26 @@ #include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h" class ConfigurationBase { - public: - ConfigurationBase() {}; - virtual ~ConfigurationBase() = default; +public: + ConfigurationBase() {}; + virtual ~ConfigurationBase() = default; - virtual std::shared_ptr makePhaseEntry(const QSqlQuery&) const { return nullptr; } + virtual QString getQueryStr(const std::vector& commands) const = 0; + virtual std::shared_ptr makePhaseEntry(const QSqlQuery&) const = 0; - // Delegated methods - const uint getClk() const; - DependencyMap getDependencies(std::vector& commands) const; - PoolControllerMap getPools() const; + // Delegated methods + const uint getClk() const; + DependencyMap getDependencies(std::vector& commands) const; + PoolControllerMap getPools() const; - static const QString getDeviceName(const TraceDB& tdb); + static const QString getDeviceName(const TraceDB& tdb); - protected: - std::shared_ptr mDeviceDeps = nullptr; +protected: + std::shared_ptr mDeviceDeps = nullptr; - static const uint mGetClk(const TraceDB& tdb); - static const QJsonObject mGetMemspec(const TraceDB& tdb); + static const uint mGetClk(const TraceDB& tdb); + static const QJsonObject mGetMemspec(const TraceDB& tdb); + + QSqlQuery mExecuteQuery(const QString& queryStr); }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp index ce676838..692b264b 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp @@ -41,6 +41,26 @@ DDR3Configuration::DDR3Configuration(const TraceDB& tdb) { } +QString DDR3Configuration::getQueryStr(const std::vector& commands) const { + // TODO update query text when feature is ready + // QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Rank " + // " FROM Phases " + // " WHERE PhaseName IN ("; + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TRank " + " FROM Phases " + " INNER JOIN Transactions " + " ON Phases.Transact=Transactions.ID " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) { + queryStr = queryStr + '\"' + cmd + "\","; + } + queryStr.back() = ')'; + queryStr += " ORDER BY PhaseBegin; "; + + return queryStr; +} + std::shared_ptr DDR3Configuration::makePhaseEntry(const QSqlQuery& query) const { return std::make_shared(query); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h index 0d0b74db..97fe6175 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h @@ -44,6 +44,7 @@ class DDR3Configuration : public ConfigurationBase { public: DDR3Configuration(const TraceDB& tdb); + QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp index d36d11f3..68f7bc14 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp @@ -40,6 +40,26 @@ DDR4Configuration::DDR4Configuration(const TraceDB& tdb) { } +QString DDR4Configuration::getQueryStr(const std::vector& commands) const { + // TODO update query text when feature is ready + // QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " + // " FROM Phases " + // " WHERE PhaseName IN ("; + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank " + " FROM Phases " + " INNER JOIN Transactions " + " ON Phases.Transact=Transactions.ID " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) { + queryStr = queryStr + '\"' + cmd + "\","; + } + queryStr.back() = ')'; + queryStr += " ORDER BY PhaseBegin; "; + + return queryStr; +} + std::shared_ptr DDR4Configuration::makePhaseEntry(const QSqlQuery& query) const { return std::make_shared(query); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h index f089b2e2..81d63577 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h @@ -43,6 +43,7 @@ class DDR4Configuration : public ConfigurationBase { public: DDR4Configuration(const TraceDB& tdb); + QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp index e0957d53..48bad324 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp @@ -41,6 +41,26 @@ DDR5Configuration::DDR5Configuration(const TraceDB& tdb) { } +QString DDR5Configuration::getQueryStr(const std::vector& commands) const { + // TODO update query text when feature is ready + // QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength " + // " FROM Phases " + // " WHERE PhaseName IN ("; + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank, Transactions.BurstLength " + " FROM Phases " + " INNER JOIN Transactions " + " ON Phases.Transact=Transactions.ID " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) { + queryStr = queryStr + '\"' + cmd + "\","; + } + queryStr.back() = ')'; + queryStr += " ORDER BY PhaseBegin; "; + + return queryStr; +} + std::shared_ptr DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const { auto phase = std::make_shared(query); diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h index 700e6af9..f04b9ecb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h @@ -43,6 +43,7 @@ class DDR5Configuration : public ConfigurationBase { public: DDR5Configuration(const TraceDB& tdb); + QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp index 59586627..e35e83d0 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp @@ -40,6 +40,26 @@ HBM2Configuration::HBM2Configuration(const TraceDB& tdb) { } +QString HBM2Configuration::getQueryStr(const std::vector& commands) const { + // TODO update query text when feature is ready + // QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank " + // " FROM Phases " + // " WHERE PhaseName IN ("; + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank " + " FROM Phases " + " INNER JOIN Transactions " + " ON Phases.Transact=Transactions.ID " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) { + queryStr = queryStr + '\"' + cmd + "\","; + } + queryStr.back() = ')'; + queryStr += " ORDER BY PhaseBegin; "; + + return queryStr; +} + std::shared_ptr HBM2Configuration::makePhaseEntry(const QSqlQuery& query) const { return std::make_shared(query); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h index ac6297e4..cdecc6c2 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h @@ -43,6 +43,7 @@ class HBM2Configuration : public ConfigurationBase { public: HBM2Configuration(const TraceDB& tdb); + QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp index b8b66f0a..c895a7eb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp @@ -41,6 +41,26 @@ LPDDR4Configuration::LPDDR4Configuration(const TraceDB& tdb) { } +QString LPDDR4Configuration::getQueryStr(const std::vector& commands) const { + // TODO update query text when feature is ready + // QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Rank " + // " FROM Phases " + // " WHERE PhaseName IN ("; + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TRank " + " FROM Phases " + " INNER JOIN Transactions " + " ON Phases.Transact=Transactions.ID " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) { + queryStr = queryStr + '\"' + cmd + "\","; + } + queryStr.back() = ')'; + queryStr += " ORDER BY PhaseBegin; "; + + return queryStr; +} + std::shared_ptr LPDDR4Configuration::makePhaseEntry(const QSqlQuery& query) const { return std::make_shared(query); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h index 5882a0b5..ca48f51b 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h @@ -43,6 +43,7 @@ class LPDDR4Configuration : public ConfigurationBase { public: LPDDR4Configuration(const TraceDB& tdb); + QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp index 403cce5f..74430065 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp @@ -41,6 +41,26 @@ LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) { } +QString LPDDR5Configuration::getQueryStr(const std::vector& commands) const { + // TODO update query text when feature is ready + // QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength " + // " FROM Phases " + // " WHERE PhaseName IN ("; + QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank, Transactions.BurstLength " + " FROM Phases " + " INNER JOIN Transactions " + " ON Phases.Transact=Transactions.ID " + " WHERE PhaseName IN ("; + + for (const auto& cmd : commands) { + queryStr = queryStr + '\"' + cmd + "\","; + } + queryStr.back() = ')'; + queryStr += " ORDER BY PhaseBegin; "; + + return queryStr; +} + std::shared_ptr LPDDR5Configuration::makePhaseEntry(const QSqlQuery& query) const { auto phase = std::make_shared(query); diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h index 1b84b4e5..8ee797e9 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h @@ -43,6 +43,7 @@ class LPDDR5Configuration : public ConfigurationBase { public: LPDDR5Configuration(const TraceDB& tdb); + QString getQueryStr(const std::vector& commands) const override; std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h index 81f82a22..f96997e6 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h @@ -40,12 +40,12 @@ #include "businessObjects/phases/phasedependency.h" #include "businessObjects/dramTimeDependencies/common/common.h" -class DBPhaseEntryBase { +class DBPhaseEntryBase : public std::enable_shared_from_this{ public: DBPhaseEntryBase() = default; virtual ~DBPhaseEntryBase() = default; - virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { return false; } + virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { return false; } size_t id; StringMapper phaseName; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp index ab5019ab..a08356ef 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp @@ -42,11 +42,10 @@ DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) { phaseEnd = query.value(3).toLongLong(); transact = query.value(4).toLongLong(); tBank = query.value(5).toLongLong(); - // tBankgroup = query.value(6).toLongLong(); - tRank = query.value(7).toLongLong(); + tRank = query.value(6).toLongLong(); } -bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h index ed78fc98..d2e3e256 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h @@ -41,8 +41,7 @@ class DDR3DBPhaseEntry : public DBPhaseEntryBase { public: DDR3DBPhaseEntry(const QSqlQuery&); - // size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp index ce79d097..2f1d7630 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp @@ -46,7 +46,7 @@ DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(7).toLongLong(); } -bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h index ddf19e90..1adaecbf 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h @@ -44,5 +44,5 @@ class DDR4DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp index adeee0d8..d80f87cb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp @@ -44,12 +44,16 @@ DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) { tBank = query.value(5).toLongLong(); tBankgroup = query.value(6).toLongLong(); tRank = query.value(7).toLongLong(); + tBurstLength = query.value(8).toLongLong(); + } -bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; + if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) return false; + bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; bool const skipOnIntraBankAndDifferentBanks = { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h index cf94e903..14be429d 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h @@ -44,10 +44,11 @@ class DDR5DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tBankInGroup; size_t tRank; + size_t tBurstLength; size_t tLogicalRank; size_t tPhysicalRank; size_t tDIMMRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp index 6403f9bf..79c30240 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp @@ -46,7 +46,7 @@ HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) { tRank = query.value(7).toLongLong(); } -bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h index 476f9e99..34dc25bb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h @@ -44,5 +44,5 @@ class HBM2DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp index 78de425b..d5f9bdef 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp @@ -42,11 +42,10 @@ LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) { phaseEnd = query.value(3).toLongLong(); transact = query.value(4).toLongLong(); tBank = query.value(5).toLongLong(); - // tBankgroup = query.value(6).toLongLong(); - tRank = query.value(7).toLongLong(); + tRank = query.value(6).toLongLong(); } -bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h index 1017ea8f..2d2aa9ee 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h @@ -42,8 +42,7 @@ class LPDDR4DBPhaseEntry : public DBPhaseEntryBase { public: LPDDR4DBPhaseEntry(const QSqlQuery&); - // size_t tBankgroup; size_t tRank; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp index 25986237..f2d460d3 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp @@ -44,12 +44,16 @@ LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) { tBank = query.value(5).toLongLong(); tBankgroup = query.value(6).toLongLong(); tRank = query.value(7).toLongLong(); + tBurstLength = query.value(8).toLongLong(); } -bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { +bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) { auto other = std::dynamic_pointer_cast(otherPhase); if (!other) return false; + if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) return false; + + bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; bool thisIsREFP2B = phaseName == StringMapper::Identifier::REFP2B; bool otherIsREFP2B = dep.phaseDep == StringMapper::Identifier::REFP2B; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h index 77af463a..c7c4bc90 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h @@ -43,7 +43,8 @@ class LPDDR5DBPhaseEntry : public DBPhaseEntryBase { size_t tBankgroup; size_t tRank; + size_t tBurstLength; size_t bankOffsetREFP2B; - bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) override; }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp index c36b40b5..185804ce 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -86,6 +86,7 @@ void TimeDependenciesInfoDDR5::mInitializeValues() { tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt(); tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt(); + tCCD_L_WR2_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt(); tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt(); tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt(); tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt(); @@ -138,8 +139,6 @@ void TimeDependenciesInfoDDR5::mInitializeValues() { } cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); - if (!(burstLength == 16 && bitWidth == 4)) - tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt(); tBURST16 = 8 * tCK; tBURST32 = 16 * tCK; @@ -236,6 +235,49 @@ const std::vector TimeDependenciesInfoDDR5::getPossiblePhases() { DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { DependencyMap dmap; + auto passBurstLength16 = std::make_shared( + [] PASSFUNCTIONDECL { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + return other->tBurstLength == 16; + } + ); + auto passBurstLength32 = std::make_shared( + [] PASSFUNCTIONDECL { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + return other->tBurstLength == 32; + } + ); + const auto localBitWidth = bitWidth; + auto passThisBL16AndBW4 = std::make_shared( + [localBitWidth] PASSFUNCTIONDECL { + auto thisP = std::dynamic_pointer_cast(thisPhase); + if (!thisP) return false; + return thisP->tBurstLength == 16 && localBitWidth == 4; + } + ); + auto passOtherBL32ThisBL16BW4 = std::make_shared( + [passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL { + return passBurstLength32->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase); + } + ); + auto passOtherBL32ThisNotBL16BW4 = std::make_shared( + [passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL { + return passBurstLength32->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase); + } + ); + auto passOtherBL16ThisBL16BW4 = std::make_shared( + [passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL { + return passBurstLength16->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase); + } + ); + auto passOtherBL16ThisNotBL16BW4 = std::make_shared( + [passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL { + return passBurstLength16->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase); + } + ); + dmap.emplace( piecewise_construct, forward_as_tuple("ACT"), @@ -246,8 +288,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"}, {tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"}, {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"}, - {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"}, - {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"}, + {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT", passBurstLength16}, + {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16", passBurstLength32}, {tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"}, {tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"}, @@ -274,40 +316,40 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, - {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, - {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -319,43 +361,48 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, - {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, - {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, + {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4}, + {tCCD_L_WR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4}, + {tCCD_L_WR2_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4}, + {tCCD_L_WR2_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4}, {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, - {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, - {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"}, + {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4}, + {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4}, + {tCCD_L_WR2_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4}, + {tCCD_L_WR2_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4}, {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, + {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -368,8 +415,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"}, @@ -386,42 +433,42 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, + {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"}, {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"}, - {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"}, - {tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"}, - {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"}, - {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"}, - {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"}, - {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"}, - {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA"}, - {tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16"}, - {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, - {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"}, - {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"}, - {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"}, - {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"}, - {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"}, - {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"}, - {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"}, - {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"}, - {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"}, - {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"}, + {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16}, + {tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16}, + {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32}, + {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16}, + {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32}, + {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA", passBurstLength16}, + {tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16}, + {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16}, + {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32}, + {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16}, + {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32}, + {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16}, + {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32}, + {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16}, + {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -433,43 +480,43 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD, "ACT", DependencyType::IntraBank, "tRCD"}, - {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, - {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"}, - {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"}, - {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"}, - {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"}, - {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"}, - {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"}, - {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"}, - {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"}, - {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"}, - {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"}, + {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16}, + {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16}, + {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32}, + {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16}, + {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32}, + {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16}, + {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32}, + {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16}, + {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32}, {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, - {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"}, - {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"}, + {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, + {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16}, + {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32}, {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"}, - {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"}, - {tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"}, - {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"}, - {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"}, - {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"}, - {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"}, + {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16}, + {tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32}, + {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16}, + {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32}, + {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16}, + {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32}, {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, } ) @@ -482,8 +529,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, - {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"}, - {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"}, + {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16}, + {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -504,8 +551,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"}, - {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"}, - {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"}, + {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16}, + {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"}, {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -527,8 +574,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"}, {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK"}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16"}, + {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK", passBurstLength16}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"}, {tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -556,8 +603,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"}, {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"}, {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"}, - {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"}, - {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"}, + {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK", passBurstLength16}, + {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32}, {tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"}, {tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"}, {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"}, @@ -585,10 +632,10 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"}, {tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"}, {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32}, + {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, @@ -604,10 +651,10 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const { {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"}, {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"}, {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"}, - {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"}, - {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK"}, - {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"}, + {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32}, + {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16}, + {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"}, {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"}, {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"}, diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h index f17513ab..fbd26766 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h @@ -36,6 +36,7 @@ #pragma once #include "../dramtimedependenciesbase.h" +#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h" class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { public: @@ -79,6 +80,7 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase { uint tWR; uint tCCD_L_slr; uint tCCD_L_WR_slr; + uint tCCD_L_WR2_slr; uint tCCD_S_slr; uint tCCD_S_WR_slr; uint tCCD_dlr; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp index 3a4f5400..d0d5ff97 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp @@ -142,6 +142,21 @@ const std::vector TimeDependenciesInfoLPDDR5::getPossiblePhases() { DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { DependencyMap dmap; + auto passBurstLength16 = std::make_shared( + [] PASSFUNCTIONDECL { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + return other->tBurstLength == 16; + } + ); + auto passBurstLength32 = std::make_shared( + [] PASSFUNCTIONDECL { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + return other->tBurstLength == 32; + } + ); + dmap.emplace( piecewise_construct, forward_as_tuple("ACT"), @@ -149,10 +164,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"}, {tRRD, "ACT", DependencyType::IntraRank, "tRRD"}, - {BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK"}, - {BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK"}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK"}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK"}, + {BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK", passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK", passBurstLength32}, {tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"}, {tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"}, {tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"}, @@ -172,26 +187,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"}, - {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"}, - {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"}, - {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"}, - {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"}, - {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"}, - {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"}, - {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"}, - {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"}, - {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"}, + {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, + {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, } ) @@ -203,26 +218,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"}, - {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"}, - {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, + {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, + {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, } ) @@ -234,10 +249,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, - {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP"}, - {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP"}, - {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR"}, - {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR"}, + {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP", passBurstLength16}, + {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, } @@ -250,26 +265,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"}, - {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"}, - {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"}, - {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"}, - {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"}, - {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"}, - {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"}, - {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"}, - {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"}, - {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"}, + {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, + {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, + {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16}, + {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32}, + {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16}, + {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32}, {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, } ) @@ -281,26 +296,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"}, - {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"}, - {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"}, - {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"}, - {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"}, - {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"}, - {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"}, - {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"}, - {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"}, - {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, + {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32}, + {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16}, + {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32}, + {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, + {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16}, + {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32}, + {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16}, + {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32}, + {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16}, + {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32}, {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, } ) @@ -312,10 +327,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"}, - {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb"}, - {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb"}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"}, + {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32}, {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"}, {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"}, @@ -330,14 +345,14 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { forward_as_tuple( initializer_list{ {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"}, - {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"}, - {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"}, - {BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"}, - {BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"}, - {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"}, - {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"}, - {tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"}, - {tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"}, + {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16}, + {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32}, + {BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16}, + {BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32}, {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"}, {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"}, } @@ -351,10 +366,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"}, {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"}, - {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"}, - {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"}, + {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32}, {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, @@ -372,10 +387,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const { initializer_list{ {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"}, {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"}, - {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"}, - {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"}, - {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"}, - {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"}, + {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16}, + {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32}, + {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16}, + {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32}, {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"}, {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"}, {tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"}, diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h index 3e72a694..0de086e7 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h @@ -36,6 +36,7 @@ #pragma once #include "../dramtimedependenciesbase.h" +#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h" class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase { public: diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp index eb935e2d..57bbdec8 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp @@ -156,17 +156,7 @@ const std::vector> PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr deviceConfig, TraceDB& tdb, const std::vector& commands) { std::vector> phases; - QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank " - " FROM Phases " - " INNER JOIN Transactions " - " ON Phases.Transact=Transactions.ID " - " WHERE PhaseName IN ("; - - for (const auto& cmd : commands) { - queryStr = queryStr + '\"' + cmd + "\","; - } - queryStr.back() = ')'; - queryStr += " ORDER BY PhaseBegin; "; + QString queryStr = deviceConfig->getQueryStr(commands); auto query = mExecuteQuery(tdb, queryStr); @@ -191,7 +181,6 @@ PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptrmakePhaseEntry(query); ++rowIt;