From 3567ff334531c3f7c09a84f9589938673e472694 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Sun, 9 Mar 2014 05:24:34 -0700 Subject: [PATCH] scheduling base, command generator --- DRAM/src/core/scheduling/Command.h | 17 ++++ DRAM/src/core/scheduling/CommandGenerator.cpp | 83 +++++++++++++++++++ DRAM/src/core/scheduling/CommandGenerator.h | 36 ++++++++ DRAM/src/core/scheduling/CommandSchedule.h | 48 +++++++++++ DRAM/src/core/scheduling/InternalScheduler.h | 22 +++++ DRAM/testing/CommandGenerator_test.cpp | 67 +++++++++++++++ 6 files changed, 273 insertions(+) create mode 100644 DRAM/src/core/scheduling/Command.h create mode 100644 DRAM/src/core/scheduling/CommandGenerator.cpp create mode 100644 DRAM/src/core/scheduling/CommandGenerator.h create mode 100644 DRAM/src/core/scheduling/CommandSchedule.h create mode 100644 DRAM/src/core/scheduling/InternalScheduler.h create mode 100644 DRAM/testing/CommandGenerator_test.cpp diff --git a/DRAM/src/core/scheduling/Command.h b/DRAM/src/core/scheduling/Command.h new file mode 100644 index 00000000..c20eca1a --- /dev/null +++ b/DRAM/src/core/scheduling/Command.h @@ -0,0 +1,17 @@ +/* + * Command.h + * + * Created on: Mar 5, 2014 + * Author: jonny + */ + +#ifndef COMMAND_H_ +#define COMMAND_H_ + +namespace controller { + +enum class Command {Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, Refresh, RefreshTrigger};//TODO handle RefreshTrigger Event differently + +} /* namespace controller */ + +#endif /* COMMAND_H_ */ diff --git a/DRAM/src/core/scheduling/CommandGenerator.cpp b/DRAM/src/core/scheduling/CommandGenerator.cpp new file mode 100644 index 00000000..63b68eab --- /dev/null +++ b/DRAM/src/core/scheduling/CommandGenerator.cpp @@ -0,0 +1,83 @@ +/* + * CommandGenerator.cpp + * + * Created on: Mar 5, 2014 + * Author: jonny + */ + +#include "CommandGenerator.h" +#include "common/schedulerextension.h" +#include "vector" + +using namespace common; +using namespace std; + +namespace controller { + +vector CommandGenerator::generateCommandSequence(tlm::tlm_generic_payload& transaction) +{ + const SchedulerExtension& extension = SchedulerExtension::getExtension(&transaction); + Bank bank = extension.getBank(); + Row row = extension.getRow(); + + vector result; + + if (!controllerState.bankStates.rowBufferIsOpen(bank)) + { + return getBankMissCommandSequence(transaction); + } + else if (controllerState.bankStates.getRowInRowBuffer(bank) != row) + { + return getRowMissCommandSequence(transaction); + } + else + { + return getRowHitCommandSequence(transaction); + } +} + +vector CommandGenerator::generateCommandSequence( + tlm::tlm_generic_payload* transaction) +{ + return generateCommandSequence(*transaction); +} + +vector CommandGenerator::getBankMissCommandSequence(tlm::tlm_generic_payload& transaction) +{ + vector result; + result.push_back(Command::Activate); + result.push_back(getReadWriteCommand(transaction)); + return result; +} + +vector CommandGenerator::getRowMissCommandSequence(tlm::tlm_generic_payload& transaction) +{ + vector result; + result.push_back(Command::Precharge); + result.push_back(Command::Activate); + result.push_back(getReadWriteCommand(transaction)); + return result; +} + +vector CommandGenerator::getRowHitCommandSequence(tlm::tlm_generic_payload& transaction) +{ + vector result; + result.push_back(getReadWriteCommand(transaction)); + return result; +} + +Command CommandGenerator::getReadWriteCommand(tlm::tlm_generic_payload& transaction) +{ + if (transaction.get_command() == tlm::tlm_command::TLM_READ_COMMAND) + { + //TODO READA + return Command::Read; + } + else + { + return Command::Write; + } +} + +} /* namespace controller */ + diff --git a/DRAM/src/core/scheduling/CommandGenerator.h b/DRAM/src/core/scheduling/CommandGenerator.h new file mode 100644 index 00000000..afa228f5 --- /dev/null +++ b/DRAM/src/core/scheduling/CommandGenerator.h @@ -0,0 +1,36 @@ +/* + * CommandGenerator.h + * + * Created on: Mar 5, 2014 + * Author: jonny + */ + +#ifndef COMMANDGENERATOR_H_ +#define COMMANDGENERATOR_H_ + +#include +#include "core/ControllerState.h" +#include "Command.h" + +namespace controller { + +class CommandGenerator { +public: + CommandGenerator(const ControllerState& controllerState) : controllerState(controllerState) {}; + virtual ~CommandGenerator() {}; + + std::vector generateCommandSequence(tlm::tlm_generic_payload& transaction); + std::vector generateCommandSequence(tlm::tlm_generic_payload* transaction); + +private: + const ControllerState& controllerState; + + Command getReadWriteCommand(tlm::tlm_generic_payload& transaction); + std::vector getBankMissCommandSequence(tlm::tlm_generic_payload& transaction); + std::vector getRowMissCommandSequence(tlm::tlm_generic_payload& transaction); + std::vector getRowHitCommandSequence(tlm::tlm_generic_payload& transaction); +}; + +} /* namespace controller */ + +#endif /* COMMANDGENERATOR_H_ */ diff --git a/DRAM/src/core/scheduling/CommandSchedule.h b/DRAM/src/core/scheduling/CommandSchedule.h new file mode 100644 index 00000000..f940616f --- /dev/null +++ b/DRAM/src/core/scheduling/CommandSchedule.h @@ -0,0 +1,48 @@ +/* + * CommandSchedule.h + * + * Created on: Mar 5, 2014 + * Author: jonny + */ + +#ifndef COMMANDSCHEDULE_H_ +#define COMMANDSCHEDULE_H_ + +#include +#include +#include "Command.h" + + +namespace controller { + +struct ScheduledCommand{ + ScheduledCommand(Command command, sc_time time) : command(command), time(time){}; + Command command; + sc_time time; + + inline bool operator==(const ScheduledCommand& b) const + { + return b.command == command && b.time == time; + } +}; + +class CommandSchedule { +public: + CommandSchedule(); + virtual ~CommandSchedule(); + + void push_back(ScheduledCommand scheduledCommand) + { + scheduledCommands.push_back(scheduledCommand); + } + const std::vector& getScheduledCommands() const + { + return this->scheduledCommands; + } +private: + std::vector scheduledCommands; +}; + +} /* namespace controller */ + +#endif /* COMMANDSCHEDULE_H_ */ diff --git a/DRAM/src/core/scheduling/InternalScheduler.h b/DRAM/src/core/scheduling/InternalScheduler.h new file mode 100644 index 00000000..10520b8d --- /dev/null +++ b/DRAM/src/core/scheduling/InternalScheduler.h @@ -0,0 +1,22 @@ +/* + * InternalScheduler.h + * + * Created on: Mar 6, 2014 + * Author: jonny + */ + +#ifndef INTERNALSCHEDULER_H_ +#define INTERNALSCHEDULER_H_ + +#include "CommandSchedule.h" + +class InternalScheduler +{ +public: + virtual ~InternalScheduler() {} + virtual void scheduleCommand(controller::ScheduledCommand command) = 0; +}; + + + +#endif /* INTERNALSCHEDULER_H_ */ diff --git a/DRAM/testing/CommandGenerator_test.cpp b/DRAM/testing/CommandGenerator_test.cpp new file mode 100644 index 00000000..f219a299 --- /dev/null +++ b/DRAM/testing/CommandGenerator_test.cpp @@ -0,0 +1,67 @@ +#include +#include "core/scheduling/CommandGenerator.h" +#include "testUtils.h" +#include + +using namespace controller; +using namespace common; +using namespace std; + +constexpr unsigned int numberOfBanks = 8; + +constexpr tlm::tlm_command READ = tlm::tlm_command::TLM_READ_COMMAND; +constexpr tlm::tlm_command WRITE = tlm::tlm_command::TLM_WRITE_COMMAND; + +TEST(CommandGenerator, ReadAndWriteWithRowHit) +{ + ControllerState state(numberOfBanks); + CommandGenerator generator(state); + + state.bankStates.openRowInRowBuffer(Bank(0), Row(3)); + + auto hit_read = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), READ); + auto hit_write = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), WRITE); + + + vector expected_read ({Command::Read}); + vector expected_write ({Command::Write}); + + EXPECT_EQ(expected_read, generator.generateCommandSequence(hit_read.get())); + EXPECT_EQ(expected_write, generator.generateCommandSequence(hit_write.get())); +} + +TEST(CommandGenerator, ReadAndWriteWithRowMiss) +{ + ControllerState state(numberOfBanks); + CommandGenerator generator(state); + + state.bankStates.openRowInRowBuffer(Bank(0), Row(3)); + + auto miss_read = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), READ); + auto miss_write = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), WRITE); + + + vector expected_read ({Command::Precharge, Command::Activate, Command::Read}); + vector expected_write ({Command::Precharge, Command::Activate, Command::Write}); + + EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get())); + EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get())); +} + +TEST(CommandGenerator, ReadAndWriteWithBankMiss) +{ + ControllerState state(numberOfBanks); + CommandGenerator generator(state); + + state.bankStates.openRowInRowBuffer(Bank(0), Row(3)); + + auto miss_read = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), READ); + auto miss_write = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), WRITE); + + + vector expected_read ({Command::Activate, Command::Read}); + vector expected_write ({Command::Activate, Command::Write}); + + EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get())); + EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get())); +}