diff --git a/DRAMSys/gem5/etrace_single/config.ini b/DRAMSys/gem5/etrace_single/config.ini
new file mode 100644
index 00000000..cec31376
--- /dev/null
+++ b/DRAMSys/gem5/etrace_single/config.ini
@@ -0,0 +1,448 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+kernel_extras=
+load_addr_mask=18446744073709551615
+load_offset=0
+mem_mode=timing
+mem_ranges=0:536870911:0:0:0:0
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TraceCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+checker=Null
+clk_domain=system.clk_domain
+cpu_id=0
+dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+enableEarlyExit=false
+eventq_index=0
+freqMultiplier=1.0
+function_trace=false
+function_trace_start=0
+instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_gating_on_idle=false
+power_model=
+profile=0
+progressMsgInterval=0
+progress_interval=0
+pwr_gating_latency=300
+simpoint_start_insts=
+sizeLoadBuffer=16
+sizeROB=40
+sizeStoreBuffer=16
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=Cache
+children=replacement_policy tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+prefetch_on_access=false
+prefetcher=Null
+replacement_policy=system.cpu.dcache.replacement_policy
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tag_latency=2
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+warmup_percentage=0
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.dcache_port
+mem_side=system.membus.slave[2]
+
+[system.cpu.dcache.replacement_policy]
+type=LRURP
+eventq_index=0
+
+[system.cpu.dcache.tags]
+type=BaseSetAssoc
+assoc=2
+block_size=64
+clk_domain=system.clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+replacement_policy=system.cpu.dcache.replacement_policy
+sequential_access=false
+size=32768
+tag_latency=2
+warmup_percentage=0
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+sys=system
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+sys=system
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.icache]
+type=Cache
+children=replacement_policy tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+prefetch_on_access=false
+prefetcher=Null
+replacement_policy=system.cpu.icache.replacement_policy
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+warmup_percentage=0
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.membus.slave[1]
+
+[system.cpu.icache.replacement_policy]
+type=LRURP
+eventq_index=0
+
+[system.cpu.icache.tags]
+type=BaseSetAssoc
+assoc=2
+block_size=64
+clk_domain=system.clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+replacement_policy=system.cpu.icache.replacement_policy
+sequential_access=false
+size=32768
+tag_latency=2
+warmup_percentage=0
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+decoderFlavour=Generic
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+impdef_nop=false
+midr=1091551472
+pmu=Null
+system=system
+vecRegRenameMode=Full
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+sys=system
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+sys=system
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.cpu_voltage_domain
+
+[system.cpu_voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.0
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+point_of_unification=true
+power_model=
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.tlm.port
+slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+latency=30000
+latency_var=0
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+range=0:134217727:0:0:0:0
+
+[system.tlm]
+type=ExternalSlave
+addr_ranges=0:536870911:0:0:0:0
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+port_data=transactor
+port_type=tlm_slave
+power_model=
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.0
+
diff --git a/DRAMSys/gem5/etrace_single_L2/config.ini b/DRAMSys/gem5/etrace_single_L2/config.ini
new file mode 100644
index 00000000..5e8ef16a
--- /dev/null
+++ b/DRAMSys/gem5/etrace_single_L2/config.ini
@@ -0,0 +1,534 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+kernel_extras=
+load_addr_mask=18446744073709551615
+load_offset=0
+mem_mode=timing
+mem_ranges=0:1073741823:0:0:0:0
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TraceCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+checker=Null
+clk_domain=system.clk_domain
+cpu_id=0
+dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+enableEarlyExit=false
+eventq_index=0
+freqMultiplier=1.0
+function_trace=false
+function_trace_start=0
+instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_gating_on_idle=false
+power_model=
+profile=0
+progressMsgInterval=0
+progress_interval=0
+pwr_gating_latency=300
+simpoint_start_insts=
+sizeLoadBuffer=16
+sizeROB=40
+sizeStoreBuffer=16
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=Cache
+children=replacement_policy tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+prefetch_on_access=false
+prefetcher=Null
+replacement_policy=system.cpu.dcache.replacement_policy
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tag_latency=2
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+warmup_percentage=0
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.dcache_port
+mem_side=system.tol2bus.slave[1]
+
+[system.cpu.dcache.replacement_policy]
+type=LRURP
+eventq_index=0
+
+[system.cpu.dcache.tags]
+type=BaseSetAssoc
+assoc=2
+block_size=64
+clk_domain=system.clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+replacement_policy=system.cpu.dcache.replacement_policy
+sequential_access=false
+size=32768
+tag_latency=2
+warmup_percentage=0
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+sys=system
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+sys=system
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.icache]
+type=Cache
+children=replacement_policy tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+prefetch_on_access=false
+prefetcher=Null
+replacement_policy=system.cpu.icache.replacement_policy
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+warmup_percentage=0
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.tol2bus.slave[0]
+
+[system.cpu.icache.replacement_policy]
+type=LRURP
+eventq_index=0
+
+[system.cpu.icache.tags]
+type=BaseSetAssoc
+assoc=2
+block_size=64
+clk_domain=system.clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+replacement_policy=system.cpu.icache.replacement_policy
+sequential_access=false
+size=32768
+tag_latency=2
+warmup_percentage=0
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+decoderFlavour=Generic
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+impdef_nop=false
+midr=1091551472
+pmu=Null
+system=system
+vecRegRenameMode=Full
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+sys=system
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+sys=system
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+sys=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.cpu_voltage_domain
+
+[system.cpu_voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.0
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.l2cache]
+type=Cache
+children=replacement_policy tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.clk_domain
+clusivity=mostly_incl
+data_latency=20
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+prefetch_on_access=false
+prefetcher=Null
+replacement_policy=system.l2cache.replacement_policy
+response_latency=20
+sequential_access=false
+size=1048576
+system=system
+tag_latency=20
+tags=system.l2cache.tags
+tgts_per_mshr=12
+warmup_percentage=0
+write_buffers=8
+writeback_clean=false
+cpu_side=system.tol2bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.l2cache.replacement_policy]
+type=LRURP
+eventq_index=0
+
+[system.l2cache.tags]
+type=BaseSetAssoc
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+replacement_policy=system.l2cache.replacement_policy
+sequential_access=false
+size=1048576
+tag_latency=20
+warmup_percentage=0
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+point_of_unification=true
+power_model=
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.tlm.port
+slave=system.system_port system.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+latency=30000
+latency_var=0
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=
+range=0:134217727:0:0:0:0
+
+[system.tlm]
+type=ExternalSlave
+addr_ranges=0:4294967295:0:0:0:0
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+port_data=transactor
+port_type=tlm_slave
+power_model=
+port=system.membus.master[0]
+
+[system.tol2bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+point_of_unification=true
+power_model=
+response_latency=1
+snoop_filter=system.tol2bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.tol2bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.0
+