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Add logo and UML to the readme.

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Lukas Steiner
2020-07-20 15:15:04 +02:00
parent cf3398c66f
commit 2f34b4d8dc
1 changed files with 21 additions and 12 deletions
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README.md
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@@ -1,7 +1,10 @@
DRAMSys4.0
===========
<img src="DRAMSys/docs/images/dramsys4_0.png" width="350" style="float: left;"/>
**DRAMSys4.0** [1] [2] [3] is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0.
**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0.
Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
[![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
@@ -18,6 +21,12 @@ Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sy
- coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation
- **Trace Analyzer** for visual and metric-based result analysis
## Architecture and Functionality
A UML diagram of the software architecture is presented below; different component implementations are left out for simplicity. More information about the architecture and functionality can be found in the papers [1] [2] [3] and in the introduction video on [Youtube](https://www.youtube.com/watch?v=8EkC3mYWpQY).
<img src="DRAMSys/docs/images/dramsys_uml.png" alt="UML" />
## Basic Setup
Start using DRAMSys by cloning the repository.
@@ -134,7 +143,7 @@ Syntax example:
# [clock-cyle]: [write|read] [hex-address] [hex-data (optional)]
31: read 0x400140
33: read 0x400160
56: write 0x7fff8000 0x123456789abcdef
56: write 0x7fff8000 0x123456789abcdef...
81: read 0x400180
```
@@ -149,7 +158,7 @@ Syntax example:
# [clock-cyle]: [write|read] [hex-address] [hex-data (optional)]
31: read 0x400140
2: read 0x400160
23: write 0x7fff8000 0x123456789abcdef
23: write 0x7fff8000 0x123456789abcdef...
25: read 0x400180
```
@@ -184,8 +193,8 @@ The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json
"ECCControllerMode": "Disabled",
"UseMalloc": false,
"AddressOffset": 0,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"ErrorCSVFile": "",
"StoreMode": "NoStorage"
}
}