derek/DRAMSys
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changed scheduler interface. Fixed bug with terminateSimulation

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This commit is contained in:
robert
2014-06-20 15:49:07 +02:00
parent 96846ca4b4
commit 2b062b86ff
42 changed files with 522 additions and 516 deletions
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18
dram/src/controller/core/ControllerCore.cpp
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@@ -94,12 +94,12 @@ void ControllerCore::resetState()
void ControllerCore::triggerRefresh(tlm::tlm_generic_payload& payload, sc_time time)
{
Bank bank = DramExtension::getExtension(payload).getBank();
printDebugMessage("Triggering refresh on bank " + to_string(bank.ID()));
state.cleanUp(time);
if (!refreshManager->isInvalidated(payload, time) && !powerDownManager->isInSelfRefresh(bank))
{
printDebugMessage("Triggering refresh on bank " + to_string(bank.ID()));
powerDownManager->wakeUpForRefresh(bank, time); //expects PDNA and PDNP to exit without delay
refreshManager->scheduleRefresh(payload, time);
}
@@ -127,7 +127,7 @@ bool ControllerCore::scheduleRequest(sc_time start, tlm::tlm_generic_payload& pa
}
}
bool ControllerCore::isBusy(sc_time time, Bank bank)
bool ControllerCore::bankIsBusy(sc_time time, Bank bank)
{
ScheduledCommand lastScheduledCommand = state.getLastScheduledCommand(bank);
@@ -158,9 +158,10 @@ bool ControllerCore::isBusy(sc_time time, Bank bank)
}
const std::vector<Bank>& ControllerCore::getBanks() const
const std::vector<Bank>& ControllerCore::getBanks()
{
static std::vector<Bank> banks;
if (banks.size() == 0)
{
for (unsigned int i = 0; i < config.NumberOfBanks; i++)
@@ -172,6 +173,17 @@ const std::vector<Bank>& ControllerCore::getBanks() const
return banks;
}
std::vector<Bank> ControllerCore::getFreeBanks(sc_time currentTime)
{
std::vector<Bank> freeBanks;
for(Bank bank: getBanks())
{
if(!bankIsBusy(currentTime, bank))
freeBanks.push_back(bank);
}
return freeBanks;
}
void ControllerCore::send(const CommandSchedule& schedule, tlm::tlm_generic_payload& payload) const
{
for (const ScheduledCommand& cmd : schedule.getScheduledCommands())