From 2a587436d9100454d5d3b50daea721aa44dce64e Mon Sep 17 00:00:00 2001
From: Peter Ehses <ehses@rhrk.uni-kl.de>
Date: Thu, 9 Apr 2015 10:01:27 +0200
Subject: [PATCH] Fixed small bug

---
 dram/src/simulation/Dram.h | 43 +++++++++++++++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 5 deletions(-)

diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h
index 8188c02c..cf5bdaaa 100644
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -64,7 +64,7 @@ struct Dram: sc_module
         IFPOW( DRAMPower = new libDRAMPower( memSpec, 0 ) );
         cout << "StorageMode = " << StorageMode << endl;
 
-        if(StorageMode == 2)
+        if(StorageMode == 2) 
         {
             fmemory = new flip_memory[Configuration::getInstance().memSpec.NumberOfBanks];
         }
@@ -126,20 +126,19 @@ struct Dram: sc_module
             {
                 // Don't store data
             }
-            else if (StorageMode == 1) //don't use StorageMode
+            else if (StorageMode == 1) // Use Storage
             {
                 memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8);
             }
-            else
+            else // == 2 Use Storage with Error Model
             {
                 fmemory[bank].store(payload);
-                sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
             }
+            sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
         }
         else if (phase == BEGIN_RD)
         {
             IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle));
-            sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
 
             // Load data:
             if (StorageMode == 1)    //use StorageMode
@@ -157,15 +156,49 @@ struct Dram: sc_module
             {
                 fmemory[bank].load(payload);
             }
+
+            sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
         }
         else if (phase == BEGIN_WRA)
         {
             IFPOW(DRAMPower->doCommand(MemCommand::WRA, bank, cycle));
+
+            //save data:
+            if (StorageMode == 0)
+            {
+                // Don't store data
+            }
+            else if (StorageMode == 1) // Use Storage
+            {
+                memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8);
+            }
+            else // == 2 Use Storage with Error Model
+            {
+                fmemory[bank].store(payload);
+            }
             sendToController(payload, END_WRA, delay +  getExecutionTime(Command::WriteA, payload));
         }
         else if (phase == BEGIN_RDA)
         {
             IFPOW(DRAMPower->doCommand(MemCommand::RDA, bank, cycle));
+
+            // Load data:
+            if (StorageMode == 1)    //use StorageMode
+            {
+                if(memory.count(payload.get_address()) == 1)
+                {
+                    memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8);
+                }
+                else
+                {
+                    //SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location.");
+                }
+            }
+            else if(StorageMode == 2)// use StorageMode with errormodel
+            {
+                fmemory[bank].load(payload);
+            }
+
             sendToController(payload, END_RDA, delay +  getExecutionTime(Command::ReadA, payload));
         }
         else if (phase == BEGIN_REFA)