From 263d28d1be451668d37eb2dde06e46f698f88637 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 25 Aug 2022 16:49:32 +0200 Subject: [PATCH] Fix HBM2 assertion in TimingChecker. --- DRAMSys/library/src/controller/checker/CheckerHBM2.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 671dcb07..76bd4650 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -135,7 +135,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic else if (command == Command::WR || command == Command::WRA) { unsigned burstLength = ControllerExtension::getBurstLength(payload); - assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2)); // Legacy mode + assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2 || burstLength == 4)); // Legacy mode assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];