diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml
index 964ed8e2..73231bba 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="8" />
     <Scheduler value="FIFO" />
@@ -7,11 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Modelling -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
index 635a5a82..dee4f5d4 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="8" />
     <Scheduler value="FIFO_STRICT" />
@@ -7,11 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Modelling -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
index 964ed8e2..73231bba 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="8" />
     <Scheduler value="FIFO" />
@@ -7,11 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Modelling -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
index 5a4ca81f..e5a6579e 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="8" />
     <Scheduler value="FR_FCFS" />
@@ -7,12 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Model: -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
-
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
index b6484e89..61221894 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
@@ -1,16 +1,49 @@
 <mcconfig>
-    <BankwiseLogic value="1"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="16" />
     <Scheduler value="FR_FCFS" />
     <Capsize value="5" />
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
+	<!-- Bankwise -->
+    <BankwiseLogic value="1"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
-
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
index d57cdc53..ff37370c 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
@@ -1,15 +1,49 @@
 <mcconfig>
-    <BankwiseLogic value="1"/>
     <OpenPagePolicy value="0" />
     <MaxNrOfTransactions value="16" />
     <Scheduler value="FR_FCFS" />
     <Capsize value="5" />
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
+	<!-- Bankwise -->
+    <BankwiseLogic value="1"/>
+    <!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
index 945ac58f..75570d40 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="16" />
     <Scheduler value="FR_FCFS_GRP" />
@@ -7,7 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Model: -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
+    <ControllerCoreRefEnablePostpone value="0"/>
+    <ControllerCoreRefEnablePullIn value="0"/>
+    <ControllerCoreRefMaxPostponed value="8"/>
+    <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
-
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
index 575f79b8..c8dd13c2 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
@@ -1,15 +1,49 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="0" />
     <MaxNrOfTransactions value="16" />
     <Scheduler value="FR_FCFS" />
     <Capsize value="5" />
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
index 9068f558..5a9f1c0c 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="16" />
     <Scheduler value="FR_FCFS_RP" />
@@ -7,7 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Model: -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
+    <ControllerCoreRefEnablePostpone value="0"/>
+    <ControllerCoreRefEnablePullIn value="0"/>
+    <ControllerCoreRefMaxPostponed value="8"/>
+    <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
-
diff --git a/DRAMSys/library/resources/configs/mcconfigs/grp.xml b/DRAMSys/library/resources/configs/mcconfigs/grp.xml
index 1d6be156..a62969fb 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/grp.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/grp.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="32" />
     <Scheduler value="GRP" />
@@ -7,11 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Modelling -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
index f2ecfdbe..478ec618 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="8" />
     <Scheduler value="PAR_BS" />
@@ -7,11 +6,45 @@
     <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownMode value="NoPowerDown" />
     <PowerDownTimeout value="100" />
-    <!-- Error Modelling -->
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>
diff --git a/DRAMSys/library/resources/configs/mcconfigs/sms.xml b/DRAMSys/library/resources/configs/mcconfigs/sms.xml
index 003f6a2c..e1ccb478 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/sms.xml
+++ b/DRAMSys/library/resources/configs/mcconfigs/sms.xml
@@ -1,5 +1,4 @@
 <mcconfig>
-    <BankwiseLogic value="0"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="30" />
     <Scheduler value="SMS" />
@@ -7,15 +6,45 @@
     <RequestBufferSize value = "10" />
     <PowerDownMode value="NoPowerDown" /> <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
     <PowerDownTimeout value="100" />
-    <!-- Error Modelling -->
-    <ErrorChipSeed value="42" />
-    <ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
-    <!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
-    <StoreMode value="NoStorage" />
+	<!-- Bankwise -->
+    <BankwiseLogic value="0"/>
+	<!-- Refresh yes, no -->
     <ControllerCoreRefDisable value="0"/>
-    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
+	<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
+    <ControllerCoreRefMode value="1"/>
+    <!-- Number of AR commands in a tREFI in 1X mode -->
+    <ControllerCoreRefNumARCmdsIntREFI value="8192"/>
+	<!-- RGR -->
+    <ControllerCoreRGR value="0"/>
+    <ControllerCoreRGRRowInc value="1"/>
+	<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
+    <ControllerCoreRGRB0  value="1"/>
+    <ControllerCoreRGRB1  value="1"/>
+    <ControllerCoreRGRB2  value="1"/>
+    <ControllerCoreRGRB3  value="1"/>
+    <ControllerCoreRGRB4  value="1"/>
+    <ControllerCoreRGRB5  value="1"/>
+    <ControllerCoreRGRB6  value="1"/>
+    <ControllerCoreRGRB7  value="1"/>
+    <ControllerCoreRGRB8  value="0"/>
+    <ControllerCoreRGRB9  value="0"/>
+    <ControllerCoreRGRB10 value="0"/>
+    <ControllerCoreRGRB11 value="0"/>
+    <ControllerCoreRGRB12 value="0"/>
+    <ControllerCoreRGRB13 value="0"/>
+    <ControllerCoreRGRB14 value="0"/>
+    <ControllerCoreRGRB15 value="0"/>
+	<!-- Timings for RGR normal or optimal values -->
+    <ControllerCoreRGRtRASBInClkCycles value="22"/>
+    <ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
+    <ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
+    <ControllerCoreRGRtRPBInClkCycles value="15"/>
+    <ControllerCoreRGRtRCBInClkCycles value="37"/>
+    <ControllerCoreRGRtFAWBInClkCycles value="0"/>
+	<!-- Postpone, pull-in -->
     <ControllerCoreRefEnablePostpone value="0"/>
     <ControllerCoreRefEnablePullIn value="0"/>
     <ControllerCoreRefMaxPostponed value="8"/>
     <ControllerCoreRefMaxPulledIn value="8"/>
+    <ControllerCoreRefForceMaxPostponeBurst value="0"/>
 </mcconfig>