diff --git a/DRAMSys/analyzer/scripts/tests.py b/DRAMSys/analyzer/scripts/tests.py
index ee844236..531c5c8a 100755
--- a/DRAMSys/analyzer/scripts/tests.py
+++ b/DRAMSys/analyzer/scripts/tests.py
@@ -109,11 +109,36 @@ class DramConfig(object):
             self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL")
             self.tAL = self.clk * memspec.getIntValue("AL")
             self.tRFC = self.clk * memspec.getIntValue("RFC")
+
+        elif (self. memoryType == "DDR3"):
+            self.nActivateWindow = 4
+            self.tRP = self.clk * memspec.getIntValue("RP");
+            self.tRAS = self.clk * memspec.getIntValue("RAS");
+            self.tRC = self.clk * memspec.getIntValue("RC");
+            self.tRTP = self.clk * memspec.getIntValue("RTP");
+            self.tRRD_S = self.clk * memspec.getIntValue("RRD");
+            self.tRRD_L = self.clk * memspec.getIntValue("RRD");
+            self.tCCD_S = self.clk * memspec.getIntValue("CCD");
+            self.tCCD_L = self.clk * memspec.getIntValue("CCD");
+            self.tRCD = self.clk * memspec.getIntValue("RCD");
+            self.tNAW = self.clk * memspec.getIntValue("FAW");
+            self.tRL = self.clk * memspec.getIntValue("RL");
+            self.tWL = self.clk * memspec.getIntValue("WL");
+            self.tWR = self.clk * memspec.getIntValue("WR");
+            self.tWTR_S = self.clk * memspec.getIntValue("WTR");
+            self.tWTR_L = self.clk * memspec.getIntValue("WTR");
+            self.tCKESR = self.clk * memspec.getIntValue("CKESR");
+            self.tCKE = self.clk * memspec.getIntValue("CKE");
+            self.tXP = self.clk * memspec.getIntValue("XP");
+            self.tXPDLL = self.clk * memspec.getIntValue("XPDLL");
+            self.tXSR = self.clk * memspec.getIntValue("XS");
+            self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL");
+            self.tAL = self.clk * memspec.getIntValue("AL");
+            self.tRFC = self.clk * memspec.getIntValue("RFC");
+
         else:
             raise Exception("MemoryType not supported yet. Insert a coin into the coin machine and try again")
 
-        # TODO ADD DDR3
-
     def clkAlign(self, value):
         return math.ceil(1.0*value/self.clk)*self.clk
 
diff --git a/DRAMSys/simulator/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml b/DRAMSys/simulator/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml
new file mode 120000
index 00000000..23f3dba5
--- /dev/null
+++ b/DRAMSys/simulator/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml
@@ -0,0 +1 @@
+../../../src/common/third_party/DRAMPower/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml
\ No newline at end of file