powerdown manager. simulation manager introduced

2014-04-05 12:18:34 +02:00
parent 0e07876071
commit 2145f3b18c
43 changed files with 823 additions and 956 deletions
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -0,0 +1,203 @@
+/*
+ * dram.h
+ *
+ *  Created on: Mar 16, 2014
+ *      Author: robert
+ */
+
+#ifndef DRAM_H_
+#define DRAM_H_
+
+
+#include <iomanip>
+#include <fstream>
+#include <tlm.h>
+#include <systemc.h>
+#include <tlm_utils/peq_with_cb_and_phase.h>
+#include <tlm_utils/simple_initiator_socket.h>
+#include <tlm_utils/simple_target_socket.h>
+
+#include "../common/protocol.h"
+#include "../common/xmlConfig.h"
+
+using namespace sc_core;
+using namespace sc_dt;
+using namespace std;
+using namespace tlm;
+
+
+template <unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false, unsigned int FIXED_BL_VALUE = 0>
+struct Dram: sc_module
+{
+	tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
+	sc_event target_done_event;
+	tlm_utils::peq_with_cb_and_phase<Dram> m_peq;
+	xmlConfig xc;
+
+	SC_CTOR(Dram) :   tSocket("socket") ,m_peq(this, &Dram::peq_cb)
+    {
+      		tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
+	}
+
+	~Dram()
+	{
+
+	}
+
+	// TLM-2 non-blocking transport method
+	virtual tlm::tlm_sync_enum nb_transport_fw( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay )
+	{
+		// Queue the transaction until the annotated time has elapsed
+		m_peq.notify( trans, phase, delay);
+		return tlm::TLM_ACCEPTED;
+	}
+
+	void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase)
+	{
+		if(phase == BEGIN_PRE || phase == BEGIN_PRE_ALL)
+		{
+
+			if(phase == BEGIN_PRE)
+			{
+				send_end_pre(trans);
+			}
+		}
+		else if(phase == BEGIN_ACT)
+		{
+			send_end_act(trans);
+		}
+		else if(phase == BEGIN_WR)
+		{
+			send_end_wr(trans,true);
+		}
+		else if(phase == BEGIN_RD)
+		{
+			send_end_rd(trans,true);
+		}
+		else if(phase == BEGIN_WRA)
+		{
+			send_end_wr(trans,false);
+		}
+		else if(phase == BEGIN_RDA)
+		{
+			send_end_rd(trans,false);
+		}
+		else if(phase == BEGIN_AUTO_REFRESH)
+		{
+			send_end_auto_refresh(trans);
+		}
+		else if(phase == BEGIN_PDNP)
+		{
+
+		}
+		else if(phase == END_PDNP)
+		{
+
+		}
+		else if(phase == BEGIN_PDNA)
+		{
+
+		}
+		else if(phase == END_PDNA)
+		{
+
+		}
+		else if(phase == BEGIN_SREF)
+		{
+
+		}
+		else if(phase == END_SREF)
+		{
+
+		}
+		else // case tlm::BEGIN_REQ,END_REQ...
+		{
+			SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by target (2)");
+		}
+	}
+
+
+	void send_end_auto_refresh(tlm::tlm_generic_payload& trans)
+	{
+		tlm::tlm_phase bw_phase;
+		sc_time delay;
+
+		bw_phase = END_AUTO_REFRESH;
+		delay = xc.tREFB;
+
+		 tSocket->nb_transport_bw( trans, bw_phase, delay );
+
+	}
+
+	void send_end_rd(tlm::tlm_generic_payload& trans, bool open_page_policy_f)
+	{
+		tlm::tlm_phase bw_phase;
+		sc_time delay = SC_ZERO_TIME;
+
+
+		unsigned int BL = 2;
+
+		if(open_page_policy_f == true)
+		{
+			bw_phase = END_RD;
+			delay = xc.tRL + xc.clk * BL;
+		}
+		else
+		{
+			bw_phase = END_RDA;
+			delay = xc.tRL + xc.clk * BL;
+		}
+
+		 tSocket->nb_transport_bw( trans, bw_phase, delay );
+	}
+
+	void send_end_wr(tlm::tlm_generic_payload& trans, bool open_page_policy_f)
+	{
+
+		tlm::tlm_phase bw_phase;
+		sc_time delay = SC_ZERO_TIME;
+
+		unsigned int BL = 2;
+
+		if(open_page_policy_f == true)
+		{
+			bw_phase = END_WR;
+			delay = xc.tWL + xc.clk * (BL -1);
+		}
+		else
+		{
+			bw_phase = END_WRA;
+			delay = xc.tWL + xc.clk * (BL -1) + xc.tWR;
+		}
+
+		// Send end of WR
+		 tSocket->nb_transport_bw( trans, bw_phase, delay );
+	}
+
+	void send_end_pre(tlm::tlm_generic_payload& trans)
+	{
+		tlm::tlm_phase bw_phase;
+		sc_time delay;
+
+		bw_phase = END_PRE;
+		delay = xc.tRP;
+
+		 tSocket->nb_transport_bw( trans, bw_phase, delay );
+	}
+	void send_end_act(tlm::tlm_generic_payload& trans)
+	{
+		tlm::tlm_phase bw_phase;
+		sc_time delay;
+
+		bw_phase = END_ACT;
+		delay = xc.tRCD;
+
+		tSocket->nb_transport_bw( trans, bw_phase, delay );
+	}
+};
+
+
+
+
+
+#endif /* DRAM_H_ */