diff --git a/dram/src/core/Configuration.h b/dram/src/core/Configuration.h
index f5af040c..90a88619 100644
--- a/dram/src/core/Configuration.h
+++ b/dram/src/core/Configuration.h
@@ -15,15 +15,16 @@ namespace core{
 
 struct Configuration
 {
-	Configuration(): numberOfBanks(8),Timings(numberOfBanks),  RefreshBankwise(false),buswidth(128),
+	Configuration(): numberOfBanks(8), burstlength(2), Timings(numberOfBanks),  RefreshBankwise(false),
 			nActivate(2)
 	{}
 	unsigned int numberOfBanks;
+	unsigned int burstlength;
 	TimingConfiguration Timings;
 
 	bool RefreshBankwise;
-	unsigned int buswidth;
 	unsigned int nActivate;
+
 };
 
 } /* namespace controller */
diff --git a/dram/src/core/Controller.cpp b/dram/src/core/Controller.cpp
index a0d20bef..540d34a1 100644
--- a/dram/src/core/Controller.cpp
+++ b/dram/src/core/Controller.cpp
@@ -46,20 +46,21 @@ void DramController::addCommandChecker(Command command, ICommandChecker* checker
 }
 
 
-void DramController::schedule(sc_time currentTime, tlm::tlm_generic_payload& externalTransaction)
+void DramController::schedule(sc_time currentTime, tlm::tlm_generic_payload& payload)
 {
 	bus.cleanUpBus(currentTime);
+	payload.set_streaming_width(config.burstlength);
 
 	CommandSequence sequence = commandSequenceGenerator.generateCommandSequence(
-			externalTransaction);
+			payload);
 	CommandSchedule schedule = commandSequenceScheduler.prepareSchedule(currentTime,
-			externalTransaction, sequence);
+			payload, sequence);
 
 	while (refreshManager.hasCollision(schedule))
 	{
 		refreshManager.scheduleRefresh(currentTime);
-		sequence = commandSequenceGenerator.generateCommandSequence(externalTransaction);
-		schedule = commandSequenceScheduler.prepareSchedule(currentTime, externalTransaction,
+		sequence = commandSequenceGenerator.generateCommandSequence(payload);
+		schedule = commandSequenceScheduler.prepareSchedule(currentTime, payload,
 				sequence);
 		assert(schedule.getExecutionTime() < config.Timings.refreshTimings[0].tREFI); //TODO make nice
 	}
diff --git a/dram/src/core/scheduling/checker/ReadChecker.cpp b/dram/src/core/scheduling/checker/ReadChecker.cpp
index 560240bd..3e6a70f3 100644
--- a/dram/src/core/scheduling/checker/ReadChecker.cpp
+++ b/dram/src/core/scheduling/checker/ReadChecker.cpp
@@ -20,12 +20,12 @@ void ReadChecker::check(ScheduledCommand& command) const
 
 }
 
-sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction,
+sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& payload,
 		Command command) const
 {
 	assert(command == Read || command == ReadA);
 	//return config.Timings.tRL + config.Timings.clk*getBurstLengthInBytes(transaction, config.buswidth);
-	return config.Timings.tRL + config.Timings.clk*2;
+	return config.Timings.tRL + config.Timings.clk*payload.get_streaming_width();
 }
 
 void ReadChecker::notifyAboutScheduledCommand(const ScheduledCommand& command)
diff --git a/dram/src/core/scheduling/checker/ReadChecker.h b/dram/src/core/scheduling/checker/ReadChecker.h
index 4a2ca756..bb87f295 100644
--- a/dram/src/core/scheduling/checker/ReadChecker.h
+++ b/dram/src/core/scheduling/checker/ReadChecker.h
@@ -21,7 +21,7 @@ public:
 	virtual ~ReadChecker() {}
 
 	virtual void check(ScheduledCommand& command) const;
-	virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const;
+	virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& payload, Command command) const;
 	virtual void notifyAboutScheduledCommand(const ScheduledCommand& command);
 private:
 	const Configuration& config;