From 20f783ad38c708f15774836cbfa7aba5c25e06ca Mon Sep 17 00:00:00 2001 From: Iron Prando da Silva Date: Tue, 8 Mar 2022 10:28:39 +0100 Subject: [PATCH] Added HBM2 dependencies. --- DRAMSys/traceAnalyzer/CMakeLists.txt | 4 + .../common/StringMapper.cpp | 6 + .../common/StringMapper.h | 2 + .../configurations/configurationfactory.cpp | 9 + .../configurations/configurationfactory.h | 1 + .../specialized/HBM2Configuration.cpp | 11 + .../specialized/HBM2Configuration.h | 14 + .../specialized/HBM2dbphaseentry.cpp | 45 ++ .../dbEntries/specialized/HBM2dbphaseentry.h | 14 + .../specialized/TimeDependenciesInfoHBM2.cpp | 398 ++++++++++++++++++ .../specialized/TimeDependenciesInfoHBM2.h | 57 +++ 11 files changed, 561 insertions(+) create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp create mode 100644 DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 2ef09e90..f3051aa5 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -127,6 +127,10 @@ add_executable(TraceAnalyzer businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp + + businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp + businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp + businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp index ddc0cfe3..450410bf 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp @@ -11,6 +11,8 @@ StringMapper::StringMapper(const QString& name) { QString StringMapper::getIDStr(StringMapper::Identifier id) { static const std::map enumToStr { {StringMapper::Identifier::CMD_BUS, "CMD_BUS"}, + {StringMapper::Identifier::RAS_BUS, "RAS_BUS"}, + {StringMapper::Identifier::CAS_BUS, "CAS_BUS"}, {StringMapper::Identifier::NAW, "NAW"}, {StringMapper::Identifier::FAW, "FAW"}, {StringMapper::Identifier::_32AW, "32AW"}, @@ -44,6 +46,8 @@ QString StringMapper::getIDStr(StringMapper::Identifier id) { StringMapper::Identifier StringMapper::getIDEnum(const QString& id) { static const std::map strToEnum { {"CMD_BUS", StringMapper::Identifier::CMD_BUS}, + {"RAS_BUS", StringMapper::Identifier::RAS_BUS}, + {"CAS_BUS", StringMapper::Identifier::CAS_BUS}, {"NAW", StringMapper::Identifier::NAW}, {"FAW", StringMapper::Identifier::FAW}, {"32AW", StringMapper::Identifier::_32AW}, @@ -76,6 +80,8 @@ StringMapper::Identifier StringMapper::getIDEnum(const QString& id) { bool StringMapper::mAuxIsPool(StringMapper::Identifier id) { return id == StringMapper::Identifier::CMD_BUS + || id == StringMapper::Identifier::RAS_BUS + || id == StringMapper::Identifier::CAS_BUS || id == StringMapper::Identifier::NAW || id == StringMapper::Identifier::FAW || id == StringMapper::Identifier::_32AW diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h index 2ecf89c3..b4034cd1 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h @@ -9,6 +9,8 @@ class StringMapper { enum Identifier { None, CMD_BUS, + RAS_BUS, + CAS_BUS, NAW, FAW, _32AW, diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp index e75607f0..ee0fa3e2 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp @@ -44,6 +44,9 @@ std::shared_ptr ConfigurationFactory::make(const TraceDB& tdb) } else if (deviceName == "DDR4") { return std::make_shared(tdb); + } else if (deviceName == "HBM2") { + return std::make_shared(tdb); + } else { // TODO maybe throw? throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\''); @@ -62,6 +65,9 @@ const std::vector ConfigurationFactory::possiblePhases(const TraceDB& t } else if (deviceName == "DDR4") { return TimeDependenciesInfoDDR4::getPossiblePhases(); + } else if (deviceName == "HBM2") { + return TimeDependenciesInfoHBM2::getPossiblePhases(); + } else { // TODO maybe throw? // throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\''); @@ -80,6 +86,9 @@ bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) { } else if (deviceName == "DDR4") { return true; + } else if (deviceName == "HBM2") { + return true; + } else { return false; } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h index c38877f5..b7b006a4 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h @@ -40,6 +40,7 @@ #include "configurationIF.h" #include "specialized/DDR3Configuration.h" #include "specialized/DDR4Configuration.h" +#include "specialized/HBM2Configuration.h" #include "data/tracedb.h" class ConfigurationFactory { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp new file mode 100644 index 00000000..0ba89bae --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp @@ -0,0 +1,11 @@ + +#include "HBM2Configuration.h" + +HBM2Configuration::HBM2Configuration(const TraceDB& tdb) { + mDeviceDeps = std::make_shared(std::forward(mGetMemspec(tdb)), mGetClk(tdb)); + +} + +std::shared_ptr HBM2Configuration::makePhaseEntry(const QSqlQuery& query) const { + return std::make_shared(query); +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h new file mode 100644 index 00000000..5abbaa37 --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h @@ -0,0 +1,14 @@ + +#pragma once + +#include "businessObjects/dramTimeDependencies/configurations/configurationIF.h" +#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h" +#include "businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h" + +class HBM2Configuration : public ConfigurationIF { + public: + HBM2Configuration(const TraceDB& tdb); + + std::shared_ptr makePhaseEntry(const QSqlQuery&) const override; + +}; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp new file mode 100644 index 00000000..09e2a38a --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp @@ -0,0 +1,45 @@ + +#include "HBM2dbphaseentry.h" + +HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) { + id = query.value(0).toLongLong(); + phaseName = StringMapper(query.value(1).toString()); + phaseBegin = query.value(2).toLongLong(); + phaseEnd = query.value(3).toLongLong(); + transact = query.value(4).toLongLong(); + tBank = query.value(5).toLongLong(); + tBankgroup = query.value(6).toLongLong(); + tRank = query.value(7).toLongLong(); +} + +bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const { + auto other = std::dynamic_pointer_cast(otherPhase); + if (!other) return false; + + bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS; + + bool const skipOnIntraBankAndDifferentBanks = { + dep.depType == DependencyType::IntraBank + && tBank != other->tBank + }; + bool const skipOnIntraBankgroupAndDifferentBankgroup = { + dep.depType == DependencyType::IntraBankGroup + && tBankgroup != other->tBankgroup + }; + bool const skipOnIntraRankAndDifferentRanks = { + dep.depType == DependencyType::IntraRank + && tRank != other->tRank + }; + bool const skipOnInterRankAndSameRank = { + dep.depType == DependencyType::InterRank + && tRank == other->tRank + && !isCmdPool + }; + + return !( + skipOnIntraBankAndDifferentBanks + || skipOnIntraBankgroupAndDifferentBankgroup + || skipOnIntraRankAndDifferentRanks + || skipOnInterRankAndSameRank + ); +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h new file mode 100644 index 00000000..541693fd --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h @@ -0,0 +1,14 @@ + +#pragma once + +#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryIF.h" + +class HBM2DBPhaseEntry : public DBPhaseEntryIF { + public: + HBM2DBPhaseEntry(const QSqlQuery&); + + size_t tBankgroup; + size_t tRank; + + bool potentialDependency(const TimeDependency& dep, const std::shared_ptr otherPhase) const override; +}; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp new file mode 100644 index 00000000..977de023 --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp @@ -0,0 +1,398 @@ +/* Generated by JetBrains MPS */ + +#include "TimeDependenciesInfoHBM2.h" + +using namespace std; + +TimeDependenciesInfoHBM2::TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesIF(memspec, tCK) { + mInitializeValues(); +} + +void TimeDependenciesInfoHBM2::mInitializeValues() { + burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); + dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); + + mPools.insert({ + "RAS_BUS", { + 1, { + "ACT", + "PREPB", + "PREAB", + "REFPB", + "REFAB", + "PDEA", + "PDXA", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + } + } + }); + + mPools.insert({ + "CAS_BUS", { + 1, { + "RD", + "RDA", + "WR", + "WRA", + "PDEA", + "PDXA", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + } + } + }); + + mPools.insert({ + "NAW", { + 4, { + "ACT", + "REFPB", + } + } + }); + + tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); + tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); + tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); + tRCDRD = tCK * mMemspecJson["memtimingspec"].toObject()["RCDRD"].toInt(); + tRCDWR = tCK * mMemspecJson["memtimingspec"].toObject()["RCDWR"].toInt(); + tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt(); + tRRDS = tCK * mMemspecJson["memtimingspec"].toObject()["RRDS"].toInt(); + tRRDL = tCK * mMemspecJson["memtimingspec"].toObject()["RRDL"].toInt(); + tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt(); + tPL = tCK * mMemspecJson["memtimingspec"].toObject()["PL"].toInt(); + tCCDS = tCK * mMemspecJson["memtimingspec"].toObject()["CCDS"].toInt(); + tCCDL = tCK * mMemspecJson["memtimingspec"].toObject()["CCDL"].toInt(); + tRTW = tCK * mMemspecJson["memtimingspec"].toObject()["RTW"].toInt(); + tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt(); + tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt(); + tWTRS = tCK * mMemspecJson["memtimingspec"].toObject()["WTRS"].toInt(); + tWTRL = tCK * mMemspecJson["memtimingspec"].toObject()["WTRL"].toInt(); + tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt(); + tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt(); + tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(); + tRFCSB = tCK * mMemspecJson["memtimingspec"].toObject()["RFCSB"].toInt(); + tRREFD = tCK * mMemspecJson["memtimingspec"].toObject()["RREFD"].toInt(); + tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt(); + tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt(); + + tPD = tCKE; + tCKESR = tCKE + tCK; + + tBURST = (uint) (burstLength / (float) dataRate) * tCK; + tRDPDE = tRL + tPL + tBURST + tCK; + tRDSRE = tRDPDE; + tWRPRE = tWL + tBURST + tWR; + tWRPDE = tWL + tPL + tBURST + tCK + tWR; + tWRAPDE = tWL + tPL + tBURST + tCK + tWR; + tWRRDS = tWL + tBURST + tWTRS; + tWRRDL = tWL + tBURST + tWTRL; + +} + +const std::vector TimeDependenciesInfoHBM2::getPossiblePhases() { + return { + "ACT", + "RD", + "WR", + "PREPB", + "RDA", + "WRA", + "REFPB", + "REFAB", + "PREAB", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX", + "PDEA", + "PDXA", + }; +} + +DependencyMap TimeDependenciesInfoHBM2::mSpecializedGetDependencies() const { + DependencyMap dmap; + + dmap.emplace( + piecewise_construct, + forward_as_tuple("ACT"), + forward_as_tuple( + initializer_list{ + {tRC, "ACT", DependencyType::IntraBank, "tRC"}, + {tRRDL, "ACT", DependencyType::IntraBankGroup, "tRRDL"}, + {tRRDS, "ACT", DependencyType::IntraRank, "tRRDS"}, + {tRTP + tRP - tCK, "RDA", DependencyType::IntraBank, "tRTP + tRP - tCK"}, + {tWRPRE + tRP - tCK, "WRA", DependencyType::IntraBank, "tWRPRE + tRP - tCK"}, + {tRP - tCK, "PREPB", DependencyType::IntraBank, "tRP - tCK"}, + {tRP - tCK, "PREAB", DependencyType::IntraRank, "tRP - tCK"}, + {tXP - tCK, "PDXA", DependencyType::IntraRank, "tXP - tCK"}, + {tXP - tCK, "PDXP", DependencyType::IntraRank, "tXP - tCK"}, + {tRFC - tCK, "REFAB", DependencyType::IntraRank, "tRFC - tCK"}, + {tRFCSB - tCK, "REFPB", DependencyType::IntraBank, "tRFCSB - tCK"}, + {tRREFD - tCK, "REFPB", DependencyType::IntraBankGroup, "tRREFD - tCK"}, + {tRREFD - tCK, "REFPB", DependencyType::IntraRank, "tRREFD - tCK"}, + {tXS - tCK, "SREFEX", DependencyType::IntraRank, "tXS - tCK"}, + {2 * tCK, "RAS_BUS", DependencyType::InterRank, "2 * tCK"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("RD"), + forward_as_tuple( + initializer_list{ + {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"}, + {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"}, + {tWRRDL, "WR", DependencyType::IntraBank, "tWRRDL"}, + {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"}, + {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("WR"), + forward_as_tuple( + initializer_list{ + {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"}, + {tRTW, "RD", DependencyType::IntraBank, "tRTW"}, + {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RD", DependencyType::IntraRank, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraRank, "tRTW"}, + {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PREPB"), + forward_as_tuple( + initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"}, + {tRTP, "RD", DependencyType::IntraBank, "tRTP"}, + {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("RDA"), + forward_as_tuple( + initializer_list{ + {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"}, + {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"}, + {tWL + tBURST + max({tWR - tRTP, tWTRL}), "WR", DependencyType::IntraBank, "tWL + tBURST + max(tWR - tRTP, tWTRL)"}, + {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"}, + {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"}, + {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("WRA"), + forward_as_tuple( + initializer_list{ + {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"}, + {tRTW, "RD", DependencyType::IntraBank, "tRTW"}, + {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RD", DependencyType::IntraRank, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"}, + {tRTW, "RDA", DependencyType::IntraRank, "tRTW"}, + {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"}, + {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"}, + {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"}, + {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("REFPB"), + forward_as_tuple( + initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraBank, "tRC + tCK"}, + {tRRDL + tCK, "ACT", DependencyType::IntraBankGroup, "tRRDL + tCK"}, + {tRRDS + tCK, "ACT", DependencyType::IntraRank, "tRRDS + tCK"}, + {tRTP + tRP, "RDA", DependencyType::IntraBank, "tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraBank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tRFCSB, "REFPB", DependencyType::IntraBank, "tRFCSB"}, + {tRREFD, "REFPB", DependencyType::IntraBankGroup, "tRREFD"}, + {tRREFD, "REFPB", DependencyType::IntraRank, "tRREFD"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tFAW, "NAW", DependencyType::IntraRank, "tFAW"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("REFAB"), + forward_as_tuple( + initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"}, + {tRTP + tRP, "RDA", DependencyType::IntraRank, "tRTP + tRP"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PREAB"), + forward_as_tuple( + initializer_list{ + {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"}, + {tRTP, "RD", DependencyType::IntraRank, "tRTP"}, + {tRTP, "RDA", DependencyType::IntraRank, "tRTP"}, + {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"}, + {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"}, + {tXP, "PDXA", DependencyType::IntraRank, "tXP"}, + {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PDEP"), + forward_as_tuple( + initializer_list{ + {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"}, + {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"}, + {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"}, + {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PDXP"), + forward_as_tuple( + initializer_list{ + {tPD, "PDEP", DependencyType::IntraRank, "tPD"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("SREFEN"), + forward_as_tuple( + initializer_list{ + {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"}, + {max({tRTP + tRP, tRDSRE}), "RDA", DependencyType::IntraRank, "max(tRTP + tRP, tRDSRE)"}, + {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"}, + {tRP, "PREPB", DependencyType::IntraRank, "tRP"}, + {tRP, "PREAB", DependencyType::IntraRank, "tRP"}, + {tXP, "PDXP", DependencyType::IntraRank, "tXP"}, + {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"}, + {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"}, + {tXS, "SREFEX", DependencyType::IntraRank, "tXS"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("SREFEX"), + forward_as_tuple( + initializer_list{ + {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PDEA"), + forward_as_tuple( + initializer_list{ + {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"}, + {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"}, + {tWRPDE, "WR", DependencyType::IntraRank, "tWRPDE"}, + {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"}, + {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + dmap.emplace( + piecewise_construct, + forward_as_tuple("PDXA"), + forward_as_tuple( + initializer_list{ + {tPD, "PDEA", DependencyType::IntraRank, "tPD"}, + {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"}, + {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"}, + } + ) + ); + + return dmap; +} diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h new file mode 100644 index 00000000..f4c9f523 --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h @@ -0,0 +1,57 @@ +/* Generated by JetBrains MPS */ + +#pragma once + +#include "../dramtimedependenciesIF.h" + +class TimeDependenciesInfoHBM2 final : public DRAMTimeDependenciesIF { + public: + TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint clk); + + static const std::vector getPossiblePhases(); + + protected: + void mInitializeValues() override; + DependencyMap mSpecializedGetDependencies() const override; + + protected: + uint burstLength; + uint dataRate; + + uint tRP; + uint tRAS; + uint tRC; + uint tRCDRD; + uint tRCDWR; + uint tRTP; + uint tRRDS; + uint tRRDL; + uint tRL; + uint tPL; + uint tCCDS; + uint tCCDL; + uint tRTW; + uint tWL; + uint tWR; + uint tWTRS; + uint tWTRL; + uint tCKE; + uint tPD; + uint tXP; + uint tRFC; + uint tRFCSB; + uint tRREFD; + uint tXS; + uint tCKESR; + uint tFAW; + + uint tBURST; + uint tRDPDE; + uint tRDSRE; + uint tWRPRE; + uint tWRPDE; + uint tWRAPDE; + uint tWRRDS; + uint tWRRDL; + +};