diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt
index 7b600c76..9cf7dc56 100644
--- a/DRAMSys/traceAnalyzer/CMakeLists.txt
+++ b/DRAMSys/traceAnalyzer/CMakeLists.txt
@@ -108,14 +108,19 @@ add_executable(TraceAnalyzer
     businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp
     businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp
     businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.cpp
-    businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
     businessObjects/dramTimeDependencies/configurations/configurationIF.cpp
     
     businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp
-    businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
+    # businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
     businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp
     businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
+    
+    businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp
+    
 
+    businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
     businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
 
     selectmetrics.ui
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h
index aaaa5968..2ecf89c3 100644
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h
@@ -27,7 +27,7 @@ class StringMapper {
        ACT,
        RD,
        WR,
-       PREPB, 
+       PREPB,
        RDA, 
        WRA,
        REFPB
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h
index 687073af..6b673bbf 100644
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h
@@ -47,7 +47,6 @@
 
 #include "businessObjects/phases/phasedependency.h"
 #include "timedependency.h"
-#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryTypes.h"
 
 struct PhaseTimeDependencies {
     explicit PhaseTimeDependencies(std::initializer_list<TimeDependency> d) : dependencies(d) {}
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
index 154e18e0..0c5036ef 100644
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
@@ -41,6 +41,9 @@ std::shared_ptr<ConfigurationIF> ConfigurationFactory::make(const TraceDB& tdb)
     if (deviceName == "DDR3") {
         return std::make_shared<DDR3Configuration>(tdb);
 
+    } else if (deviceName == "DDR4") {
+        return std::make_shared<DDR4Configuration>(tdb);
+
     } else {
         // TODO maybe throw?
         throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
@@ -53,7 +56,11 @@ const std::vector<QString> ConfigurationFactory::possiblePhases(const TraceDB& t
     const QString deviceName = ConfigurationIF::getDeviceName(tdb);
     
     if (deviceName == "DDR3") {
-        return DDR3TimeDependencies::getPossiblePhases();
+        // return DDR3TimeDependencies::getPossiblePhases();
+        return TimeDependenciesInfoDDR3::getPossiblePhases();
+
+    } else if (deviceName == "DDR4") {
+        return TimeDependenciesInfoDDR4::getPossiblePhases();
 
     } else {
         // TODO maybe throw?
@@ -70,6 +77,9 @@ bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) {
     if (deviceName == "DDR3") {
         return true;
 
+    } else if (deviceName == "DDR4") {
+        return true;
+
     } else {
         return false;
     }
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h
index d3d4fb08..c38877f5 100644
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h
@@ -39,6 +39,7 @@
 
 #include "configurationIF.h"
 #include "specialized/DDR3Configuration.h"
+#include "specialized/DDR4Configuration.h"
 #include "data/tracedb.h"
 
 class ConfigurationFactory {
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp
new file mode 100644
index 00000000..ce696152
--- /dev/null
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp
@@ -0,0 +1,11 @@
+
+#include "DDR4Configuration.h"
+
+DDR4Configuration::DDR4Configuration(const TraceDB& tdb) {
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoDDR4>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryIF> DDR4Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    return std::make_shared<DDR4DBPhaseEntry>(query);
+}
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h
new file mode 100644
index 00000000..992e8df2
--- /dev/null
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h
@@ -0,0 +1,14 @@
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationIF.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h"
+
+class DDR4Configuration : public ConfigurationIF {
+ public:
+    DDR4Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryIF> makePhaseEntry(const QSqlQuery&) const override;
+
+};
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryTypes.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryTypes.h
deleted file mode 100644
index 1a809fa7..00000000
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryTypes.h
+++ /dev/null
@@ -1,5 +0,0 @@
-
-#pragma once
-
-#include "dbphaseentryIF.h"
-#include "specialized/DDR3dbphaseentry.h"
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp
new file mode 100644
index 00000000..611ac9b7
--- /dev/null
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp
@@ -0,0 +1,45 @@
+
+#include "DDR4dbphaseentry.h"
+
+DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryIF> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<DDR4DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+
+    bool const skipOnIntraBankAndDifferentBanks = {
+        dep.depType == DependencyType::IntraBank 
+        && tBank != other->tBank
+    };
+    bool const skipOnIntraBankgroupAndDifferentBankgroup = {
+        dep.depType == DependencyType::IntraBankGroup
+        && tBankgroup != other->tBankgroup
+    };
+    bool const skipOnIntraRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraRank 
+        && tRank != other->tRank
+    };
+    bool const skipOnInterRankAndSameRank = {
+        dep.depType == DependencyType::InterRank
+        && tRank == other->tRank
+        && !isCmdPool
+    };
+    
+    return !(
+        skipOnIntraBankAndDifferentBanks
+        || skipOnIntraBankgroupAndDifferentBankgroup
+        || skipOnIntraRankAndDifferentRanks 
+        || skipOnInterRankAndSameRank
+    );
+}
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h
new file mode 100644
index 00000000..7f53fe6c
--- /dev/null
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h
@@ -0,0 +1,14 @@
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryIF.h"
+
+class DDR4DBPhaseEntry : public DBPhaseEntryIF {
+ public:
+    DDR4DBPhaseEntry(const QSqlQuery&);
+
+    size_t tBankgroup;
+    size_t tRank;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryIF> otherPhase) const override;
+};
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.cpp
index 420fdde3..df67097c 100644
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.cpp
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.cpp
@@ -65,7 +65,6 @@ DRAMTimeDependenciesIF::getDependencies(std::vector<QString>& dependencyFilter)
         ++it;
     }
 
-
     return dependenciesMap;
 }
 
@@ -141,10 +140,10 @@ void DRAMTimeDependenciesIF::mFilterDependencyMap(DependencyMap& dependencyMap,
                 dependencyMap.erase(pair.second, dependencyMap.end());
                 break;
 
-            } else if (*(pair.first) < pair.second->first < 0) {
+            } else if (*(pair.first) < pair.second->first) {
                 ++(pair.first);
 
-            } else if (*(pair.first) == pair.second->first == 0) {
+            } else if (*(pair.first) == pair.second->first) {
                 ++(pair.second);
 
             } else {
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp
new file mode 100644
index 00000000..287239af
--- /dev/null
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp
@@ -0,0 +1,387 @@
+/* Generated by JetBrains MPS */
+
+#include "TimeDependenciesInfoDDR4.h"
+
+using namespace std;
+
+TimeDependenciesInfoDDR4::TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesIF(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoDDR4::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        "ACT",
+        "RD",
+        "WR",
+        "PREPB",
+        "RDA",
+        "WRA",
+        "REFAB",
+        "PREAB",
+        "PDEP",
+        "PDXP",
+        "SREFEN",
+        "SREFEX",
+        "PDEA",
+        "PDXA",
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        "ACT",
+      }
+    }
+  });
+
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
+  tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
+  tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
+  tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
+  tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt();
+  tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt();
+  tRRD_S = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S"].toInt();
+  tRRD_L = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+  tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
+  tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+  tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
+  tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
+  tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+  tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+
+  tPD = tCKE;
+  tRFC = tCK * (
+    (mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 4) ?
+      (mMemspecJson["memtimingspec"].toObject()["RFC4"].toInt(1)) :
+      (
+        (mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 2) ?
+          (mMemspecJson["memtimingspec"].toObject()["RFC2"].toInt(1)) :
+          (mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(1))
+      )
+    );
+                   
+  tBURST = (uint) (burstLength / (float) dataRate) * tCK;
+  tRDWR = tRL + tBURST + tCK - tWL + tWPRE;
+  tRDWR_R = tRL + tBURST + tRTRS - tWL + tWPRE;
+  tWRRD_S = tWL + tBURST + tWTR_S - tAL;
+  tWRRD_L = tWL + tBURST + tWTR_L - tAL;
+  tWRRD_R = tWL + tBURST + tRTRS - tRL + tRPRE;
+  tRDAACT = tAL + tRTP + tRP;
+  tWRPRE = tWL + tBURST + tWR;
+  tWRAACT = tWRPRE + tRP;
+  tRDPDEN = tRL + tBURST + tCK;
+  tWRPDEN = tWL + tBURST + tWR;
+  tWRAPDEN = tWL + tBURST + tWR + tCK;
+
+}
+
+const std::vector<QString> TimeDependenciesInfoDDR4::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+  };
+}
+
+DependencyMap TimeDependenciesInfoDDR4::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+        {tRRD_L, "ACT", DependencyType::IntraBankGroup, "tRRD_L"},
+        {tRRD_S, "ACT", DependencyType::IntraRank, "tRRD_S"},
+        {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
+        {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
+        {tRP, "PREPB", DependencyType::IntraBank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"},
+        {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tWRRD_L, "WR", DependencyType::IntraBank, "tWRRD_L"},
+        {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"},
+        {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraBank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"},
+        {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {max({tWRRD_L, tWRPRE - tRTP - tAL}), "WR", DependencyType::IntraBank, "max(tWRRD_L, tWRPRE - tRTP - tAL)"},
+        {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"},
+        {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {tRDAACT, "RDA", DependencyType::IntraRank, "tRDAACT"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraRank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"},
+        {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+        {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+        {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEP", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"},
+        {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEA", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  return dmap;
+}
diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h
new file mode 100644
index 00000000..5b89e31a
--- /dev/null
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h
@@ -0,0 +1,66 @@
+/* Generated by JetBrains MPS */
+
+#pragma once
+
+#include "../dramtimedependenciesIF.h"
+
+class TimeDependenciesInfoDDR4 final : public DRAMTimeDependenciesIF {
+  public:
+    TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tRCD;
+    uint tRP;
+    uint tRAS;
+    uint tRC;
+    uint tCL;
+    uint tCWL;
+    uint tAL;
+    uint tRL;
+    uint tRPRE;
+    uint tWPRE;
+    uint tWL;
+    uint tCCD_S;
+    uint tCCD_L;
+    uint tRRD_S;
+    uint tRRD_L;
+    uint tFAW;
+    uint tWTR_S;
+    uint tWTR_L;
+    uint tRTP;
+    uint tWR;
+    uint tRFC;
+    uint tXS;
+    uint tXSDLL;
+    uint tXP;
+    uint tCKE;
+    uint tCKESR;
+    uint tPD;
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tREFPDEN;
+    uint tRTRS;
+
+    uint tBURST;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD_S;
+    uint tWRRD_L;
+    uint tWRRD_R;
+    uint tRDAACT;
+    uint tWRPRE;
+    uint tWRAACT;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+};