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Merge branch 'feat/remove_resource_directory' into 'develop'

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Remove the concept of a resource directory

See merge request ems/astdm/modeling.dram/dram.sys.5!115
This commit is contained in:
Lukas Steiner
2025-04-24 14:12:23 +00:00
parent 0f2be6ece5 939fc90f98
commit 1863987af3
41 changed files with 92 additions and 330 deletions
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22
tests/tests_regression/CMakeLists.txt
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@@ -48,7 +48,7 @@ set(TABLES_TO_COMPARE
Power
)
function(test_standard standard test_name base_config resource_dir output_filename)
function(test_standard standard test_name base_config output_filename)
if(NOT IS_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/${standard})
message(WARNING "Cannot find regression test ${standard}")
return()
@@ -61,7 +61,7 @@ function(test_standard standard test_name base_config resource_dir output_filena
add_test(
NAME Regression${test_name}.CreateDatabase
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name}
COMMAND $<TARGET_FILE:DRAMSys> ${base_config} ${resource_dir}
COMMAND $<TARGET_FILE:DRAMSys> ${base_config}
)
set_tests_properties(Regression${test_name}.CreateDatabase PROPERTIES FIXTURES_SETUP Regression${test_name}.CreateDatabase)
@@ -89,12 +89,12 @@ function(test_standard standard test_name base_config resource_dir output_filena
endforeach()
endfunction()
test_standard(DDR3 DDR3 ${CMAKE_CURRENT_SOURCE_DIR}/DDR3/ddr3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR3 DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb)
test_standard(DDR4 DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR4 DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb)
test_standard(DDR5 DDR5.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch0.tdb)
test_standard(DDR5 DDR5.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch1.tdb)
test_standard(LPDDR4 LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4 DRAMSys_lpddr4-example_lpddr4_ch0.tdb)
test_standard(LPDDR5 LPDDR5 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5/lpddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5 DRAMSys_lpddr5-example_lpddr5_ch0.tdb)
test_standard(HBM2 HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch0.tdb)
test_standard(HBM2 HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch1.tdb)
test_standard(HBM3 HBM3 ${CMAKE_CURRENT_SOURCE_DIR}/HBM3/hbm3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM3 DRAMSys_hbm3-example_hbm3_ch0.tdb)
test_standard(DDR3 DDR3 ${CMAKE_CURRENT_SOURCE_DIR}/DDR3/ddr3-example.json DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb)
test_standard(DDR4 DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb)
test_standard(DDR5 DDR5.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json DRAMSys_ddr5-example_ddr5_ch0.tdb)
test_standard(DDR5 DDR5.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json DRAMSys_ddr5-example_ddr5_ch1.tdb)
test_standard(LPDDR4 LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json DRAMSys_lpddr4-example_lpddr4_ch0.tdb)
test_standard(LPDDR5 LPDDR5 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5/lpddr5-example.json DRAMSys_lpddr5-example_lpddr5_ch0.tdb)
test_standard(HBM2 HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json DRAMSys_hbm2-example_hbm2_ch0.tdb)
test_standard(HBM2 HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json DRAMSys_hbm2-example_hbm2_ch1.tdb)
test_standard(HBM3 HBM3 ${CMAKE_CURRENT_SOURCE_DIR}/HBM3/hbm3-example.json DRAMSys_hbm3-example_hbm3_ch0.tdb)

2
tests/tests_regression/DDR3/ddr3-example.json
View File

@@ -135,7 +135,7 @@
"tracesetup": [
{
"clkMhz": 533,
"name": "trace_test2.stl"
"name": "traces/trace_test2.stl"
}
]
}

2
tests/tests_regression/DDR4/ddr4-example.json
View File

@@ -146,7 +146,7 @@
"tracesetup": [
{
"clkMhz": 933,
"name": "trace_test3.stl"
"name": "traces/trace_test3.stl"
}
]
}

2
tests/tests_regression/DDR5/ddr5-example.json
View File

@@ -158,7 +158,7 @@
"tracesetup": [
{
"clkMhz": 1600,
"name": "trace_test3.stl"
"name": "traces/trace_test3.stl"
}
]
}

4
tests/tests_regression/HBM2/hbm2-example.json
View File

@@ -126,11 +126,11 @@
"tracesetup": [
{
"clkMhz": 1000,
"name": "trace1_test4.stl"
"name": "traces/trace1_test4.stl"
},
{
"clkMhz": 1000,
"name": "trace2_test4.stl"
"name": "traces/trace2_test4.stl"
}
]
}

0
tests/tests_regression/HBM2/hbm2.txt
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4
tests/tests_regression/HBM3/hbm3-example.json
View File

@@ -129,11 +129,11 @@
"tracesetup": [
{
"clkMhz": 1600,
"name": "trace1_test4.stl"
"name": "traces/trace1_test4.stl"
},
{
"clkMhz": 1600,
"name": "trace2_test4.stl"
"name": "traces/trace2_test4.stl"
}
]
}

2
tests/tests_regression/LPDDR4/lpddr4-example.json
View File

@@ -123,7 +123,7 @@
"tracesetup": [
{
"clkMhz": 1600,
"name": "trace_lpddr4.stl"
"name": "traces/trace_lpddr4.stl"
}
]
}

2
tests/tests_regression/LPDDR5/lpddr5-example.json
View File

@@ -134,7 +134,7 @@
"tracesetup": [
{
"clkMhz": 1600,
"name": "trace_lpddr5.stl"
"name": "traces/trace_lpddr5.stl"
}
]
}