diff --git a/dram/src/common/Utils.cpp b/dram/src/common/Utils.cpp index 82a96635..8b9af361 100644 --- a/dram/src/common/Utils.cpp +++ b/dram/src/common/Utils.cpp @@ -41,7 +41,7 @@ std::string phaseNameToString(tlm::tlm_phase phase) unsigned int queryUIntParameter(XMLElement* node, string name) { - int result; + int result = 0; XMLElement* element; for (element = node->FirstChildElement("parameter"); element != NULL; element = element->NextSiblingElement("parameter")) @@ -49,8 +49,7 @@ unsigned int queryUIntParameter(XMLElement* node, string name) if (element->Attribute("id") == name) { sc_assert(!strcmp(element->Attribute("type"), "uint")); - XMLError error = element->QueryIntAttribute("value", &result); - sc_assert(!error); + sc_assert(element->QueryIntAttribute("value", &result) == XML_NO_ERROR); return result; } } @@ -75,7 +74,7 @@ bool parameterExists(tinyxml2::XMLElement* node, std::string name) double queryDoubleParameter(XMLElement* node, string name) { - double result; + double result = 0; XMLElement* element; for (element = node->FirstChildElement("parameter"); element != NULL; element = element->NextSiblingElement("parameter")) @@ -83,8 +82,7 @@ double queryDoubleParameter(XMLElement* node, string name) if (element->Attribute("id") == name) { sc_assert(!strcmp(element->Attribute("type"), "double")); - XMLError error = element->QueryDoubleAttribute("value", &result); - sc_assert(!error); + sc_assert(element->QueryDoubleAttribute("value", &result) == XML_NO_ERROR); return result; } } @@ -95,7 +93,7 @@ double queryDoubleParameter(XMLElement* node, string name) bool queryBoolParameter(XMLElement* node, string name) { - bool result; + bool result = false; XMLElement* element;// = node->FirstChildElement("parameter"); for (element = node->FirstChildElement("parameter"); element != NULL; element = element->NextSiblingElement("parameter")) @@ -103,8 +101,7 @@ bool queryBoolParameter(XMLElement* node, string name) if (element->Attribute("id") == name) { sc_assert(!strcmp(element->Attribute("type"), "bool")); - XMLError error = element->QueryBoolAttribute("value", &result); - sc_assert(!error); + sc_assert(element->QueryBoolAttribute("value", &result) == XML_NO_ERROR); return result; } } @@ -151,7 +148,7 @@ string errorToString(XMLError error) case XML_ERROR_PARSING: return "ERROR_PARSING"; case XML_CAN_NOT_CONVERT_TEXT: return "CAN_NOT_CONVERT_TEXT"; case XML_NO_TEXT_NODE: return "NO_TEXT_NODE"; - default: ""; + default: return ""; } } diff --git a/dram/src/controller/core/refresh/RefreshManager.cpp b/dram/src/controller/core/refresh/RefreshManager.cpp index 2953e766..2b7ed16c 100644 --- a/dram/src/controller/core/refresh/RefreshManager.cpp +++ b/dram/src/controller/core/refresh/RefreshManager.cpp @@ -32,7 +32,7 @@ bool RefreshManager::hasCollision(const ScheduledCommand& command) return command.getStart() < controllerCore.state.getLastCommand(Command::AutoRefresh).getEnd() || command.getEnd() > nextPlannedRefresh; } -void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time) +void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload __attribute((unused)), sc_time time) { sc_assert(!isInvalidated(payload, time)); @@ -78,7 +78,7 @@ void RefreshManager::reInitialize(Bank /*bank*/, sc_time time) planNextRefresh(); } -bool RefreshManager::isInvalidated(tlm::tlm_generic_payload& payload, sc_time time) +bool RefreshManager::isInvalidated(tlm::tlm_generic_payload& payload __attribute((unused)), sc_time time) { return nextPlannedRefresh > time; } diff --git a/dram/src/controller/core/scheduling/checker/WriteChecker.cpp b/dram/src/controller/core/scheduling/checker/WriteChecker.cpp index 1d5321af..04de71ea 100644 --- a/dram/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -87,7 +87,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand& firstWrite, ScheduledComman return max(tCCD, getWriteAccessTime()); } -sc_time WriteChecker::readToWrite(ScheduledCommand& read, ScheduledCommand& write) +sc_time WriteChecker::readToWrite(ScheduledCommand& read __attribute__((unused)), ScheduledCommand& write __attribute__((unused))) { sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); diff --git a/dram/src/simulation/Simulation.cpp b/dram/src/simulation/Simulation.cpp index 7cbf8851..6cf56175 100644 --- a/dram/src/simulation/Simulation.cpp +++ b/dram/src/simulation/Simulation.cpp @@ -21,7 +21,7 @@ using namespace std; -Simulation::Simulation(sc_module_name __attribute__((__unused__)) name, string pathToResources, string traceName, DramSetup setup, +Simulation::Simulation(sc_module_name __attribute__((unused)) name, string pathToResources, string traceName, DramSetup setup, std::vector devices) : traceName(traceName), dramSetup(setup)