diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp
index de402431..91967821 100644
--- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp
+++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp
@@ -269,14 +269,22 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
     memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
     memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
     memSpec->tFAW   = clk * queryUIntParameter(timings, "FAW");
-    memSpec->tREFI  = clk * queryUIntParameter(timings, "REFI");
     unsigned refMode = Configuration::getInstance().getRefMode();
     if (refMode == 1)
+    {
+        memSpec->tREFI  = clk * queryUIntParameter(timings, "REFI");
         memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
+    }
     else if (refMode == 2)
+    {
+        memSpec->tREFI  = clk * (queryUIntParameter(timings, "REFI") / 2);
         memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2");
+    }
     else if (refMode == 4)
+    {
+        memSpec->tREFI  = clk * (queryUIntParameter(timings, "REFI") / 2);
         memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4");
+    }
     else
         SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
     memSpec->tRP    = clk * queryUIntParameter(timings, "RP");
diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py
index 7b874c6b..c82dbc81 100755
--- a/DRAMSys/traceAnalyzer/scripts/tests.py
+++ b/DRAMSys/traceAnalyzer/scripts/tests.py
@@ -39,9 +39,7 @@ class DramConfig(object):
     tXS = 0        # min delay to row access command after srefx
     tXSDLL = 0     # min delay to row access command after srefx for dll commands
     tAL = 0         # additive delay (delayed execution in dram)
-    tRFC = 0        # min ref->act delay 1X
-    tRFC2 = 0       # min ref->act delay 2X
-    tRFC4 = 0       # min ref->act delay 4X
+    tRFC = 0        # min ref->act delay
     tREFI = 0       # time between REF commands
 
     def readConfigFromFiles(self, connection):
@@ -114,10 +112,15 @@ class DramConfig(object):
             self.tXS = self.clk * memspec.getIntValue("XS")
             self.tXSDLL = self.clk * memspec.getIntValue("XSDLL")
             self.tAL = self.clk * memspec.getIntValue("AL")
-            self.tRFC = self.clk * memspec.getIntValue("RFC")
-            self.tRFC2 = self.clk * memspec.getIntValue("RFC2")
-            self.tRFC4 = self.clk * memspec.getIntValue("RFC4")
-            self.tREFI = self.clk * memspec.getIntValue("REFI")
+            if (self.refMode == "4"):
+                self.tRFC = self.clk * memspec.getIntValue("RFC4")
+                self.tREFI = self.clk * (memspec.getIntValue("REFI") / 4)
+            elif (self.refMode == "2"):
+                self.tRFC = self.clk * memspec.getIntValue("RFC2")
+                self.tREFI = self.clk * (memspec.getIntValue("REFI") / 2)
+            else:
+                self.tRFC = self.clk * memspec.getIntValue("RFC")
+                self.tREFI = self.clk * memspec.getIntValue("REFI")
 
         elif (self. memoryType == "DDR3"):
             self.nActivateWindow = 4
@@ -358,12 +361,7 @@ def timing_constraint(FirstPhase, SecondPhase):
             return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR + dramconfig.clk
 
     elif (FirstPhaseName == "REFA"):
-        if dramconfig.refMode == "4":
-            return dramconfig.tRFC4
-        elif dramconfig.refMode == "2":
-            return dramconfig.tRFC2
-        else:
-            return dramconfig.tRFC
+        return dramconfig.tRFC
 
     elif (FirstPhaseName in ["PDNA", "PDNP"]):
         # print("{0}".format(FirstPhaseName))