Fix various bugs

- Fix data race for some tests by disabling database recording
- Fix undefined behaviour in configuration test
- Port clkMhz to tCK for simulation script
- Port memUtil Python script to tCK with backwards compatibility
This commit is contained in:
2024-02-26 09:58:19 +01:00
parent 41f683619d
commit 12bfba1fb3
5 changed files with 12 additions and 4 deletions

View File

@@ -108,7 +108,14 @@ def maximum_data_rate(connection):
width = memspec.getIntValue("memarchitecturespec", "nbrOfDevices") * memspec.getIntValue("memarchitecturespec", "width")
except:
width = memspec.getIntValue("memarchitecturespec", "width")
# Backwards compatibility for traces where clkMHz was not yet replaced with tCK
clk = None
try:
clk = 1000000 / memspec.getIntValue("memtimingspec", "tCK")
except:
clk = memspec.getIntValue("memtimingspec", "clkMhz")
rate = memspec.getIntValue("memarchitecturespec", "dataRate")
if getPseudoChannelMode(connection):
maxDataRate = float(clk) * float(width) * float(rate) * 2

View File

@@ -111,7 +111,7 @@
"XPDLL": 20,
"XS": 96,
"XSDLL": 512,
"clkMhz": 800
"tCK": 1250
}
},
"simconfig": {

View File

@@ -75,6 +75,7 @@ protected:
addressMapBitVector({13, 14, 15}),
addressMapBitVector({17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}),
addressMapBitVector({33}),
std::nullopt,
std::nullopt};
DRAMSys::Config::McConfig mcConfig{PagePolicyType::Open,

View File

@@ -135,7 +135,7 @@
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"DatabaseRecording": false,
"Debug": false,
"EnableWindowing": false,
"PowerAnalysis": false,

View File

@@ -133,7 +133,7 @@
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"DatabaseRecording": false,
"Debug": false,
"EnableWindowing": false,
"PowerAnalysis": false,