From 1053f7c1b7bac823ab5afec1fdeb1716ddab2f4c Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 30 Jul 2019 16:03:49 +0200 Subject: [PATCH] Created CheckerIF, removed old CheckerDDR3. --- DRAMSys/library/library.pro | 8 +- .../src/controller/checker/CheckerIF.cpp | 2 + .../src/controller/checker/CheckerIF.h | 64 ++ .../src/controller/core/ControllerCore.cpp | 1 - .../core/scheduling/checker/CheckerDDR3.cpp | 561 ------------------ .../core/scheduling/checker/CheckerDDR3.h | 58 -- .../core/scheduling/checker/CheckerDDR3New.h | 1 - 7 files changed, 70 insertions(+), 625 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerIF.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerIF.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index c7ddd020..386605e1 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -147,7 +147,6 @@ SOURCES += \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ - src/controller/core/scheduling/checker/CheckerDDR3.cpp \ src/controller/core/configuration/MemSpec.cpp \ src/controller/core/scheduling/checker/CheckerDDR3New.cpp \ src/controller/BankMachine.cpp \ @@ -156,7 +155,8 @@ SOURCES += \ src/controller/scheduler/SchedulerFrFcfs.cpp \ src/controller/cmdmux/CmdMuxStrict.cpp \ src/controller/cmdmux/CmdMuxOldest.cpp \ - src/controller/ControllerRecordable.cpp + src/controller/ControllerRecordable.cpp \ + src/controller/checker/CheckerIF.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -237,7 +237,6 @@ HEADERS += \ src/simulation/DramDDR4.h \ src/simulation/DramRecordable.h \ src/simulation/DramWideIO.h \ - src/controller/core/scheduling/checker/CheckerDDR3.h \ src/controller/GenericController.h \ src/controller/core/scheduling/checker/CheckerDDR3New.h \ src/controller/BankMachine.h \ @@ -248,7 +247,8 @@ HEADERS += \ src/controller/cmdmux/CmdMuxIF.h \ src/controller/cmdmux/CmdMuxStrict.h \ src/controller/cmdmux/CmdMuxOldest.h \ - src/controller/ControllerRecordable.h + src/controller/ControllerRecordable.h \ + src/controller/checker/CheckerIF.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.cpp b/DRAMSys/library/src/controller/checker/CheckerIF.cpp new file mode 100644 index 00000000..fd5f6059 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerIF.cpp @@ -0,0 +1,2 @@ +#include "CheckerIF.h" + diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h new file mode 100644 index 00000000..015a1cd8 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERIF_H +#define CHECKERIF_H + +#include +#include +#include "../core/scheduling/ScheduledCommand.h" +#include "../Command.h" +#include "../../common/dramExtensions.h" +#include "../../common/DebugManager.h" + +class CheckerIF +{ +public: + virtual ~CheckerIF() {} + + virtual sc_time delayToSatisfyConstraints(Command, Bank) = 0; + virtual void insert(const ScheduledCommand &) = 0; + +protected: + std::map> lastScheduledByCommandAndBank; + std::map lastScheduledByCommand; + ScheduledCommand lastScheduled; + + void printDebugMessage(std::string message) + { + DebugManager::getInstance().printDebugMessage("Checker", message); + } +}; + +#endif // CHECKERIF_H diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 8b5c87ab..c9d46587 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -52,7 +52,6 @@ #include "../../common/dramExtensions.h" #include "../../common/utils.h" #include "timingCalculations.h" -#include "scheduling/checker/CheckerDDR3.h" #include "scheduling/checker/CheckerDDR3New.h" #include "powerdown/PowerDownManager.h" diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp deleted file mode 100644 index 94ac3ffb..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ /dev/null @@ -1,561 +0,0 @@ -#include "CheckerDDR3.h" - -#include -#include -#include -#include -#include "../../timingCalculations.h" -#include "../../../../common/DebugManager.h" -#include "../../../Command.h" -#include "../../../../common/utils.h" - -using namespace std; - -void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const -{ - ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); - Command lastCmd = lastCommandOnBank.getCommand(); - Command nextCmd = command.getCommand(); - - if (nextCmd == Command::ACT) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - default: - reportFatal("Checker DDR3", - "Activate can not follow " + commandToString(lastCmd)); - } - } - - delay_to_satisfy_activateToActivate_sameBank(command); - - while (!(state.bus.isFree(command.getStart()) && - satsfies_activateToActivate_differentBank(command) && satisfies_nActivateWindow(command))) - { - command.delayStart(memSpec->clk); - } - } - else if (nextCmd == Command::RD || nextCmd == Command::RDA) - { - delayToSatisfyDLL(command); - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - CasToCas(lastCommandOnBank, command)); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - writeToRead(lastCommandOnBank, command)); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("Checker DDR3", - "Read can not follow " + commandToString(lastCmd) + "First: Activate!"); - } - } - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::WR || nextCmd == Command::WRA) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - readToWrite(lastCommandOnBank, command)); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - CasToCas(lastCommandOnBank, command)); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("Checker DDR3", "Write can not follow " + commandToString(lastCmd)); - } - } - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::PRE) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->tWR - + memSpec->getWriteAccessTime()); - break; - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("Checker DDR3", - "Precharge can not follow " + commandToString(lastCmd)); - } - } - ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); - if (lastActivate.isValidCommand()) - command.establishMinDistanceFromStart(lastActivate.getStart(), - memSpec->tRAS); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PREA) - { - for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) - { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - if (lastCommand.isValidCommand()) - { - switch (lastCommand.getCommand()) - { - case Command::PRE: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::PDXA: - case Command::PDXP: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC_old); - break; - default: - reportFatal("Checker_DDR3", - "Precharge All can not follow " + commandToString(lastCmd)); - } - } - } - ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); - if (lastActivate.isValidCommand()) - command.establishMinDistanceFromStart(lastActivate.getStart(), - memSpec->tRAS); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDEA || nextCmd == Command::PDEP || nextCmd == Command::SREFEN ) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RD: - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRL + memSpec->getReadAccessTime() - + memSpec->clk); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->clk); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXA: - case Command::PDXP: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - default: - reportFatal("Checker DDR3", commandToString(nextCmd) + " can not follow " - + commandToString(lastCmd) + ".First: Precharge!"); - } - } - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDXA) - { - // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, - command.getBank()).getStart(), memSpec->tCKE); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDXP) - { - // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, - command.getBank()).getStart(), memSpec->tCKE); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::SREFEX) - { - // Leaving Self Refresh - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, - command.getBank()).getStart(), memSpec->tCKESR); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::REFA) - { - if (config.BankwiseLogic) { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - default: - reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(lastCmd)); - } - } - } - else - { - for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) - { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - - if (lastCommand.isValidCommand()) - { - switch (lastCommand.getCommand()) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRCD); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); - break; - default: - reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(lastCmd)); - } - } - } - } - state.bus.moveCommandToNextFreeSlot(command); - } -} - -/* -* ActivateChecker -*/ - -void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const -{ - ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, command.getBank()); - if (lastActivateOnBank.isValidCommand()) - command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); -} - -bool CheckerDDR3::satsfies_activateToActivate_differentBank(ScheduledCommand &command) const -{ -// for (auto act : state.lastActivates) -// { -// sc_time time = act.first; -// if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) -// || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) -// return false; -// } - return true; - -} - -bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const -{ - /* - * there may be activates scheduled in the future, so emplace - * command in a copied set (not necessarily the last in time), - * and check if the n-act constraint holds for the whole set. - */ -// if (state.lastActivates.size() >= memSpec->nActivate) -// { -// std::map lastActivates = state.lastActivates; -// lastActivates.emplace(command.getStart(), command); -// auto upper = lastActivates.begin(); -// std::advance(upper, memSpec->nActivate); -// auto lower = lastActivates.begin(); - -// while (upper != lastActivates.end()) -// { -// if (upper->first - lower->first < memSpec->tNAW_old) -// return false; -// upper++; -// lower++; -// } -// } - return true; -} - - -/* - * Read-Checker -*/ - -bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const -{ -// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) -// { -// if (collidesWithStrobeCommand_RD(read, strobeCommand)) -// return true; -// } - return false; -} - -bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - return getDistance(read.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, read); - } - else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - if (strobeCommand.getStart() >= read.getStart()) - return getDistance(read.getStart(), - strobeCommand.getStart()) < readToWrite(read, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - read.getStart()) < writeToRead(strobeCommand, read); - } else { - reportFatal("Checker DDR3", - "Invalid strobeCommand in data strobe commands " + commandToString( - strobeCommand.getCommand())); - return true; - } - return false; -} - - -void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const -{ - ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, read.getBank()); - if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); -} - - -sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const -{ - sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA); - - return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; -} - -/* CAS-CAS */ - -sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const -{ - if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA) - { - if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA) - return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); - } - else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA) - { - if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA) - return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); - } - SC_REPORT_FATAL("CasToCas", "Exception reached"); - return SC_ZERO_TIME; -} - -/* -* Write-Checker -*/ - -bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const -{ -// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) -// { -// if (collidesWithStrobeCommand_WR(write, strobeCommand)) -// return true; -// } - return false; -} - -bool CheckerDDR3::collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - // TODO: Cast from sc_time to bool? - return getDistance(write.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, write); - } - else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - if (strobeCommand.getStart() >= write.getStart()) - return getDistance(write.getStart(), - strobeCommand.getStart()) < writeToRead(write, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - write.getStart()) < readToWrite(strobeCommand, write); - } - else - { - reportFatal("CheckerDDR3", "Invalid strobeCommand in data strobe commands " - + commandToString(strobeCommand.getCommand())); - return true; - } -} - - -sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const -{ - sc_assert(read.getCommand() == Command::RD - || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR - || write.getCommand() == Command::WRA); - - return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h deleted file mode 100644 index 28baca01..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef CHECKERDDR3_H -#define CHECKERDDR3_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -//Activate -class CheckerDDR3 : public ICommandChecker -{ -public: - CheckerDDR3(const Configuration &config, - ControllerState &state) : config(config), state(state) - { - memSpec = dynamic_cast(Configuration::getInstance().memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - } - virtual ~CheckerDDR3() {} - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const override; - -private: - MemSpecDDR3 *memSpec; - - //Activate - void delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const; - bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const; - bool satisfies_nActivateWindow(ScheduledCommand &command) const; - - //PowerDown - sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; - - //used for Read - void delayToSatisfyDLL(ScheduledCommand &read) const; - bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; - bool collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const; - - //Write - bool collidesOnDataStrobe_WR(ScheduledCommand &write) const; - bool collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const; - - //handles WR->RD - sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const; - - //RD->WR - sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const; - - //CasToCas Commands (WR->WR)(RD->RD) - sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const; - - const Configuration &config; - ControllerState &state;//TODO make const -}; - -#endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 81b50295..085104e6 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -44,7 +44,6 @@ #include "../../../Command.h" #include "../../../../common/dramExtensions.h" -//Activate class CheckerDDR3New { public: