diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 54a20c85..d4bb25a2 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -32,7 +32,7 @@ tlm_generic_payload *BankMachine::getNextStateAndResult() return payloadToReturn; } -void BankMachine::startBankMachine(sc_time minDelay) +void BankMachine::startBankMachine() { if (currentPayload == nullptr) { @@ -42,7 +42,7 @@ void BankMachine::startBankMachine(sc_time minDelay) } if (currentState == BmState::Precharged) { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::ACT, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::ACT, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 1"); nextCommand = Command::ACT; timeToSchedule = sc_time_stamp() + delay; @@ -50,18 +50,18 @@ void BankMachine::startBankMachine(sc_time minDelay) else if (currentState == BmState::Activated) { DramExtension extension = DramExtension::getExtension(currentPayload); - if (extension.getRow() == currentRow) + if (extension.getRow() == currentRow) // row hit { if (currentPayload->get_command() == TLM_READ_COMMAND) { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::RD, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::RD, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 2"); nextCommand = Command::RD; timeToSchedule = sc_time_stamp() + delay; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::WR, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::WR, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 3"); nextCommand = Command::WR; timeToSchedule = sc_time_stamp() + delay; @@ -69,9 +69,9 @@ void BankMachine::startBankMachine(sc_time minDelay) else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - else + else // row miss { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::PRE, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::PRE, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 4"); nextCommand = Command::PRE; timeToSchedule = sc_time_stamp() + delay; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 08e029f8..0d02269f 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -29,7 +29,7 @@ public: BankMachine(ControllerNew *, SchedulerNew *, CheckerDDR3New*, Bank); void setCommandFinishedTime(sc_time); tlm_generic_payload *getNextStateAndResult(); - void startBankMachine(sc_time minDelay); + void startBankMachine(); std::pair getNextCommand(); void updateState(Command); private: diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 65d290a5..7aee2d15 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -17,26 +17,30 @@ void CommandMux::selectCommand() if (result.first != Command::NOP) readyCommands.push_back(result); } - for (auto it : readyCommands) + if (!readyCommands.empty()) { - if (it.first == Command::ACT || it.first == Command::PRE) + for (auto it : readyCommands) { - controller->sendToDram(it.first, it.second); - readyCommands.clear(); - return; - } - } - for (auto it : readyCommands) - { - if (it.first == Command::RD || it.first == Command::WR) - { - if (it.second == payloadOrder.front()) + if (it.first == Command::ACT || it.first == Command::PRE) { - payloadOrder.pop(); controller->sendToDram(it.first, it.second); readyCommands.clear(); return; } } + for (auto it : readyCommands) + { + if (it.first == Command::RD || it.first == Command::WR) + { + if (it.second == payloadOrder.front()) + { + payloadOrder.pop(); + controller->sendToDram(it.first, it.second); + readyCommands.clear(); + return; + } + } + } + readyCommands.clear(); } } diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 3c591783..567f47d4 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -38,19 +38,19 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { recordPhase(trans, phase, delay); - sc_time notDelay = delay; + sc_time notificationDelay = delay; if (phase == BEGIN_REQ) { - notDelay += Configuration::getInstance().memSpec->clk; + notificationDelay += Configuration::getInstance().memSpec->clk; payloadToAcquire = &trans; - timeToAcquire = sc_time_stamp() + notDelay; + timeToAcquire = sc_time_stamp() + notificationDelay; } else if (phase = END_RESP) { // FIXME: synchronization! - notDelay += Configuration::getInstance().memSpec->clk; - timeToRelease = sc_time_stamp() + notDelay; + notificationDelay += Configuration::getInstance().memSpec->clk; + timeToRelease = sc_time_stamp() + notificationDelay; } else { @@ -59,13 +59,13 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, } printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + - notDelay.to_string()); - triggerEventQueueAfterDelay(notDelay, "nb_transport_fw"); + notificationDelay.to_string()); + triggerEventQueueAfterDelay(notificationDelay, "nb_transport_fw"); return TLM_ACCEPTED; } -unsigned int ControllerNew::transport_dbg(tlm_generic_payload &trans) +unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) { SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); return 0; @@ -134,7 +134,7 @@ void ControllerNew::controllerMethod() sendToFrontend(); startBankMachines(); commandMux->selectCommand(); - restartBankMachines(); + startBankMachines(); } } @@ -163,7 +163,7 @@ void ControllerNew::acquirePayload() numberOfPayloads++; // TODO: insert payload ID printDebugMessage("Payload ID entered system."); - payloadToAcquire->set_response_status(tlm::TLM_OK_RESPONSE); + payloadToAcquire->set_response_status(TLM_OK_RESPONSE); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; recordPhase(*payloadToAcquire, tPhase, tDelay); @@ -206,14 +206,7 @@ void ControllerNew::getNextBmStates() void ControllerNew::startBankMachines() { for (auto it : bankMachines) - it.second->startBankMachine(SC_ZERO_TIME); -} - -void ControllerNew::restartBankMachines() -{ - sc_time minDelay = Configuration::getInstance().memSpec->clk; - for (auto it : bankMachines) - it.second->startBankMachine(minDelay); + it.second->startBankMachine(); } void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) @@ -250,16 +243,3 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) iSocket->nb_transport_fw(*payload, phase, delay); } - - -//void CommandMux::compute() -//{ -// // Handling of backpressure from / to arbiter!!! - -// /* END_RESP from arbiter: check for successful transaction, remove payload from response queue, numberOfPayloads-- -// * END_RD / END_WR from DRAM: check for successful transaction, move payload from BM to response queue, send result to arbiter (delay??) -// * BEGIN_REQ from arbiter: check for transaction, move to scheduler map -// * Trigger by BM: get transactions from all BM, choose one, send one, change state on BM, postpone all BM to next point in time -// */ -//} - diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index d24429a1..0e54fd61 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -47,7 +47,7 @@ public: private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); - unsigned int transport_dbg(tlm_generic_payload &trans); + unsigned int transport_dbg(tlm_generic_payload &); tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); void printDebugMessage(string message); @@ -58,7 +58,6 @@ private: void getNextBmStates(); void sendToFrontend(); void startBankMachines(); - void restartBankMachines(); unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index a5d9d609..19cde85b 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -69,6 +69,7 @@ public: //used by the various checkers std::map > lastScheduledByCommandAndBank; + // TODO: remove std::map lastScheduledByCommand; std::map lastScheduledByBank; ScheduledCommand lastScheduled;