From 0b08a1a54caf355e43ec6a42634a58346b0ae330 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Wed, 9 Apr 2014 16:53:42 +0200 Subject: [PATCH] ss --- dram/src/common/TlmRecorder.cpp | 2 +- dram/src/core/ControllerState.cpp | 3 +- dram/src/core/configuration/MemSpecLoader.cpp | 2 +- .../core/scheduling/checker/ReadChecker.cpp | 10 ++++++- .../core/scheduling/checker/WriteChecker.cpp | 10 ++++++- dram/src/core/utils/Utils.cpp | 29 ++++++++++++++----- dram/src/core/utils/Utils.h | 2 ++ dram/src/simulation/main.cpp | 13 +++++---- 8 files changed, 52 insertions(+), 19 deletions(-) diff --git a/dram/src/common/TlmRecorder.cpp b/dram/src/common/TlmRecorder.cpp index 2cd6fa4f..9d3b0928 100644 --- a/dram/src/common/TlmRecorder.cpp +++ b/dram/src/common/TlmRecorder.cpp @@ -129,7 +129,7 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 1, transactionIDCounter - 1); sqlite3_bind_int64(insertGeneralInfoStatement, 2, recordingEndTime.value()); sqlite3_bind_int(insertGeneralInfoStatement, 3, - xmlAddressDecoder::getInstance().getNumberOfBanks()); + core::Configuration::getInstance().NumberOfBanks); sqlite3_bind_text(insertGeneralInfoStatement, 4, "", 0, NULL); sqlite3_bind_int(insertGeneralInfoStatement, 5, core::Configuration::getInstance().Timings.clk.value()); sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL); diff --git a/dram/src/core/ControllerState.cpp b/dram/src/core/ControllerState.cpp index d9848d82..c2cb15d0 100644 --- a/dram/src/core/ControllerState.cpp +++ b/dram/src/core/ControllerState.cpp @@ -7,6 +7,7 @@ #include "ControllerState.h" #include +#include "utils/Utils.h" namespace core { @@ -86,7 +87,7 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand) void ControllerState::cleanUp(sc_time time) { bus.cleanUpSlots(time); - lastDataStrobeCommands.remove_if([&](ScheduledCommand command){return command.getEnd() < time - config->Timings.tDataStrobeHistory();}); + lastDataStrobeCommands.remove_if([&](ScheduledCommand command){return command.getEnd() < time && getDistance(command.getEnd(), time) > config->Timings.tDataStrobeHistory();}); lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory())); } diff --git a/dram/src/core/configuration/MemSpecLoader.cpp b/dram/src/core/configuration/MemSpecLoader.cpp index b56d3674..6e0050f9 100644 --- a/dram/src/core/configuration/MemSpecLoader.cpp +++ b/dram/src/core/configuration/MemSpecLoader.cpp @@ -81,7 +81,7 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec) config.Timings.tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); config.Timings.tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); config.Timings.tRCD = clk * queryUIntParameter(timings, "RCD"); - config.Timings.tNAW = clk * queryUIntParameter(timings, "TAW"); + config.Timings.tNAW = clk * queryUIntParameter(timings, "FAW"); config.Timings.tRL = clk * queryUIntParameter(timings, "RL"); config.Timings.tWL = clk * queryUIntParameter(timings, "WL"); config.Timings.tWR = clk * queryUIntParameter(timings, "WR"); diff --git a/dram/src/core/scheduling/checker/ReadChecker.cpp b/dram/src/core/scheduling/checker/ReadChecker.cpp index e1e2d84e..58c4c95b 100644 --- a/dram/src/core/scheduling/checker/ReadChecker.cpp +++ b/dram/src/core/scheduling/checker/ReadChecker.cpp @@ -70,9 +70,17 @@ bool ReadChecker::collidesOnDataStrobe(ScheduledCommand& read) const bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand& read, ScheduledCommand& strobeCommand) const { + //read to read if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA) { - return getIntervalOnDataStrobe(read).intersects(getIntervalOnDataStrobe(strobeCommand)); + bool collision = getIntervalOnDataStrobe(read).intersects(getIntervalOnDataStrobe(strobeCommand)); + + sc_time tCCD = + (getBankGroup(read.getBank()) == getBankGroup(strobeCommand.getBank())) ? + config.Timings.tCCD_L : config.Timings.tCCD_S; + bool casToCas = (getDistance(read.getStart(), strobeCommand.getStart()) < tCCD) ? true : false; + + return collision || casToCas; } else if (strobeCommand.getCommand() == Command::Write || strobeCommand.getCommand() == Command::WriteA) diff --git a/dram/src/core/scheduling/checker/WriteChecker.cpp b/dram/src/core/scheduling/checker/WriteChecker.cpp index 9b52d2c9..f53a04dd 100644 --- a/dram/src/core/scheduling/checker/WriteChecker.cpp +++ b/dram/src/core/scheduling/checker/WriteChecker.cpp @@ -71,10 +71,18 @@ bool WriteChecker::collidesOnDataStrobe(ScheduledCommand& write) const bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand& write, ScheduledCommand& strobeCommand) const { + //write to write if (strobeCommand.getCommand() == Command::Write || strobeCommand.getCommand() == Command::WriteA) { - return getIntervalOnDataStrobe(write).intersects(getIntervalOnDataStrobe(strobeCommand)); + bool collision = getIntervalOnDataStrobe(write).intersects(getIntervalOnDataStrobe(strobeCommand)); + + sc_time tCCD = + (getBankGroup(write.getBank()) == getBankGroup(strobeCommand.getBank())) ? + config.Timings.tCCD_L : config.Timings.tCCD_S; + bool casToCas = (getDistance(write.getStart(), strobeCommand.getStart()) < tCCD) ? true : false; + + return collision || casToCas; } else if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA) diff --git a/dram/src/core/utils/Utils.cpp b/dram/src/core/utils/Utils.cpp index 2b19f0e1..3789b8a3 100644 --- a/dram/src/core/utils/Utils.cpp +++ b/dram/src/core/utils/Utils.cpp @@ -11,14 +11,20 @@ #include "../../common/DebugManager.h" #include "../configuration/Configuration.h" -namespace core -{ +namespace core { unsigned int getStartAddress(const Bank& bank) { return 0; } +sc_time getDistance(sc_time a, sc_time b) +{ + if (a > b) + return a - b; + else + return b - a; +} sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint) { @@ -38,18 +44,26 @@ const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment) TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command) { - sc_assert(command.getCommand() == Command::Read || command.getCommand() == Command::ReadA || - command.getCommand() == Command::Write ||command.getCommand() == Command::WriteA); + sc_assert( + command.getCommand() == Command::Read || command.getCommand() == Command::ReadA + || command.getCommand() == Command::Write + || command.getCommand() == Command::WriteA); TimingConfiguration& timings = Configuration::getInstance().Timings; - if(command.getCommand() == Command::Read || command.getCommand() == Command::ReadA) + sc_assert((command.getBurstLength() / Configuration::getInstance().DataRate) > 0); + sc_time burstLength = timings.clk + * (command.getBurstLength() / Configuration::getInstance().DataRate); + + if (command.getCommand() == Command::Read || command.getCommand() == Command::ReadA) { - return TimeInterval(command.getStart() + timings.tRL, command.getStart() + timings.tRL + timings.clk * command.getBurstLength()); + return TimeInterval(command.getStart() + timings.tRL, + command.getStart() + timings.tRL + burstLength); } else { - return TimeInterval(command.getStart() + timings.tWL, command.getStart() + timings.tWL + timings.clk * command.getBurstLength()); + return TimeInterval(command.getStart() + timings.tWL, + command.getStart() + timings.tWL + burstLength); } } @@ -58,7 +72,6 @@ bool isClkAligned(sc_time time, sc_time clk) return !((time / clk) - ceil(time / clk)); } - bool TimeInterval::timeIsInInterval(sc_time time) { return (start < time && time < end); diff --git a/dram/src/core/utils/Utils.h b/dram/src/core/utils/Utils.h index 2b2fef07..3ace036a 100644 --- a/dram/src/core/utils/Utils.h +++ b/dram/src/core/utils/Utils.h @@ -26,6 +26,8 @@ struct TimeInterval bool intersects(TimeInterval other); }; +sc_time getDistance(sc_time a, sc_time b); + struct TimingConfiguration; sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint); TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command); diff --git a/dram/src/simulation/main.cpp b/dram/src/simulation/main.cpp index e7036cdd..7bb7f030 100644 --- a/dram/src/simulation/main.cpp +++ b/dram/src/simulation/main.cpp @@ -29,20 +29,21 @@ int sc_main(int argc, char **argv) { sc_set_time_resolution(1, SC_PS); - - string resources = pathOfFile(argv[0]) + string("/../resources/"); string memconfig = "memconfig.xml"; string memspec = "MatzesWideIO.xml"; string stl1 = "chstone-sha_32.stl"; - unsigned int burstlength1 = 4; + stl1 = "empty.stl"; + unsigned int burstlength1 = 8; string stl2 = "mediabench-h263decode_32.stl"; - unsigned int burstlength2 = 4; + stl2 = "trace.stl"; + unsigned int burstlength2 = 8; string traceName = "unaware_long.tdb"; - Configuration::memspecUri = "/home/robert/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml"; - Configuration::memconfigUri = "/home/robert/git/dram/dram/resources/configs/memconfigs/memconfig.xml"; + Configuration::memspecUri = "/home/jonny/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml"; + Configuration::memspecUri = "/home/jonny/git/dram/dram/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml"; + Configuration::memconfigUri = "/home/jonny/git/dram/dram/resources/configs/memconfigs/memconfig.xml"; // Configuration::memconfigUri = resources + string("configs/memconfigs/") + memconfig; // Configuration::memconfigUri = resources + string("configs/memspecs/") + memspec;