From 9935abe28a3de0f699dd5341d46348783d1fdc22 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 28 Oct 2021 15:44:50 +0200 Subject: [PATCH 01/23] Introduce a common json configuration library This new configuration library is capable of parsing DRAMSys config jsons and generating them. The "Configuration" struct contains the complete configuration required for simulation. The library will be used in future in DRAMSys itself and also in the TracePlayer, gem5 player, TraceAnalyzer and all other tools that use DRAMSys as a library. --- DRAMSys/library/CMakeLists.txt | 5 +- .../common/configuration/AddressMapping.cpp | 87 +++++++++ .../src/common/configuration/AddressMapping.h | 71 +++++++ .../src/common/configuration/CMakeLists.txt | 57 ++++++ .../common/configuration/Configuration.cpp | 68 +++++++ .../src/common/configuration/Configuration.h | 80 ++++++++ .../src/common/configuration/McConfig.cpp | 78 ++++++++ .../src/common/configuration/McConfig.h | 171 +++++++++++++++++ .../src/common/configuration/SimConfig.cpp | 79 ++++++++ .../src/common/configuration/SimConfig.h | 92 +++++++++ .../common/configuration/ThermalConfig.cpp | 98 ++++++++++ .../src/common/configuration/ThermalConfig.h | 117 +++++++++++ .../src/common/configuration/TraceSetup.cpp | 131 +++++++++++++ .../src/common/configuration/TraceSetup.h | 112 +++++++++++ .../memspec/MemArchitectureSpec.cpp | 59 ++++++ .../memspec/MemArchitectureSpec.h | 56 ++++++ .../configuration/memspec/MemPowerSpec.cpp | 59 ++++++ .../configuration/memspec/MemPowerSpec.h | 56 ++++++ .../common/configuration/memspec/MemSpec.cpp | 62 ++++++ .../common/configuration/memspec/MemSpec.h | 63 ++++++ .../configuration/memspec/MemTimingSpec.cpp | 59 ++++++ .../configuration/memspec/MemTimingSpec.h | 56 ++++++ .../common/configuration/tests/CMakeLists.txt | 2 + .../common/configuration/tests/simpletest.cpp | 181 ++++++++++++++++++ .../library/src/common/configuration/util.h | 75 ++++++++ 25 files changed, 1971 insertions(+), 3 deletions(-) create mode 100644 DRAMSys/library/src/common/configuration/AddressMapping.cpp create mode 100644 DRAMSys/library/src/common/configuration/AddressMapping.h create mode 100644 DRAMSys/library/src/common/configuration/CMakeLists.txt create mode 100644 DRAMSys/library/src/common/configuration/Configuration.cpp create mode 100644 DRAMSys/library/src/common/configuration/Configuration.h create mode 100644 DRAMSys/library/src/common/configuration/McConfig.cpp create mode 100644 DRAMSys/library/src/common/configuration/McConfig.h create mode 100644 DRAMSys/library/src/common/configuration/SimConfig.cpp create mode 100644 DRAMSys/library/src/common/configuration/SimConfig.h create mode 100644 DRAMSys/library/src/common/configuration/ThermalConfig.cpp create mode 100644 DRAMSys/library/src/common/configuration/ThermalConfig.h create mode 100644 DRAMSys/library/src/common/configuration/TraceSetup.cpp create mode 100644 DRAMSys/library/src/common/configuration/TraceSetup.h create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemSpec.h create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp create mode 100644 DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h create mode 100644 DRAMSys/library/src/common/configuration/tests/CMakeLists.txt create mode 100644 DRAMSys/library/src/common/configuration/tests/simpletest.cpp create mode 100644 DRAMSys/library/src/common/configuration/util.h diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 8549b70d..61b4756b 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -44,9 +44,8 @@ set(DCMAKE_SH="CMAKE_SH-NOTFOUND") # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) -# Add nlohmann: -set(JSON_BuildTests OFF CACHE INTERNAL "") -add_subdirectory(src/common/third_party/nlohmann) +# Add Configuration +add_subdirectory(src/common/configuration) # Add SystemC: if(DEFINED ENV{SYSTEMC_HOME}) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp new file mode 100644 index 00000000..cceea826 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "AddressMapping.h" +#include "util.h" + +#include + +namespace Configuration +{ + +void to_json(json &j, const AddressMapping &m) +{ + json congen = json{}; + + congen = json{{"BYTE_BIT", m.byteBits}, + {"COLUMN_BIT", m.coloumnBits}, + {"BANKGROUP_BIT", m.bankGroupBits}, + {"BANK_BIT", m.bankBits}, + {"ROW_BIT", m.rowBits}}; + + Util::from_optional("CHANNEL_BIT", congen, m.channelBits); + Util::from_optional("BYTE_BIT", congen, m.byteBits); + Util::from_optional("BANKGROUP_BIT", congen, m.bankGroupBits); + Util::from_optional("XOR", congen, m.xorBits); + + j["CONGEN"] = congen; +} + +void from_json(const json &j, AddressMapping &m) +{ + json congen = j.at("CONGEN"); + + congen.at("COLUMN_BIT").get_to(m.coloumnBits); + congen.at("BANK_BIT").get_to(m.bankBits); + congen.at("ROW_BIT").get_to(m.rowBits); + + Util::get_optional("CHANNEL_BIT", congen, m.channelBits); + Util::get_optional("BYTE_BIT", congen, m.byteBits); + Util::get_optional("BANKGROUP_BIT", congen, m.bankGroupBits); + Util::get_optional("XOR", congen, m.xorBits); +} + +void to_json(json &j, const XorPair &x) +{ + j = json{{"FIRST", x.first}, {"SECOND", x.second}}; +} + +void from_json(const json &j, XorPair &x) +{ + j.at("FIRST").get_to(x.first); + j.at("SECOND").get_to(x.second); +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h new file mode 100644 index 00000000..dd3f9c91 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef ADDRESSMAPPING_H +#define ADDRESSMAPPING_H + +#include +#include + +namespace Configuration +{ +using json = nlohmann::json; + +struct XorPair +{ + unsigned int first; + unsigned int second; +}; + +void to_json(json &j, const XorPair &x); +void from_json(const json &j, XorPair &x); + +struct AddressMapping +{ + std::pair, bool> byteBits; + std::unordered_set coloumnBits; + std::unordered_set bankBits; + std::pair, bool> bankGroupBits; + std::unordered_set rowBits; + std::pair, bool> channelBits; + std::pair, bool> xorBits; +}; + +void to_json(json &j, const AddressMapping &m); +void from_json(const json &j, AddressMapping &m); + +} // namespace Configuration + +#endif // ADDRESSMAPPING_H diff --git a/DRAMSys/library/src/common/configuration/CMakeLists.txt b/DRAMSys/library/src/common/configuration/CMakeLists.txt new file mode 100644 index 00000000..87c02b92 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/CMakeLists.txt @@ -0,0 +1,57 @@ +# Copyright (c) 2021, Technische Universität Kaiserslautern +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: +# Derek Christ + +set(JSON_BuildTests OFF CACHE INTERNAL "") +add_subdirectory(${CMAKE_SOURCE_DIR}/library/src/common/third_party/nlohmann ${CMAKE_CURRENT_BINARY_DIR}/nlohmann) + +option(DRAMSYS_CONFIGURATION_TESTS "Build the unit tests for configuration." OFF) + +if (DRAMSYS_CONFIGURATION_TESTS) + add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/tests) +endif() + +add_library(DRAMSysConfiguration STATIC + Configuration.cpp + AddressMapping.cpp + McConfig.cpp + SimConfig.cpp + ThermalConfig.cpp + TraceSetup.cpp + memspec/MemSpec.cpp + memspec/MemArchitectureSpec.cpp + memspec/MemPowerSpec.cpp + memspec/MemTimingSpec.cpp +) + +target_link_libraries(DRAMSysConfiguration PRIVATE nlohmann_json::nlohmann_json) +target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) diff --git a/DRAMSys/library/src/common/configuration/Configuration.cpp b/DRAMSys/library/src/common/configuration/Configuration.cpp new file mode 100644 index 00000000..24cd663f --- /dev/null +++ b/DRAMSys/library/src/common/configuration/Configuration.cpp @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "Configuration.h" +#include "util.h" + +#include + +namespace Configuration +{ + +void to_json(json &j, const Configuration &c) +{ + j = json{{"addressmapping", c.addressMapping}, + {"mcconfig", c.mcConfig}, + {"memspec", c.memSpec}, + {"simulationid", c.simulationId}, + {"simconfig", c.simConfig}}; + + Util::from_optional("thermalconfig", j, c.thermalConfig); + Util::from_optional("tracesetup", j, c.traceSetup); +} + +void from_json(const json &j, Configuration &c) +{ + j.at("addressmapping").get_to(c.addressMapping); + j.at("mcconfig").get_to(c.mcConfig); + j.at("memspec").get_to(c.memSpec); + j.at("simulationid").get_to(c.simulationId); + j.at("simconfig").get_to(c.simConfig); + + Util::get_optional("thermalconfig", j, c.thermalConfig); + Util::get_optional("tracesetup", j, c.traceSetup); +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h new file mode 100644 index 00000000..069a5147 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef CONFIGURATION_H +#define CONFIGURATION_H + +#include "AddressMapping.h" +#include "McConfig.h" +#include "SimConfig.h" +#include "ThermalConfig.h" +#include "TraceSetup.h" +#include "memspec/MemSpec.h" + +#include +#include +#include + +/** + * To support polymorphic configurations, a Json "type" tag is used + * to determine the correct type before further parsing. + * + * To support optional values, std::pair is used. The first parameter is the value, + * the second parameter specifies if the value is valid. + * Replace with std::optional when this project is updated to C++17. + * Consider also switching to std::variant to achieve static polymorphism. + */ + +namespace Configuration +{ +using json = nlohmann::json; + +struct Configuration +{ + AddressMapping addressMapping; + McConfig mcConfig; + MemSpec memSpec; + SimConfig simConfig; + std::string simulationId; + std::pair thermalConfig; + std::pair traceSetup; +}; + +void to_json(json &j, const Configuration &p); +void from_json(const json &j, Configuration &p); + +} // namespace Configuration + +#endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp new file mode 100644 index 00000000..b0ad41ec --- /dev/null +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "McConfig.h" +#include "util.h" + +namespace Configuration +{ + +void to_json(json &j, const McConfig &c) +{ + j = json{{"PagePolicy", c.pagePolicy}, + {"Scheduler", c.scheduler}, + {"SchedulerBuffer", c.schedulerBuffer}, + {"RequestBufferSize", c.requestBufferSize}, + {"CmdMux", c.cmdMux}, + {"RespQueue", c.respQueue}, + {"RefreshPolicy", c.refreshPolicy}, + {"RefreshMaxPostponed", c.refreshMaxPostponed}, + {"RefreshMaxPulledin", c.refreshMaxPulledin}, + {"PowerDownPolicy", c.powerDownPolicy}, + {"Arbiter", c.arbiter}, + {"MaxActiveTransactions", c.maxActiveTransactions}}; + + Util::from_optional("RefreshManagment", j, c.refreshManagement); +} + +void from_json(const json &j, McConfig &c) +{ + j.at("PagePolicy").get_to(c.pagePolicy); + j.at("Scheduler").get_to(c.scheduler); + j.at("SchedulerBuffer").get_to(c.schedulerBuffer); + j.at("RequestBufferSize").get_to(c.requestBufferSize); + j.at("CmdMux").get_to(c.cmdMux); + j.at("RespQueue").get_to(c.respQueue); + j.at("RefreshPolicy").get_to(c.refreshPolicy); + j.at("RefreshMaxPostponed").get_to(c.refreshMaxPostponed); + j.at("RefreshMaxPulledin").get_to(c.refreshMaxPulledin); + j.at("PowerDownPolicy").get_to(c.powerDownPolicy); + j.at("Arbiter").get_to(c.arbiter); + j.at("MaxActiveTransactions").get_to(c.maxActiveTransactions); + + Util::get_optional("RefreshManagment", j, c.refreshManagement); +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h new file mode 100644 index 00000000..d265e022 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef MCCONFIG_H +#define MCCONFIG_H + +#include +#include +#include + +namespace Configuration +{ +using json = nlohmann::json; + +enum class PagePolicy +{ + Open, + OpenAdaptive, + Closed, + ClosedAdaptive, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(PagePolicy, { + {PagePolicy::Invalid, nullptr}, + {PagePolicy::Open, "Open"}, + {PagePolicy::OpenAdaptive, "OpenAdaptive"}, + {PagePolicy::Closed, "Closed"}, + {PagePolicy::ClosedAdaptive, "ClosedAdaptive"}, + }) + +enum class Scheduler +{ + Fifo, + FrFcfs, + FrFcfsGrp, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(Scheduler, {{Scheduler::Invalid, nullptr}, + {Scheduler::Fifo, "Fifo"}, + {Scheduler::FrFcfs, "FrFcfs"}, + {Scheduler::FrFcfsGrp, "FrFcfsGrp"}}) + +enum class SchedulerBuffer +{ + Bankwise, + ReadWrite, + Shared, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(SchedulerBuffer, {{SchedulerBuffer::Invalid, nullptr}, + {SchedulerBuffer::Bankwise, "Bankwise"}, + {SchedulerBuffer::ReadWrite, "ReadWrite"}, + {SchedulerBuffer::Shared, "Shared"}}) + +enum class CmdMux +{ + Oldest, + Strict, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(CmdMux, + {{CmdMux::Invalid, nullptr}, {CmdMux::Oldest, "Oldest"}, {CmdMux::Strict, "Strict"}}) + +enum class RespQueue +{ + Fifo, + Reorder, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(RespQueue, {{RespQueue::Invalid, nullptr}, + {RespQueue::Fifo, "Fifo"}, + {RespQueue::Reorder, "Reorder"}}) + +enum class RefreshPolicy +{ + NoRefresh, + AllBank, + PerBank, + SameBank, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicy, {{RefreshPolicy::Invalid, nullptr}, + {RefreshPolicy::AllBank, "AllBank"}, + {RefreshPolicy::PerBank, "PerBank"}, + {RefreshPolicy::SameBank, "SameBank"}}) + +enum class PowerDownPolicy +{ + NoPowerDown, + Staggered, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(PowerDownPolicy, {{PowerDownPolicy::Invalid, nullptr}, + {PowerDownPolicy::NoPowerDown, "NoPowerDown"}, + {PowerDownPolicy::Staggered, "Staggered"}}) + +enum class Arbiter +{ + Simple, + Fifo, + Reorder, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(Arbiter, {{Arbiter::Invalid, nullptr}, + {Arbiter::Simple, "Simple"}, + {Arbiter::Fifo, "Fifo"}, + {Arbiter::Reorder, "Reorder"}}) + +struct McConfig +{ + PagePolicy pagePolicy; + Scheduler scheduler; + SchedulerBuffer schedulerBuffer; + unsigned int requestBufferSize; + CmdMux cmdMux; + RespQueue respQueue; + RefreshPolicy refreshPolicy; + unsigned int refreshMaxPostponed; + unsigned int refreshMaxPulledin; + PowerDownPolicy powerDownPolicy; + Arbiter arbiter; + unsigned int maxActiveTransactions; + std::pair refreshManagement; +}; + +void to_json(json &j, const McConfig &c); +void from_json(const json &j, McConfig &c); + +} // namespace Configuration + +#endif // MCCONFIG_H diff --git a/DRAMSys/library/src/common/configuration/SimConfig.cpp b/DRAMSys/library/src/common/configuration/SimConfig.cpp new file mode 100644 index 00000000..91acde69 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/SimConfig.cpp @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "SimConfig.h" + +namespace Configuration +{ + +void to_json(json &j, const SimConfig &c) +{ + j = json{{"AddressOffset", c.addressOffset}, + {"CheckTLM2Protocol", c.checkTLM2Protocol}, + {"DatabaseRecording", c.databaseRecording}, + {"Debug", c.debug}, + {"ECCControllerMode", c.eccControllerMode}, + {"EnableWindowing", c.enableWindowing}, + {"ErrorCSVFile", c.errorCsvFile}, + {"ErrorChipSeed", c.errorChipSeed}, + {"PowerAnalysis", c.powerAnalysis}, + {"SimulationName", c.simulationName}, + {"SimulationProgressBar", c.simulationProgressBar}, + {"StoreMode", c.storeMode}, + {"ThermalSimulation", c.thermalSimulation}, + {"UseMalloc", c.useMalloc}, + {"WindowSize", c.windowSize}}; +} + +void from_json(const json &j, SimConfig &c) +{ + j.at("AddressOffset").get_to(c.addressOffset); + j.at("CheckTLM2Protocol").get_to(c.checkTLM2Protocol); + j.at("DatabaseRecording").get_to(c.databaseRecording); + j.at("Debug").get_to(c.debug); + j.at("ECCControllerMode").get_to(c.eccControllerMode); + j.at("EnableWindowing").get_to(c.enableWindowing); + j.at("ErrorCSVFile").get_to(c.errorCsvFile); + j.at("ErrorChipSeed").get_to(c.errorChipSeed); + j.at("PowerAnalysis").get_to(c.powerAnalysis); + j.at("SimulationName").get_to(c.simulationName); + j.at("SimulationProgressBar").get_to(c.simulationProgressBar); + j.at("StoreMode").get_to(c.storeMode); + j.at("ThermalSimulation").get_to(c.thermalSimulation); + j.at("UseMalloc").get_to(c.useMalloc); + j.at("WindowSize").get_to(c.windowSize); +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/SimConfig.h b/DRAMSys/library/src/common/configuration/SimConfig.h new file mode 100644 index 00000000..7d23ff75 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/SimConfig.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef SIMCONFIG_H +#define SIMCONFIG_H + +#include + +namespace Configuration +{ +using json = nlohmann::json; + +enum class ECCControllerMode +{ + Disabled, + Hamming, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(ECCControllerMode, {{ECCControllerMode::Invalid, nullptr}, + {ECCControllerMode::Disabled, "Disabled"}, + {ECCControllerMode::Hamming, "Hamming"}}) + +enum class StoreMode +{ + NoStorage, + Store, + ErrorModel, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(StoreMode, {{StoreMode::Invalid, nullptr}, + {StoreMode::Store, "Store"}, + {StoreMode::ErrorModel, "ErrorModel"}}) + +struct SimConfig +{ + unsigned int addressOffset; + bool checkTLM2Protocol; + bool databaseRecording; + bool debug; + ECCControllerMode eccControllerMode; + bool enableWindowing; + std::string errorCsvFile; + unsigned int errorChipSeed; + bool powerAnalysis; + std::string simulationName; + bool simulationProgressBar; + StoreMode storeMode; + bool thermalSimulation; + bool useMalloc; + unsigned int windowSize; +}; + +void to_json(json &j, const SimConfig &c); +void from_json(const json &j, SimConfig &c); + +} // namespace Configuration + +#endif diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp new file mode 100644 index 00000000..e593fcbe --- /dev/null +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "ThermalConfig.h" + +namespace Configuration +{ + +void to_json(json &j, const ThermalConfig &c) +{ + j = json{{"TemperatureScale", c.temperatureScale}, + {"StaticTemperatureDefaultValue", c.staticTemperatureDefaultValue}, + {"ThermalSimPeriod", c.thermalSimPeriod}, + {"ThermalSimUnit", c.thermalSimUnit}, + {"PowerInfoFile", c.powerInfo}, + {"IceServerIp", c.iceServerIp}, + {"IceServerPort", c.iceServerPort}, + {"SimPeriodAdjustFactor", c.simPeriodAdjustFactor}, + {"NPowStableCyclesToIncreasePeriod", c.nPowStableCyclesToIncreasePeriod}, + {"GenerateTemperatureMap", c.generateTemperatureMap}, + {"GeneratePowerMap", c.generatePowerMap}}; +} + +void from_json(const json &j, ThermalConfig &c) +{ + j.at("TemperatureScale").get_to(c.temperatureScale); + j.at("StaticTemperatureDefaultValue").get_to(c.staticTemperatureDefaultValue); + j.at("ThermalSimPeriod").get_to(c.thermalSimPeriod); + j.at("ThermalSimUnit").get_to(c.thermalSimUnit); + j.at("PowerInfoFile").get_to(c.powerInfo); + j.at("IceServerIp").get_to(c.iceServerIp); + j.at("IceServerPort").get_to(c.iceServerPort); + j.at("SimPeriodAdjustFactor").get_to(c.simPeriodAdjustFactor); + j.at("NPowStableCyclesToIncreasePeriod").get_to(c.nPowStableCyclesToIncreasePeriod); + j.at("GenerateTemperatureMap").get_to(c.generateTemperatureMap); + j.at("GeneratePowerMap").get_to(c.generatePowerMap); +} + +void to_json(json &j, const DramDieChannel &c) +{ + j = json{{"init_pow", c.init_pow}, {"threshold", c.threshold}}; +} + +void from_json(const json &j, DramDieChannel &c) +{ + j.at("init_pow").get_to(c.init_pow); + j.at("threshold").get_to(c.threshold); +} + +void to_json(json &j, const PowerInfo &c) +{ + j = json{{"dram_die_channel0", c.channel0}, + {"dram_die_channel1", c.channel1}, + {"dram_die_channel2", c.channel2}, + {"dram_die_channel3", c.channel3}}; +} + +void from_json(const json &j, PowerInfo &c) +{ + j.at("dram_die_channel0").get_to(c.channel0); + j.at("dram_die_channel1").get_to(c.channel1); + j.at("dram_die_channel2").get_to(c.channel2); + j.at("dram_die_channel3").get_to(c.channel3); +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.h b/DRAMSys/library/src/common/configuration/ThermalConfig.h new file mode 100644 index 00000000..a6e6fd34 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef THERMALCONFIG_H +#define THERMALCONFIG_H + +#include + +namespace Configuration +{ +using json = nlohmann::json; + +enum class TemperatureScale +{ + Celsius, + Fahrenheit, + Kelvin, + Invalid = -1, +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(TemperatureScale, {{TemperatureScale::Invalid, nullptr}, + {TemperatureScale::Celsius, "Celsius"}, + {TemperatureScale::Fahrenheit, "Fahrenheit"}, + {TemperatureScale::Kelvin, "Kelvin"}}) + +enum class ThermalSimUnit +{ + Seconds, + Milliseconds, + Microseconds, + Nanoseconds, + Picoseconds, + Femtoseconds, + Invalid = -1, +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(ThermalSimUnit, {{ThermalSimUnit::Invalid, nullptr}, + {ThermalSimUnit::Seconds, "s"}, + {ThermalSimUnit::Milliseconds, "ms"}, + {ThermalSimUnit::Microseconds, "us"}, + {ThermalSimUnit::Nanoseconds, "ns"}, + {ThermalSimUnit::Picoseconds, "ps"}, + {ThermalSimUnit::Femtoseconds, "fs"}}) + +struct DramDieChannel +{ + double init_pow; + double threshold; +}; + +void to_json(json &j, const DramDieChannel &c); +void from_json(const json &j, DramDieChannel &c); + +struct PowerInfo +{ + DramDieChannel channel0; + DramDieChannel channel1; + DramDieChannel channel2; + DramDieChannel channel3; +}; + +void to_json(json &j, const PowerInfo &c); +void from_json(const json &j, PowerInfo &c); + +struct ThermalConfig +{ + TemperatureScale temperatureScale; + int staticTemperatureDefaultValue; + double thermalSimPeriod; + ThermalSimUnit thermalSimUnit; + PowerInfo powerInfo; + std::string iceServerIp; + unsigned int iceServerPort; + unsigned int simPeriodAdjustFactor; + unsigned int nPowStableCyclesToIncreasePeriod; + bool generateTemperatureMap; + bool generatePowerMap; +}; + +void to_json(json &j, const ThermalConfig &c); +void from_json(const json &j, ThermalConfig &c); + +} // namespace Configuration + +#endif // THERMALCONFIG_H diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp new file mode 100644 index 00000000..e39452fc --- /dev/null +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "TraceSetup.h" +#include "util.h" + +namespace Configuration +{ + +TrafficInitiator::~TrafficInitiator() +{ +} + +void to_json(json &j, const TraceSetup &c) +{ + // Create an empty array + j = json::array(); + + for (const auto &initiator : c.initiators) + { + json inititator_j; + + inititator_j["name"] = initiator->name; + inititator_j["clkMhz"] = initiator->clkMhz; + + if (const auto generator = dynamic_cast(initiator.get())) + { + inititator_j["type"] = "generator"; + inititator_j["numRequests"] = generator->numRequests; + inititator_j["rwRatio"] = generator->rwRatio; + inititator_j["addressDistribution"] = generator->addressDistribution; + + Util::from_optional("seed", inititator_j, generator->seed); + Util::from_optional("maxPendingReadRequests", inititator_j, generator->maxPendingReadRequests); + Util::from_optional("maxPendingWriteRequests", inititator_j, generator->maxPendingWriteRequests); + Util::from_optional("minAddress", inititator_j, generator->minAddress); + Util::from_optional("maxAddress", inititator_j, generator->maxAddress); + } + else if (const auto hammer = dynamic_cast(initiator.get())) + { + inititator_j["type"] = "hammer"; + inititator_j["numRequests"] = hammer->numRequests; + inititator_j["rowIncrement"] = hammer->rowIncrement; + } + else if (const auto player = dynamic_cast(initiator.get())) + { + inititator_j["type"] = "player"; + } + + j.insert(j.end(), inititator_j); + } +} + +void from_json(const json &j, TraceSetup &c) +{ + for (const auto &initiator_j : j) + { + // Default to Player, when not specified + TrafficInitiatorType type = initiator_j.value("type", TrafficInitiatorType::Player); + + std::unique_ptr initiator; + if (type == TrafficInitiatorType::Player) + { + initiator = std::unique_ptr(new TracePlayer); + } + else if (type == TrafficInitiatorType::Generator) + { + TraceGenerator *generator = new TraceGenerator; + + initiator_j.at("numRequests").get_to(generator->numRequests); + initiator_j.at("rwRatio").get_to(generator->rwRatio); + initiator_j.at("addressDistribution").get_to(generator->addressDistribution); + + Util::get_optional("seed", initiator_j, generator->seed); + Util::get_optional("maxPendingReadRequests", initiator_j, generator->maxPendingReadRequests); + Util::get_optional("maxPendingWriteRequests", initiator_j, generator->maxPendingWriteRequests); + Util::get_optional("minAddress", initiator_j, generator->minAddress); + Util::get_optional("maxAddress", initiator_j, generator->maxAddress); + + initiator = std::unique_ptr(generator); + } + else if (type == TrafficInitiatorType::Hammer) + { + TraceHammer *hammer = new TraceHammer; + + initiator_j.at("numRequests").get_to(hammer->numRequests); + initiator_j.at("rowIncrement").get_to(hammer->rowIncrement); + + initiator = std::unique_ptr(hammer); + } + + initiator_j.at("name").get_to(initiator->name); + initiator_j.at("clkMhz").get_to(initiator->clkMhz); + + c.initiators.emplace(std::move(initiator)); + } +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h new file mode 100644 index 00000000..d3974ec6 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef TRACESETUP_H +#define TRACESETUP_H + +#include +#include +#include + +namespace Configuration +{ +using json = nlohmann::json; + +enum class TrafficInitiatorType +{ + Player, + Generator, + Hammer, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(TrafficInitiatorType, {{TrafficInitiatorType::Invalid, nullptr}, + {TrafficInitiatorType::Player, "player"}, + {TrafficInitiatorType::Hammer, "hammer"}, + {TrafficInitiatorType::Generator, "generator"}}) + +enum class AddressDistribution +{ + Random, + Sequential, + Invalid = -1 +}; + +NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid, nullptr}, + {AddressDistribution::Random, "random"}, + {AddressDistribution::Sequential, "sequential"}}) + +struct TrafficInitiator +{ + virtual ~TrafficInitiator() = 0; + + unsigned int clkMhz; + std::string name; +}; + +struct TracePlayer : public TrafficInitiator +{ +}; + +struct TraceGenerator : public TrafficInitiator +{ + unsigned int numRequests; + double rwRatio; + AddressDistribution addressDistribution; + std::pair addressIncrement; + std::pair seed; + std::pair maxPendingReadRequests; + std::pair maxPendingWriteRequests; + std::pair minAddress; + std::pair maxAddress; +}; + +struct TraceHammer : public TrafficInitiator +{ + unsigned int numRequests; + unsigned int rowIncrement; +}; + +struct TraceSetup +{ + std::unordered_set> initiators; +}; + +void to_json(json &j, const TraceSetup &c); +void from_json(const json &j, TraceSetup &c); + +} // namespace Configuration + +#endif diff --git a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp new file mode 100644 index 00000000..5de2684b --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "MemArchitectureSpec.h" + +namespace Configuration +{ + +void to_json(json &j, const MemArchitectureSpec &c) +{ + j = json{}; + + for (const auto &entry : c.entries) + { + j[entry.first] = entry.second; + } +} + +void from_json(const json &j, MemArchitectureSpec &c) +{ + for (const auto &entry : j.items()) + { + c.entries[entry.key()] = entry.value(); + } +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h new file mode 100644 index 00000000..cd516ad2 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef MEMARCHITECTURESPEC_H +#define MEMARCHITECTURESPEC_H + +#include +#include + +namespace Configuration +{ +using json = nlohmann::json; + +struct MemArchitectureSpec +{ + std::unordered_map entries; +}; + +void to_json(json &j, const MemArchitectureSpec &c); +void from_json(const json &j, MemArchitectureSpec &c); + +} // namespace Configuration + +#endif diff --git a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp new file mode 100644 index 00000000..6621fabc --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "MemPowerSpec.h" + +namespace Configuration +{ + +void to_json(json &j, const MemPowerSpec &c) +{ + j = json{}; + + for (const auto &entry : c.entries) + { + j[entry.first] = entry.second; + } +} + +void from_json(const json &j, MemPowerSpec &c) +{ + for (const auto &entry : j.items()) + { + c.entries[entry.key()] = entry.value(); + } +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h new file mode 100644 index 00000000..5c201580 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef MEMPOWERSPEC_H +#define MEMPOWERSPEC_H + +#include +#include + +namespace Configuration +{ +using json = nlohmann::json; + +struct MemPowerSpec +{ + std::unordered_map entries; +}; + +void to_json(json &j, const MemPowerSpec &c); +void from_json(const json &j, MemPowerSpec &c); + +} // namespace Configuration + +#endif diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp new file mode 100644 index 00000000..8bdcf0ef --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "MemSpec.h" +#include "util.h" + +namespace Configuration +{ + +void to_json(json &j, const MemSpec &c) +{ + j = json{{"memarchitecturespec", c.memArchitectureSpec}, + {"memoryId", c.memoryId}, + {"memoryType", c.memoryType}, + {"memtimingspec", c.memTimingSpec}}; + + Util::from_optional("mempowerspec", j, c.memPowerSpec); +} + +void from_json(const json &j, MemSpec &c) +{ + j.at("memarchitecturespec").get_to(c.memArchitectureSpec); + j.at("memoryId").get_to(c.memoryId); + j.at("memoryType").get_to(c.memoryType); + j.at("memtimingspec").get_to(c.memTimingSpec); + + Util::get_optional("mempowerspec", j, c.memPowerSpec); +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h new file mode 100644 index 00000000..5d716963 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef MEMSPEC_H +#define MEMSPEC_H + +#include "MemArchitectureSpec.h" +#include "MemPowerSpec.h" +#include "MemTimingSpec.h" + +#include + +namespace Configuration +{ +using json = nlohmann::json; + +struct MemSpec +{ + MemArchitectureSpec memArchitectureSpec; + std::string memoryId; + std::string memoryType; + MemTimingSpec memTimingSpec; + std::pair memPowerSpec; +}; + +void to_json(json &j, const MemSpec &c); +void from_json(const json &j, MemSpec &c); + +} // namespace Configuration + +#endif // MEMSPEC_H diff --git a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp new file mode 100644 index 00000000..0b41f8cf --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "MemTimingSpec.h" + +namespace Configuration +{ + +void to_json(json &j, const MemTimingSpec &c) +{ + j = json{}; + + for (const auto &entry : c.entries) + { + j[entry.first] = entry.second; + } +} + +void from_json(const json &j, MemTimingSpec &c) +{ + for (const auto &entry : j.items()) + { + c.entries[entry.key()] = entry.value(); + } +} + +} // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h new file mode 100644 index 00000000..6203803b --- /dev/null +++ b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef MEMTIMINGSPEC_H +#define MEMTIMINGSPEC_H + +#include +#include + +namespace Configuration +{ +using json = nlohmann::json; + +struct MemTimingSpec +{ + std::unordered_map entries; +}; + +void to_json(json &j, const MemTimingSpec &c); +void from_json(const json &j, MemTimingSpec &c); + +} // namespace Configuration + +#endif diff --git a/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt b/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt new file mode 100644 index 00000000..0b9890b0 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt @@ -0,0 +1,2 @@ +add_executable(simpletest simpletest.cpp) +target_link_libraries(simpletest PRIVATE DRAMSysConfiguration nlohmann_json::nlohmann_json) diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp new file mode 100644 index 00000000..4c7f2b1a --- /dev/null +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -0,0 +1,181 @@ +#include +#include +#include + +using json = nlohmann::json; + +Configuration::AddressMapping getAddressMapping() +{ + // Configuration::ConGen *mycongen = new Configuration::ConGen; + // mycongen->byteBits = {{0, 1}, true}; + // mycongen->bankBits = {16}; + // mycongen->bankGroupBits = {{13, 14, 15}, true}; + // mycongen->coloumnBits = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}; + // mycongen->channelBits = {{33}, true}; + // mycongen->rowBits = {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + // return std::unique_ptr(mycongen); + + return Configuration::AddressMapping{{{0, 1}, true}, + {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, + {16}, + {{13, 14, 15}, true}, + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}, + {{33}, true}, + {{}, false}}; +} + +Configuration::McConfig getMcConfig() +{ + return Configuration::McConfig{Configuration::PagePolicy::Open, + Configuration::Scheduler::FrFcfs, + Configuration::SchedulerBuffer::Bankwise, + 8, + Configuration::CmdMux::Oldest, + Configuration::RespQueue::Fifo, + Configuration::RefreshPolicy::AllBank, + 0, + 0, + Configuration::PowerDownPolicy::NoPowerDown, + Configuration::Arbiter::Simple, + 128, + std::pair{false, true}}; +} + +Configuration::SimConfig getSimConfig() +{ + return Configuration::SimConfig { + 0, + false, + true, + false, + Configuration::ECCControllerMode::Disabled, + false, + "error.csv", + 42, + false, + "ddr5", + true, + Configuration::StoreMode::NoStorage, + false, + false, + 1000 + }; +} + +Configuration::ThermalConfig getThermalConfig() +{ + return Configuration::ThermalConfig{Configuration::TemperatureScale::Celsius, + 89, + 100, + Configuration::ThermalSimUnit::Microseconds, + Configuration::PowerInfo{{0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}}, + "127.0.0.1", + 118800, + 10, + 5, + true, + true}; +} + +std::unique_ptr getTracePlayer() +{ + Configuration::TracePlayer *player = new Configuration::TracePlayer; + + player->clkMhz = 100; + player->name = "mytrace.stl"; + + return std::unique_ptr(player); +} + +std::unique_ptr getTraceGeneratorRandom() +{ + Configuration::TraceGenerator *gen = new Configuration::TraceGenerator; + + gen->clkMhz = 100; + gen->name = "MyTestGen"; + + gen->addressDistribution = Configuration::AddressDistribution::Random; + gen->maxAddress = {1000, true}; + gen->maxPendingReadRequests = {8, true}; + gen->rwRatio = 0.5; + gen->seed = {1337, true}; + gen->numRequests = 1000; + + return std::unique_ptr(gen); +} + +std::unique_ptr getTraceGeneratorSequential() +{ + Configuration::TraceGenerator *gen = new Configuration::TraceGenerator; + + gen->clkMhz = 100; + gen->name = "MyTestGen"; + + gen->addressDistribution = Configuration::AddressDistribution::Sequential; + gen->addressIncrement = {64, true}; + gen->maxAddress = {1000, true}; + gen->maxPendingReadRequests = {8, true}; + gen->rwRatio = 0.5; + gen->numRequests = 1000; + + return std::unique_ptr(gen); +} + +std::unique_ptr getTraceHammer() +{ + Configuration::TraceHammer *hammer = new Configuration::TraceHammer; + + hammer->clkMhz = 100; + hammer->name = "MyTestHammer"; + + hammer->numRequests = 4000; + hammer->rowIncrement = 2097152; + + return std::unique_ptr(hammer); +} + +Configuration::TraceSetup getTraceSetup() +{ + std::unordered_set> initiators; + initiators.emplace(getTracePlayer()); + initiators.emplace(getTraceGeneratorRandom()); + initiators.emplace(getTraceGeneratorSequential()); + initiators.emplace(getTraceHammer()); + + return Configuration::TraceSetup{std::move(initiators)}; +} + +Configuration::Configuration getConfig(const Configuration::MemSpec &memSpec) +{ + return Configuration::Configuration{ + getAddressMapping(), + getMcConfig(), + memSpec, + getSimConfig(), + "std::string_simulationId", + {getThermalConfig(), true}, + // {{}, false}, works too + {getTraceSetup(), true}, + }; +} + +int main() +{ + std::ifstream file("ddr5.json"); + json ddr5_j = json::parse(file, nullptr, false); + json config = ddr5_j.at("simulation"); + Configuration::Configuration conf = config.get(); + std::ofstream fileout("myjson.json"); + json j_my; + j_my["simulation"] = getConfig(conf.memSpec); // just copy memspec over + fileout << j_my.dump(4); + + std::ifstream file2("hbm2.json"); + json hbm2_j = json::parse(file2, nullptr, false); + json hbm2_config = hbm2_j.at("simulation"); + Configuration::Configuration hbm2conf = hbm2_config.get(); + std::ofstream filehbm2("myhbm2.json"); + json j_myhbm2; + j_myhbm2["simulation"] = hbm2conf; + filehbm2 << j_myhbm2.dump(4); +} diff --git a/DRAMSys/library/src/common/configuration/util.h b/DRAMSys/library/src/common/configuration/util.h new file mode 100644 index 00000000..1f25489c --- /dev/null +++ b/DRAMSys/library/src/common/configuration/util.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef UTIL_H +#define UTIL_H + +#include +#include + +namespace Util +{ +using json = nlohmann::json; + +/** + * Inspired from https://github.com/nlohmann/json/issues/1749#issuecomment-770748811 + */ +template +void get_optional(const std::string &name, const json &j, std::pair &val) +{ + auto it = j.find(name); + if (it != j.end()) + { + val.first = it->template get(); + val.second = true; + } + else + { + val.second = false; + } +} + +template +void from_optional(const std::string &name, json &j, const std::pair &val) +{ + if (val.second) + { + j[name] = val.first; + } +} + +} // namespace Util + +#endif From 70c58ccc63ebaf5438515de1f0c53afb882baa16 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 29 Oct 2021 10:45:47 +0200 Subject: [PATCH 02/23] Make configuration library backwards compatible It's now possible to either directly insert the configuration objects into the main config json (new format) or just to enter the json file names to the configurations (old format). --- DRAMSys/library/CMakeLists.txt | 1 + .../common/configuration/AddressMapping.cpp | 26 +-- .../src/common/configuration/AddressMapping.h | 4 +- .../src/common/configuration/CMakeLists.txt | 3 + .../common/configuration/Configuration.cpp | 19 ++- .../src/common/configuration/Configuration.h | 4 +- .../src/common/configuration/McConfig.cpp | 32 ++-- .../src/common/configuration/McConfig.h | 4 +- .../src/common/configuration/SimConfig.cpp | 35 ++-- .../src/common/configuration/SimConfig.h | 4 +- .../common/configuration/ThermalConfig.cpp | 37 ++-- .../src/common/configuration/ThermalConfig.h | 4 +- .../src/common/configuration/TraceSetup.cpp | 22 +-- .../src/common/configuration/TraceSetup.h | 2 +- .../memspec/MemArchitectureSpec.cpp | 2 +- .../memspec/MemArchitectureSpec.h | 2 +- .../configuration/memspec/MemPowerSpec.cpp | 2 +- .../configuration/memspec/MemPowerSpec.h | 2 +- .../common/configuration/memspec/MemSpec.cpp | 16 +- .../common/configuration/memspec/MemSpec.h | 4 +- .../configuration/memspec/MemTimingSpec.cpp | 2 +- .../configuration/memspec/MemTimingSpec.h | 2 +- .../common/configuration/tests/simpletest.cpp | 159 ++++++++---------- .../library/src/common/configuration/util.cpp | 60 +++++++ .../library/src/common/configuration/util.h | 6 +- 25 files changed, 271 insertions(+), 183 deletions(-) create mode 100644 DRAMSys/library/src/common/configuration/util.cpp diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 61b4756b..391b6179 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -322,4 +322,5 @@ endif() target_link_libraries(DRAMSysLibrary PUBLIC ${SYSTEMC_LIBRARY} PRIVATE DRAMPower + PRIVATE DRAMSysConfiguration ) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp index cceea826..b3277d89 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.cpp +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -38,7 +38,7 @@ #include -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const AddressMapping &m) @@ -51,26 +51,32 @@ void to_json(json &j, const AddressMapping &m) {"BANK_BIT", m.bankBits}, {"ROW_BIT", m.rowBits}}; - Util::from_optional("CHANNEL_BIT", congen, m.channelBits); - Util::from_optional("BYTE_BIT", congen, m.byteBits); - Util::from_optional("BANKGROUP_BIT", congen, m.bankGroupBits); - Util::from_optional("XOR", congen, m.xorBits); + from_optional("CHANNEL_BIT", congen, m.channelBits); + from_optional("BYTE_BIT", congen, m.byteBits); + from_optional("BANKGROUP_BIT", congen, m.bankGroupBits); + from_optional("XOR", congen, m.xorBits); j["CONGEN"] = congen; } void from_json(const json &j, AddressMapping &m) { - json congen = j.at("CONGEN"); + json j_addressmapping = get_config_json(j, addressMappingPath, "CONGEN"); + + json congen; + if (j_addressmapping["CONGEN"].is_null()) + congen = j_addressmapping; + else + congen = j_addressmapping["CONGEN"]; congen.at("COLUMN_BIT").get_to(m.coloumnBits); congen.at("BANK_BIT").get_to(m.bankBits); congen.at("ROW_BIT").get_to(m.rowBits); - Util::get_optional("CHANNEL_BIT", congen, m.channelBits); - Util::get_optional("BYTE_BIT", congen, m.byteBits); - Util::get_optional("BANKGROUP_BIT", congen, m.bankGroupBits); - Util::get_optional("XOR", congen, m.xorBits); + get_optional("CHANNEL_BIT", congen, m.channelBits); + get_optional("BYTE_BIT", congen, m.byteBits); + get_optional("BANKGROUP_BIT", congen, m.bankGroupBits); + get_optional("XOR", congen, m.xorBits); } void to_json(json &j, const XorPair &x) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index dd3f9c91..07c4cda0 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -39,10 +39,12 @@ #include #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; +const std::string addressMappingPath = "configs/amconfigs"; + struct XorPair { unsigned int first; diff --git a/DRAMSys/library/src/common/configuration/CMakeLists.txt b/DRAMSys/library/src/common/configuration/CMakeLists.txt index 87c02b92..d62c5fdc 100644 --- a/DRAMSys/library/src/common/configuration/CMakeLists.txt +++ b/DRAMSys/library/src/common/configuration/CMakeLists.txt @@ -51,7 +51,10 @@ add_library(DRAMSysConfiguration STATIC memspec/MemArchitectureSpec.cpp memspec/MemPowerSpec.cpp memspec/MemTimingSpec.cpp + util.cpp ) +target_compile_definitions(DRAMSysConfiguration PRIVATE DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources") + target_link_libraries(DRAMSysConfiguration PRIVATE nlohmann_json::nlohmann_json) target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) diff --git a/DRAMSys/library/src/common/configuration/Configuration.cpp b/DRAMSys/library/src/common/configuration/Configuration.cpp index 24cd663f..006db6f2 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.cpp +++ b/DRAMSys/library/src/common/configuration/Configuration.cpp @@ -36,9 +36,9 @@ #include "Configuration.h" #include "util.h" -#include +#include -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const Configuration &c) @@ -49,8 +49,8 @@ void to_json(json &j, const Configuration &c) {"simulationid", c.simulationId}, {"simconfig", c.simConfig}}; - Util::from_optional("thermalconfig", j, c.thermalConfig); - Util::from_optional("tracesetup", j, c.traceSetup); + from_optional("thermalconfig", j, c.thermalConfig); + from_optional("tracesetup", j, c.traceSetup); } void from_json(const json &j, Configuration &c) @@ -61,8 +61,15 @@ void from_json(const json &j, Configuration &c) j.at("simulationid").get_to(c.simulationId); j.at("simconfig").get_to(c.simConfig); - Util::get_optional("thermalconfig", j, c.thermalConfig); - Util::get_optional("tracesetup", j, c.traceSetup); + get_optional("thermalconfig", j, c.thermalConfig); + get_optional("tracesetup", j, c.traceSetup); +} + +Configuration from_path(const std::string &path) +{ + std::ifstream file(path); + json simulation = json::parse(file).at("simulation"); + return simulation.get(); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h index 069a5147..9385d13a 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.h +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -57,7 +57,7 @@ * Consider also switching to std::variant to achieve static polymorphism. */ -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; @@ -75,6 +75,8 @@ struct Configuration void to_json(json &j, const Configuration &p); void from_json(const json &j, Configuration &p); +Configuration from_path(const std::string &path); + } // namespace Configuration #endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp index b0ad41ec..daaf66d0 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.cpp +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -36,7 +36,7 @@ #include "McConfig.h" #include "util.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const McConfig &c) @@ -54,25 +54,27 @@ void to_json(json &j, const McConfig &c) {"Arbiter", c.arbiter}, {"MaxActiveTransactions", c.maxActiveTransactions}}; - Util::from_optional("RefreshManagment", j, c.refreshManagement); + from_optional("RefreshManagment", j, c.refreshManagement); } void from_json(const json &j, McConfig &c) { - j.at("PagePolicy").get_to(c.pagePolicy); - j.at("Scheduler").get_to(c.scheduler); - j.at("SchedulerBuffer").get_to(c.schedulerBuffer); - j.at("RequestBufferSize").get_to(c.requestBufferSize); - j.at("CmdMux").get_to(c.cmdMux); - j.at("RespQueue").get_to(c.respQueue); - j.at("RefreshPolicy").get_to(c.refreshPolicy); - j.at("RefreshMaxPostponed").get_to(c.refreshMaxPostponed); - j.at("RefreshMaxPulledin").get_to(c.refreshMaxPulledin); - j.at("PowerDownPolicy").get_to(c.powerDownPolicy); - j.at("Arbiter").get_to(c.arbiter); - j.at("MaxActiveTransactions").get_to(c.maxActiveTransactions); + json j_mcconfig = get_config_json(j, mcConfigPath, "mcconfig"); - Util::get_optional("RefreshManagment", j, c.refreshManagement); + j_mcconfig.at("PagePolicy").get_to(c.pagePolicy); + j_mcconfig.at("Scheduler").get_to(c.scheduler); + j_mcconfig.at("SchedulerBuffer").get_to(c.schedulerBuffer); + j_mcconfig.at("RequestBufferSize").get_to(c.requestBufferSize); + j_mcconfig.at("CmdMux").get_to(c.cmdMux); + j_mcconfig.at("RespQueue").get_to(c.respQueue); + j_mcconfig.at("RefreshPolicy").get_to(c.refreshPolicy); + j_mcconfig.at("RefreshMaxPostponed").get_to(c.refreshMaxPostponed); + j_mcconfig.at("RefreshMaxPulledin").get_to(c.refreshMaxPulledin); + j_mcconfig.at("PowerDownPolicy").get_to(c.powerDownPolicy); + j_mcconfig.at("Arbiter").get_to(c.arbiter); + j_mcconfig.at("MaxActiveTransactions").get_to(c.maxActiveTransactions); + + get_optional("RefreshManagment", j_mcconfig, c.refreshManagement); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index d265e022..363a06b8 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -40,10 +40,12 @@ #include #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; +const std::string mcConfigPath = "configs/mcconfigs"; + enum class PagePolicy { Open, diff --git a/DRAMSys/library/src/common/configuration/SimConfig.cpp b/DRAMSys/library/src/common/configuration/SimConfig.cpp index 91acde69..77903e0b 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.cpp +++ b/DRAMSys/library/src/common/configuration/SimConfig.cpp @@ -34,8 +34,9 @@ */ #include "SimConfig.h" +#include "util.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const SimConfig &c) @@ -59,21 +60,23 @@ void to_json(json &j, const SimConfig &c) void from_json(const json &j, SimConfig &c) { - j.at("AddressOffset").get_to(c.addressOffset); - j.at("CheckTLM2Protocol").get_to(c.checkTLM2Protocol); - j.at("DatabaseRecording").get_to(c.databaseRecording); - j.at("Debug").get_to(c.debug); - j.at("ECCControllerMode").get_to(c.eccControllerMode); - j.at("EnableWindowing").get_to(c.enableWindowing); - j.at("ErrorCSVFile").get_to(c.errorCsvFile); - j.at("ErrorChipSeed").get_to(c.errorChipSeed); - j.at("PowerAnalysis").get_to(c.powerAnalysis); - j.at("SimulationName").get_to(c.simulationName); - j.at("SimulationProgressBar").get_to(c.simulationProgressBar); - j.at("StoreMode").get_to(c.storeMode); - j.at("ThermalSimulation").get_to(c.thermalSimulation); - j.at("UseMalloc").get_to(c.useMalloc); - j.at("WindowSize").get_to(c.windowSize); + json j_simconfig = get_config_json(j, simConfigPath, "simconfig"); + + j_simconfig.at("AddressOffset").get_to(c.addressOffset); + j_simconfig.at("CheckTLM2Protocol").get_to(c.checkTLM2Protocol); + j_simconfig.at("DatabaseRecording").get_to(c.databaseRecording); + j_simconfig.at("Debug").get_to(c.debug); + j_simconfig.at("ECCControllerMode").get_to(c.eccControllerMode); + j_simconfig.at("EnableWindowing").get_to(c.enableWindowing); + j_simconfig.at("ErrorCSVFile").get_to(c.errorCsvFile); + j_simconfig.at("ErrorChipSeed").get_to(c.errorChipSeed); + j_simconfig.at("PowerAnalysis").get_to(c.powerAnalysis); + j_simconfig.at("SimulationName").get_to(c.simulationName); + j_simconfig.at("SimulationProgressBar").get_to(c.simulationProgressBar); + j_simconfig.at("StoreMode").get_to(c.storeMode); + j_simconfig.at("ThermalSimulation").get_to(c.thermalSimulation); + j_simconfig.at("UseMalloc").get_to(c.useMalloc); + j_simconfig.at("WindowSize").get_to(c.windowSize); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/SimConfig.h b/DRAMSys/library/src/common/configuration/SimConfig.h index 7d23ff75..b28d131d 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.h +++ b/DRAMSys/library/src/common/configuration/SimConfig.h @@ -38,10 +38,12 @@ #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; +const std::string simConfigPath = "configs/simulator"; + enum class ECCControllerMode { Disabled, diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp index e593fcbe..6c69daec 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp @@ -34,8 +34,9 @@ */ #include "ThermalConfig.h" +#include "util.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const ThermalConfig &c) @@ -55,17 +56,19 @@ void to_json(json &j, const ThermalConfig &c) void from_json(const json &j, ThermalConfig &c) { - j.at("TemperatureScale").get_to(c.temperatureScale); - j.at("StaticTemperatureDefaultValue").get_to(c.staticTemperatureDefaultValue); - j.at("ThermalSimPeriod").get_to(c.thermalSimPeriod); - j.at("ThermalSimUnit").get_to(c.thermalSimUnit); - j.at("PowerInfoFile").get_to(c.powerInfo); - j.at("IceServerIp").get_to(c.iceServerIp); - j.at("IceServerPort").get_to(c.iceServerPort); - j.at("SimPeriodAdjustFactor").get_to(c.simPeriodAdjustFactor); - j.at("NPowStableCyclesToIncreasePeriod").get_to(c.nPowStableCyclesToIncreasePeriod); - j.at("GenerateTemperatureMap").get_to(c.generateTemperatureMap); - j.at("GeneratePowerMap").get_to(c.generatePowerMap); + json j_thermalsim = get_config_json(j, thermalConfigPath, "thermalsimconfig"); + + j_thermalsim.at("TemperatureScale").get_to(c.temperatureScale); + j_thermalsim.at("StaticTemperatureDefaultValue").get_to(c.staticTemperatureDefaultValue); + j_thermalsim.at("ThermalSimPeriod").get_to(c.thermalSimPeriod); + j_thermalsim.at("ThermalSimUnit").get_to(c.thermalSimUnit); + j_thermalsim.at("PowerInfoFile").get_to(c.powerInfo); + j_thermalsim.at("IceServerIp").get_to(c.iceServerIp); + j_thermalsim.at("IceServerPort").get_to(c.iceServerPort); + j_thermalsim.at("SimPeriodAdjustFactor").get_to(c.simPeriodAdjustFactor); + j_thermalsim.at("NPowStableCyclesToIncreasePeriod").get_to(c.nPowStableCyclesToIncreasePeriod); + j_thermalsim.at("GenerateTemperatureMap").get_to(c.generateTemperatureMap); + j_thermalsim.at("GeneratePowerMap").get_to(c.generatePowerMap); } void to_json(json &j, const DramDieChannel &c) @@ -89,10 +92,12 @@ void to_json(json &j, const PowerInfo &c) void from_json(const json &j, PowerInfo &c) { - j.at("dram_die_channel0").get_to(c.channel0); - j.at("dram_die_channel1").get_to(c.channel1); - j.at("dram_die_channel2").get_to(c.channel2); - j.at("dram_die_channel3").get_to(c.channel3); + json j_powerinfo = get_config_json(j, thermalConfigPath, "powerInfo"); + + j_powerinfo.at("dram_die_channel0").get_to(c.channel0); + j_powerinfo.at("dram_die_channel1").get_to(c.channel1); + j_powerinfo.at("dram_die_channel2").get_to(c.channel2); + j_powerinfo.at("dram_die_channel3").get_to(c.channel3); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.h b/DRAMSys/library/src/common/configuration/ThermalConfig.h index a6e6fd34..02c905b6 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.h +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.h @@ -38,10 +38,12 @@ #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; +const std::string thermalConfigPath = "configs/thermalsim"; + enum class TemperatureScale { Celsius, diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index e39452fc..39b76790 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -36,7 +36,7 @@ #include "TraceSetup.h" #include "util.h" -namespace Configuration +namespace DRAMSysConfiguration { TrafficInitiator::~TrafficInitiator() @@ -62,11 +62,11 @@ void to_json(json &j, const TraceSetup &c) inititator_j["rwRatio"] = generator->rwRatio; inititator_j["addressDistribution"] = generator->addressDistribution; - Util::from_optional("seed", inititator_j, generator->seed); - Util::from_optional("maxPendingReadRequests", inititator_j, generator->maxPendingReadRequests); - Util::from_optional("maxPendingWriteRequests", inititator_j, generator->maxPendingWriteRequests); - Util::from_optional("minAddress", inititator_j, generator->minAddress); - Util::from_optional("maxAddress", inititator_j, generator->maxAddress); + from_optional("seed", inititator_j, generator->seed); + from_optional("maxPendingReadRequests", inititator_j, generator->maxPendingReadRequests); + from_optional("maxPendingWriteRequests", inititator_j, generator->maxPendingWriteRequests); + from_optional("minAddress", inititator_j, generator->minAddress); + from_optional("maxAddress", inititator_j, generator->maxAddress); } else if (const auto hammer = dynamic_cast(initiator.get())) { @@ -103,11 +103,11 @@ void from_json(const json &j, TraceSetup &c) initiator_j.at("rwRatio").get_to(generator->rwRatio); initiator_j.at("addressDistribution").get_to(generator->addressDistribution); - Util::get_optional("seed", initiator_j, generator->seed); - Util::get_optional("maxPendingReadRequests", initiator_j, generator->maxPendingReadRequests); - Util::get_optional("maxPendingWriteRequests", initiator_j, generator->maxPendingWriteRequests); - Util::get_optional("minAddress", initiator_j, generator->minAddress); - Util::get_optional("maxAddress", initiator_j, generator->maxAddress); + get_optional("seed", initiator_j, generator->seed); + get_optional("maxPendingReadRequests", initiator_j, generator->maxPendingReadRequests); + get_optional("maxPendingWriteRequests", initiator_j, generator->maxPendingWriteRequests); + get_optional("minAddress", initiator_j, generator->minAddress); + get_optional("maxAddress", initiator_j, generator->maxAddress); initiator = std::unique_ptr(generator); } diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index d3974ec6..61361bc2 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -40,7 +40,7 @@ #include #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; diff --git a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp index 5de2684b..ce2b33d2 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.cpp @@ -35,7 +35,7 @@ #include "MemArchitectureSpec.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const MemArchitectureSpec &c) diff --git a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h index cd516ad2..80a18ecc 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h @@ -39,7 +39,7 @@ #include #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; diff --git a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp index 6621fabc..0cdb3059 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.cpp @@ -35,7 +35,7 @@ #include "MemPowerSpec.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const MemPowerSpec &c) diff --git a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h index 5c201580..8d125a44 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h @@ -39,7 +39,7 @@ #include #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp index 8bdcf0ef..29def6d8 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp @@ -36,7 +36,7 @@ #include "MemSpec.h" #include "util.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const MemSpec &c) @@ -46,17 +46,19 @@ void to_json(json &j, const MemSpec &c) {"memoryType", c.memoryType}, {"memtimingspec", c.memTimingSpec}}; - Util::from_optional("mempowerspec", j, c.memPowerSpec); + from_optional("mempowerspec", j, c.memPowerSpec); } void from_json(const json &j, MemSpec &c) { - j.at("memarchitecturespec").get_to(c.memArchitectureSpec); - j.at("memoryId").get_to(c.memoryId); - j.at("memoryType").get_to(c.memoryType); - j.at("memtimingspec").get_to(c.memTimingSpec); + json j_memspecs = get_config_json(j, memSpecPath, "memspec"); - Util::get_optional("mempowerspec", j, c.memPowerSpec); + j_memspecs.at("memarchitecturespec").get_to(c.memArchitectureSpec); + j_memspecs.at("memoryId").get_to(c.memoryId); + j_memspecs.at("memoryType").get_to(c.memoryType); + j_memspecs.at("memtimingspec").get_to(c.memTimingSpec); + + get_optional("mempowerspec", j, c.memPowerSpec); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h index 5d716963..248709b4 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h @@ -42,10 +42,12 @@ #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; +const std::string memSpecPath = "configs/memspecs"; + struct MemSpec { MemArchitectureSpec memArchitectureSpec; diff --git a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp index 0b41f8cf..27414e57 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.cpp @@ -35,7 +35,7 @@ #include "MemTimingSpec.h" -namespace Configuration +namespace DRAMSysConfiguration { void to_json(json &j, const MemTimingSpec &c) diff --git a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h index 6203803b..61ba7308 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h @@ -39,7 +39,7 @@ #include #include -namespace Configuration +namespace DRAMSysConfiguration { using json = nlohmann::json; diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 4c7f2b1a..1be7c5e5 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -4,126 +4,105 @@ using json = nlohmann::json; -Configuration::AddressMapping getAddressMapping() +DRAMSysConfiguration::AddressMapping getAddressMapping() { - // Configuration::ConGen *mycongen = new Configuration::ConGen; - // mycongen->byteBits = {{0, 1}, true}; - // mycongen->bankBits = {16}; - // mycongen->bankGroupBits = {{13, 14, 15}, true}; - // mycongen->coloumnBits = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}; - // mycongen->channelBits = {{33}, true}; - // mycongen->rowBits = {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; - // return std::unique_ptr(mycongen); - - return Configuration::AddressMapping{{{0, 1}, true}, - {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, - {16}, - {{13, 14, 15}, true}, - {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}, - {{33}, true}, - {{}, false}}; + return DRAMSysConfiguration::AddressMapping{{{0, 1}, true}, + {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, + {16}, + {{13, 14, 15}, true}, + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}, + {{33}, true}, + {{}, false}}; } -Configuration::McConfig getMcConfig() +DRAMSysConfiguration::McConfig getMcConfig() { - return Configuration::McConfig{Configuration::PagePolicy::Open, - Configuration::Scheduler::FrFcfs, - Configuration::SchedulerBuffer::Bankwise, - 8, - Configuration::CmdMux::Oldest, - Configuration::RespQueue::Fifo, - Configuration::RefreshPolicy::AllBank, - 0, - 0, - Configuration::PowerDownPolicy::NoPowerDown, - Configuration::Arbiter::Simple, - 128, - std::pair{false, true}}; + return DRAMSysConfiguration::McConfig{DRAMSysConfiguration::PagePolicy::Open, + DRAMSysConfiguration::Scheduler::FrFcfs, + DRAMSysConfiguration::SchedulerBuffer::Bankwise, + 8, + DRAMSysConfiguration::CmdMux::Oldest, + DRAMSysConfiguration::RespQueue::Fifo, + DRAMSysConfiguration::RefreshPolicy::AllBank, + 0, + 0, + DRAMSysConfiguration::PowerDownPolicy::NoPowerDown, + DRAMSysConfiguration::Arbiter::Simple, + 128, + std::pair{false, true}}; } -Configuration::SimConfig getSimConfig() +DRAMSysConfiguration::SimConfig getSimConfig() { - return Configuration::SimConfig { - 0, - false, + return DRAMSysConfiguration::SimConfig{ + 0, false, true, false, DRAMSysConfiguration::ECCControllerMode::Disabled, false, "error.csv", + 42, false, "ddr5", true, DRAMSysConfiguration::StoreMode::NoStorage, false, false, + 1000}; +} + +DRAMSysConfiguration::ThermalConfig getThermalConfig() +{ + return DRAMSysConfiguration::ThermalConfig{ + DRAMSysConfiguration::TemperatureScale::Celsius, + 89, + 100, + DRAMSysConfiguration::ThermalSimUnit::Microseconds, + DRAMSysConfiguration::PowerInfo{{0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}}, + "127.0.0.1", + 118800, + 10, + 5, true, - false, - Configuration::ECCControllerMode::Disabled, - false, - "error.csv", - 42, - false, - "ddr5", - true, - Configuration::StoreMode::NoStorage, - false, - false, - 1000 - }; + true}; } -Configuration::ThermalConfig getThermalConfig() +std::unique_ptr getTracePlayer() { - return Configuration::ThermalConfig{Configuration::TemperatureScale::Celsius, - 89, - 100, - Configuration::ThermalSimUnit::Microseconds, - Configuration::PowerInfo{{0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}}, - "127.0.0.1", - 118800, - 10, - 5, - true, - true}; -} - -std::unique_ptr getTracePlayer() -{ - Configuration::TracePlayer *player = new Configuration::TracePlayer; + DRAMSysConfiguration::TracePlayer *player = new DRAMSysConfiguration::TracePlayer; player->clkMhz = 100; player->name = "mytrace.stl"; - return std::unique_ptr(player); + return std::unique_ptr(player); } -std::unique_ptr getTraceGeneratorRandom() +std::unique_ptr getTraceGeneratorRandom() { - Configuration::TraceGenerator *gen = new Configuration::TraceGenerator; + DRAMSysConfiguration::TraceGenerator *gen = new DRAMSysConfiguration::TraceGenerator; gen->clkMhz = 100; gen->name = "MyTestGen"; - gen->addressDistribution = Configuration::AddressDistribution::Random; + gen->addressDistribution = DRAMSysConfiguration::AddressDistribution::Random; gen->maxAddress = {1000, true}; gen->maxPendingReadRequests = {8, true}; gen->rwRatio = 0.5; gen->seed = {1337, true}; gen->numRequests = 1000; - return std::unique_ptr(gen); + return std::unique_ptr(gen); } -std::unique_ptr getTraceGeneratorSequential() +std::unique_ptr getTraceGeneratorSequential() { - Configuration::TraceGenerator *gen = new Configuration::TraceGenerator; + DRAMSysConfiguration::TraceGenerator *gen = new DRAMSysConfiguration::TraceGenerator; gen->clkMhz = 100; gen->name = "MyTestGen"; - gen->addressDistribution = Configuration::AddressDistribution::Sequential; + gen->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; gen->addressIncrement = {64, true}; gen->maxAddress = {1000, true}; gen->maxPendingReadRequests = {8, true}; gen->rwRatio = 0.5; gen->numRequests = 1000; - return std::unique_ptr(gen); + return std::unique_ptr(gen); } -std::unique_ptr getTraceHammer() +std::unique_ptr getTraceHammer() { - Configuration::TraceHammer *hammer = new Configuration::TraceHammer; + DRAMSysConfiguration::TraceHammer *hammer = new DRAMSysConfiguration::TraceHammer; hammer->clkMhz = 100; hammer->name = "MyTestHammer"; @@ -131,23 +110,23 @@ std::unique_ptr getTraceHammer() hammer->numRequests = 4000; hammer->rowIncrement = 2097152; - return std::unique_ptr(hammer); + return std::unique_ptr(hammer); } -Configuration::TraceSetup getTraceSetup() +DRAMSysConfiguration::TraceSetup getTraceSetup() { - std::unordered_set> initiators; + std::unordered_set> initiators; initiators.emplace(getTracePlayer()); initiators.emplace(getTraceGeneratorRandom()); initiators.emplace(getTraceGeneratorSequential()); initiators.emplace(getTraceHammer()); - return Configuration::TraceSetup{std::move(initiators)}; + return DRAMSysConfiguration::TraceSetup{std::move(initiators)}; } -Configuration::Configuration getConfig(const Configuration::MemSpec &memSpec) +DRAMSysConfiguration::Configuration getConfig(const DRAMSysConfiguration::MemSpec &memSpec) { - return Configuration::Configuration{ + return DRAMSysConfiguration::Configuration{ getAddressMapping(), getMcConfig(), memSpec, @@ -161,10 +140,7 @@ Configuration::Configuration getConfig(const Configuration::MemSpec &memSpec) int main() { - std::ifstream file("ddr5.json"); - json ddr5_j = json::parse(file, nullptr, false); - json config = ddr5_j.at("simulation"); - Configuration::Configuration conf = config.get(); + DRAMSysConfiguration::Configuration conf = DRAMSysConfiguration::from_path("ddr5.json"); std::ofstream fileout("myjson.json"); json j_my; j_my["simulation"] = getConfig(conf.memSpec); // just copy memspec over @@ -173,9 +149,18 @@ int main() std::ifstream file2("hbm2.json"); json hbm2_j = json::parse(file2, nullptr, false); json hbm2_config = hbm2_j.at("simulation"); - Configuration::Configuration hbm2conf = hbm2_config.get(); + DRAMSysConfiguration::Configuration hbm2conf = hbm2_config.get(); std::ofstream filehbm2("myhbm2.json"); json j_myhbm2; j_myhbm2["simulation"] = hbm2conf; filehbm2 << j_myhbm2.dump(4); + + std::ifstream file3("old_conf.json"); + json ddr5_old = json::parse(file3, nullptr, false); + json ddr5_old_conf = ddr5_old.at("simulation"); + DRAMSysConfiguration::Configuration ddr5_old_config = ddr5_old_conf.get(); + std::ofstream fileoldout("old_conf_converted.json"); + json j_oldconfconv; + j_oldconfconv["simulation"] = ddr5_old_config; + fileoldout << j_oldconfconv.dump(4); } diff --git a/DRAMSys/library/src/common/configuration/util.cpp b/DRAMSys/library/src/common/configuration/util.cpp new file mode 100644 index 00000000..d4d3ef29 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/util.cpp @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "util.h" + +#include + +namespace DRAMSysConfiguration +{ + +json get_config_json(const json &j, const std::string &configPath, const std::string &objectName) +{ + if (j.is_object()) + { + return j; + } + else // j should be a string path to the real json file + { + std::string jsonFileName; + j.get_to(jsonFileName); + + std::ifstream file(std::string(DRAMSysResourceDirectory) + "/" + configPath + "/" + jsonFileName); + json j_object = json::parse(file); + return j_object.at(objectName); + } +} + +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/util.h b/DRAMSys/library/src/common/configuration/util.h index 1f25489c..113c3265 100644 --- a/DRAMSys/library/src/common/configuration/util.h +++ b/DRAMSys/library/src/common/configuration/util.h @@ -39,7 +39,7 @@ #include #include -namespace Util +namespace DRAMSysConfiguration { using json = nlohmann::json; @@ -70,6 +70,8 @@ void from_optional(const std::string &name, json &j, const std::pair &v } } -} // namespace Util +json get_config_json(const json &j, const std::string &configPath, const std::string &objectName); + +} // namespace DRAMSysConfiguration #endif From 778b974c0fd228c4c052a4218d7adcbacde50f47 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 2 Nov 2021 14:42:04 +0100 Subject: [PATCH 03/23] Introduce an own optional type for configuration lib --- .../common/configuration/AddressMapping.cpp | 29 +++--- .../src/common/configuration/AddressMapping.h | 14 +-- .../src/common/configuration/CMakeLists.txt | 4 +- .../common/configuration/Configuration.cpp | 21 ++--- .../src/common/configuration/Configuration.h | 13 +-- .../src/common/configuration/McConfig.cpp | 70 ++++++++++---- .../src/common/configuration/McConfig.h | 32 ++++--- .../src/common/configuration/SimConfig.cpp | 65 +++++++++---- .../src/common/configuration/SimConfig.h | 37 ++++---- .../common/configuration/ThermalConfig.cpp | 2 +- .../src/common/configuration/ThermalConfig.h | 4 +- .../src/common/configuration/TraceSetup.cpp | 34 ++++--- .../src/common/configuration/TraceSetup.h | 20 ++-- .../memspec/MemArchitectureSpec.h | 4 +- .../configuration/memspec/MemPowerSpec.h | 4 +- .../common/configuration/memspec/MemSpec.cpp | 9 +- .../common/configuration/memspec/MemSpec.h | 7 +- .../configuration/memspec/MemTimingSpec.h | 4 +- .../common/configuration/tests/simpletest.cpp | 34 +++---- .../library/src/common/configuration/util.h | 92 +++++++++++++++---- 20 files changed, 323 insertions(+), 176 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp index b3277d89..7b2237cc 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.cpp +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -34,7 +34,6 @@ */ #include "AddressMapping.h" -#include "util.h" #include @@ -49,12 +48,11 @@ void to_json(json &j, const AddressMapping &m) {"COLUMN_BIT", m.coloumnBits}, {"BANKGROUP_BIT", m.bankGroupBits}, {"BANK_BIT", m.bankBits}, - {"ROW_BIT", m.rowBits}}; - - from_optional("CHANNEL_BIT", congen, m.channelBits); - from_optional("BYTE_BIT", congen, m.byteBits); - from_optional("BANKGROUP_BIT", congen, m.bankGroupBits); - from_optional("XOR", congen, m.xorBits); + {"ROW_BIT", m.rowBits}, + {"CHANNEL_BIT", m.channelBits}, + {"BYTE_BIT", m.byteBits}, + {"BANKGROUP_BIT", m.bankGroupBits}, + {"XOR", m.xorBits}}; j["CONGEN"] = congen; } @@ -73,10 +71,17 @@ void from_json(const json &j, AddressMapping &m) congen.at("BANK_BIT").get_to(m.bankBits); congen.at("ROW_BIT").get_to(m.rowBits); - get_optional("CHANNEL_BIT", congen, m.channelBits); - get_optional("BYTE_BIT", congen, m.byteBits); - get_optional("BANKGROUP_BIT", congen, m.bankGroupBits); - get_optional("XOR", congen, m.xorBits); + if (congen.contains("CHANNEL_BIT")) + congen.at("CHANNEL_BIT").get_to(m.channelBits); + + if (congen.contains("BYTE_BIT")) + congen.at("BYTE_BIT").get_to(m.byteBits); + + if (congen.contains("BANKGROUP_BIT")) + congen.at("BANKGROUP_BIT").get_to(m.bankGroupBits); + + if (congen.contains("XOR")) + congen.at("XOR").get_to(m.xorBits); } void to_json(json &j, const XorPair &x) @@ -90,4 +95,4 @@ void from_json(const json &j, XorPair &x) j.at("SECOND").get_to(x.second); } -} // namespace Configuration +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index 07c4cda0..ffcc3ca2 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -33,8 +33,10 @@ * Derek Christ */ -#ifndef ADDRESSMAPPING_H -#define ADDRESSMAPPING_H +#ifndef DRAMSYSCONFIGURATION_ADDRESSMAPPING_H +#define DRAMSYSCONFIGURATION_ADDRESSMAPPING_H + +#include "util.h" #include #include @@ -56,13 +58,13 @@ void from_json(const json &j, XorPair &x); struct AddressMapping { - std::pair, bool> byteBits; + Optional> byteBits; std::unordered_set coloumnBits; std::unordered_set bankBits; - std::pair, bool> bankGroupBits; + Optional> bankGroupBits; std::unordered_set rowBits; - std::pair, bool> channelBits; - std::pair, bool> xorBits; + Optional> channelBits; + Optional> xorBits; }; void to_json(json &j, const AddressMapping &m); diff --git a/DRAMSys/library/src/common/configuration/CMakeLists.txt b/DRAMSys/library/src/common/configuration/CMakeLists.txt index d62c5fdc..bd199eae 100644 --- a/DRAMSys/library/src/common/configuration/CMakeLists.txt +++ b/DRAMSys/library/src/common/configuration/CMakeLists.txt @@ -32,6 +32,7 @@ # Derek Christ set(JSON_BuildTests OFF CACHE INTERNAL "") +set(JSON_ImplicitConversions OFF CACHE INTERNAL "") add_subdirectory(${CMAKE_SOURCE_DIR}/library/src/common/third_party/nlohmann ${CMAKE_CURRENT_BINARY_DIR}/nlohmann) option(DRAMSYS_CONFIGURATION_TESTS "Build the unit tests for configuration." OFF) @@ -56,5 +57,6 @@ add_library(DRAMSysConfiguration STATIC target_compile_definitions(DRAMSysConfiguration PRIVATE DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources") -target_link_libraries(DRAMSysConfiguration PRIVATE nlohmann_json::nlohmann_json) target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) + +target_link_libraries(DRAMSysConfiguration PRIVATE nlohmann_json::nlohmann_json) diff --git a/DRAMSys/library/src/common/configuration/Configuration.cpp b/DRAMSys/library/src/common/configuration/Configuration.cpp index 006db6f2..c610f579 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.cpp +++ b/DRAMSys/library/src/common/configuration/Configuration.cpp @@ -34,7 +34,6 @@ */ #include "Configuration.h" -#include "util.h" #include @@ -43,14 +42,11 @@ namespace DRAMSysConfiguration void to_json(json &j, const Configuration &c) { - j = json{{"addressmapping", c.addressMapping}, - {"mcconfig", c.mcConfig}, - {"memspec", c.memSpec}, - {"simulationid", c.simulationId}, - {"simconfig", c.simConfig}}; + j = json{{"addressmapping", c.addressMapping}, {"mcconfig", c.mcConfig}, {"memspec", c.memSpec}, + {"simulationid", c.simulationId}, {"simconfig", c.simConfig}, {"thermalconfig", c.thermalConfig}, + {"tracesetup", c.traceSetup}}; - from_optional("thermalconfig", j, c.thermalConfig); - from_optional("tracesetup", j, c.traceSetup); + remove_null_values(j); } void from_json(const json &j, Configuration &c) @@ -61,8 +57,11 @@ void from_json(const json &j, Configuration &c) j.at("simulationid").get_to(c.simulationId); j.at("simconfig").get_to(c.simConfig); - get_optional("thermalconfig", j, c.thermalConfig); - get_optional("tracesetup", j, c.traceSetup); + if (j.contains("thermalconfig")) + j.at("thermalconfig").get_to(c.thermalConfig); + + if (j.contains("tracesetup")) + j.at("tracesetup").get_to(c.traceSetup); } Configuration from_path(const std::string &path) @@ -72,4 +71,4 @@ Configuration from_path(const std::string &path) return simulation.get(); } -} // namespace Configuration +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h index 9385d13a..676036ec 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.h +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -33,8 +33,8 @@ * Derek Christ */ -#ifndef CONFIGURATION_H -#define CONFIGURATION_H +#ifndef DRAMSYSCONFIGURATION_CONFIGURATION_H +#define DRAMSYSCONFIGURATION_CONFIGURATION_H #include "AddressMapping.h" #include "McConfig.h" @@ -42,6 +42,7 @@ #include "ThermalConfig.h" #include "TraceSetup.h" #include "memspec/MemSpec.h" +#include "util.h" #include #include @@ -68,8 +69,8 @@ struct Configuration MemSpec memSpec; SimConfig simConfig; std::string simulationId; - std::pair thermalConfig; - std::pair traceSetup; + Optional thermalConfig; + Optional traceSetup; }; void to_json(json &j, const Configuration &p); @@ -77,6 +78,6 @@ void from_json(const json &j, Configuration &p); Configuration from_path(const std::string &path); -} // namespace Configuration +} // namespace DRAMSysConfiguration -#endif // CONFIGURATION_H +#endif // DRAMSYSCONFIGURATION_CONFIGURATION_H diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp index daaf66d0..50684665 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.cpp +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -34,8 +34,7 @@ */ #include "McConfig.h" -#include "util.h" - +#include namespace DRAMSysConfiguration { @@ -52,29 +51,64 @@ void to_json(json &j, const McConfig &c) {"RefreshMaxPulledin", c.refreshMaxPulledin}, {"PowerDownPolicy", c.powerDownPolicy}, {"Arbiter", c.arbiter}, - {"MaxActiveTransactions", c.maxActiveTransactions}}; + {"MaxActiveTransactions", c.maxActiveTransactions}, + {"RefreshManagment", c.refreshManagement}}; - from_optional("RefreshManagment", j, c.refreshManagement); + remove_null_values(j); } void from_json(const json &j, McConfig &c) { json j_mcconfig = get_config_json(j, mcConfigPath, "mcconfig"); - j_mcconfig.at("PagePolicy").get_to(c.pagePolicy); - j_mcconfig.at("Scheduler").get_to(c.scheduler); - j_mcconfig.at("SchedulerBuffer").get_to(c.schedulerBuffer); - j_mcconfig.at("RequestBufferSize").get_to(c.requestBufferSize); - j_mcconfig.at("CmdMux").get_to(c.cmdMux); - j_mcconfig.at("RespQueue").get_to(c.respQueue); - j_mcconfig.at("RefreshPolicy").get_to(c.refreshPolicy); - j_mcconfig.at("RefreshMaxPostponed").get_to(c.refreshMaxPostponed); - j_mcconfig.at("RefreshMaxPulledin").get_to(c.refreshMaxPulledin); - j_mcconfig.at("PowerDownPolicy").get_to(c.powerDownPolicy); - j_mcconfig.at("Arbiter").get_to(c.arbiter); - j_mcconfig.at("MaxActiveTransactions").get_to(c.maxActiveTransactions); + if (j_mcconfig.contains("PagePolicy")) + j_mcconfig.at("PagePolicy").get_to(c.pagePolicy); - get_optional("RefreshManagment", j_mcconfig, c.refreshManagement); + if (j_mcconfig.contains("PagePolicy")) + j_mcconfig.at("Scheduler").get_to(c.scheduler); + + if (j_mcconfig.contains("SchedulerBuffer")) + j_mcconfig.at("SchedulerBuffer").get_to(c.schedulerBuffer); + + if (j_mcconfig.contains("RequestBufferSize")) + j_mcconfig.at("RequestBufferSize").get_to(c.requestBufferSize); + + if (j_mcconfig.contains("CmdMux")) + j_mcconfig.at("CmdMux").get_to(c.cmdMux); + + if (j_mcconfig.contains("RespQueue")) + j_mcconfig.at("RespQueue").get_to(c.respQueue); + + if (j_mcconfig.contains("RefreshPolicy")) + j_mcconfig.at("RefreshPolicy").get_to(c.refreshPolicy); + + if (j_mcconfig.contains("RefreshMaxPostponed")) + j_mcconfig.at("RefreshMaxPostponed").get_to(c.refreshMaxPostponed); + + if (j_mcconfig.contains("RefreshMaxPulledin")) + j_mcconfig.at("RefreshMaxPulledin").get_to(c.refreshMaxPulledin); + + if (j_mcconfig.contains("PowerDownPolicy")) + j_mcconfig.at("PowerDownPolicy").get_to(c.powerDownPolicy); + + if (j_mcconfig.contains("Arbiter")) + j_mcconfig.at("Arbiter").get_to(c.arbiter); + + if (j_mcconfig.contains("MaxActiveTransactions")) + j_mcconfig.at("MaxActiveTransactions").get_to(c.maxActiveTransactions); + + if (j_mcconfig.contains("RefreshManagment")) + j_mcconfig.at("RefreshManagment").get_to(c.refreshManagement); + + invalidateEnum(c.pagePolicy); + invalidateEnum(c.scheduler); + invalidateEnum(c.schedulerBuffer); + invalidateEnum(c.cmdMux); + invalidateEnum(c.respQueue); + invalidateEnum(c.refreshPolicy); + invalidateEnum(c.respQueue); + invalidateEnum(c.powerDownPolicy); + invalidateEnum(c.arbiter); } -} // namespace Configuration +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index 363a06b8..649d81bb 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -33,8 +33,10 @@ * Derek Christ */ -#ifndef MCCONFIG_H -#define MCCONFIG_H +#ifndef DRAMSYSCONFIGURATION_MCCONFIG_H +#define DRAMSYSCONFIGURATION_MCCONFIG_H + +#include "util.h" #include #include @@ -150,19 +152,19 @@ NLOHMANN_JSON_SERIALIZE_ENUM(Arbiter, {{Arbiter::Invalid, nullptr}, struct McConfig { - PagePolicy pagePolicy; - Scheduler scheduler; - SchedulerBuffer schedulerBuffer; - unsigned int requestBufferSize; - CmdMux cmdMux; - RespQueue respQueue; - RefreshPolicy refreshPolicy; - unsigned int refreshMaxPostponed; - unsigned int refreshMaxPulledin; - PowerDownPolicy powerDownPolicy; - Arbiter arbiter; - unsigned int maxActiveTransactions; - std::pair refreshManagement; + Optional pagePolicy; + Optional scheduler; + Optional schedulerBuffer; + Optional requestBufferSize; + Optional cmdMux; + Optional respQueue; + Optional refreshPolicy; + Optional refreshMaxPostponed; + Optional refreshMaxPulledin; + Optional powerDownPolicy; + Optional arbiter; + Optional maxActiveTransactions; + Optional refreshManagement; }; void to_json(json &j, const McConfig &c); diff --git a/DRAMSys/library/src/common/configuration/SimConfig.cpp b/DRAMSys/library/src/common/configuration/SimConfig.cpp index 77903e0b..34cc41ef 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.cpp +++ b/DRAMSys/library/src/common/configuration/SimConfig.cpp @@ -34,7 +34,6 @@ */ #include "SimConfig.h" -#include "util.h" namespace DRAMSysConfiguration { @@ -62,21 +61,53 @@ void from_json(const json &j, SimConfig &c) { json j_simconfig = get_config_json(j, simConfigPath, "simconfig"); - j_simconfig.at("AddressOffset").get_to(c.addressOffset); - j_simconfig.at("CheckTLM2Protocol").get_to(c.checkTLM2Protocol); - j_simconfig.at("DatabaseRecording").get_to(c.databaseRecording); - j_simconfig.at("Debug").get_to(c.debug); - j_simconfig.at("ECCControllerMode").get_to(c.eccControllerMode); - j_simconfig.at("EnableWindowing").get_to(c.enableWindowing); - j_simconfig.at("ErrorCSVFile").get_to(c.errorCsvFile); - j_simconfig.at("ErrorChipSeed").get_to(c.errorChipSeed); - j_simconfig.at("PowerAnalysis").get_to(c.powerAnalysis); - j_simconfig.at("SimulationName").get_to(c.simulationName); - j_simconfig.at("SimulationProgressBar").get_to(c.simulationProgressBar); - j_simconfig.at("StoreMode").get_to(c.storeMode); - j_simconfig.at("ThermalSimulation").get_to(c.thermalSimulation); - j_simconfig.at("UseMalloc").get_to(c.useMalloc); - j_simconfig.at("WindowSize").get_to(c.windowSize); + if (j_simconfig.contains("AddressOffset")) + j_simconfig.at("AddressOffset").get_to(c.addressOffset); + + if (j_simconfig.contains("CheckTLM2Protocol")) + j_simconfig.at("CheckTLM2Protocol").get_to(c.checkTLM2Protocol); + + if (j_simconfig.contains("DatabaseRecording")) + j_simconfig.at("DatabaseRecording").get_to(c.databaseRecording); + + if (j_simconfig.contains("Debug")) + j_simconfig.at("Debug").get_to(c.debug); + + if (j_simconfig.contains("ECCControllerMode")) + j_simconfig.at("ECCControllerMode").get_to(c.eccControllerMode); + + if (j_simconfig.contains("EnableWindowing")) + j_simconfig.at("EnableWindowing").get_to(c.enableWindowing); + + if (j_simconfig.contains("ErrorCSVFile")) + j_simconfig.at("ErrorCSVFile").get_to(c.errorCsvFile); + + if (j_simconfig.contains("ErrorChipSeed")) + j_simconfig.at("ErrorChipSeed").get_to(c.errorChipSeed); + + if (j_simconfig.contains("PowerAnalysis")) + j_simconfig.at("PowerAnalysis").get_to(c.powerAnalysis); + + if (j_simconfig.contains("SimulationName")) + j_simconfig.at("SimulationName").get_to(c.simulationName); + + if (j_simconfig.contains("SimulationProgressBar")) + j_simconfig.at("SimulationProgressBar").get_to(c.simulationProgressBar); + + if (j_simconfig.contains("StoreMode")) + j_simconfig.at("StoreMode").get_to(c.storeMode); + + if (j_simconfig.contains("ThermalSimulation")) + j_simconfig.at("ThermalSimulation").get_to(c.thermalSimulation); + + if (j_simconfig.contains("UseMalloc")) + j_simconfig.at("UseMalloc").get_to(c.useMalloc); + + if (j_simconfig.contains("WindowSize")) + j_simconfig.at("WindowSize").get_to(c.windowSize); + + invalidateEnum(c.eccControllerMode); + invalidateEnum(c.storeMode); } -} // namespace Configuration +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/SimConfig.h b/DRAMSys/library/src/common/configuration/SimConfig.h index b28d131d..d0ca2fa5 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.h +++ b/DRAMSys/library/src/common/configuration/SimConfig.h @@ -33,8 +33,10 @@ * Derek Christ */ -#ifndef SIMCONFIG_H -#define SIMCONFIG_H +#ifndef DRAMSYSCONFIGURATION_SIMCONFIG_H +#define DRAMSYSCONFIGURATION_SIMCONFIG_H + +#include "util.h" #include @@ -64,26 +66,27 @@ enum class StoreMode }; NLOHMANN_JSON_SERIALIZE_ENUM(StoreMode, {{StoreMode::Invalid, nullptr}, + {StoreMode::NoStorage, "NoStorage"}, {StoreMode::Store, "Store"}, {StoreMode::ErrorModel, "ErrorModel"}}) struct SimConfig { - unsigned int addressOffset; - bool checkTLM2Protocol; - bool databaseRecording; - bool debug; - ECCControllerMode eccControllerMode; - bool enableWindowing; - std::string errorCsvFile; - unsigned int errorChipSeed; - bool powerAnalysis; - std::string simulationName; - bool simulationProgressBar; - StoreMode storeMode; - bool thermalSimulation; - bool useMalloc; - unsigned int windowSize; + Optional addressOffset; + Optional checkTLM2Protocol; + Optional databaseRecording; + Optional debug; + Optional eccControllerMode; + Optional enableWindowing; + Optional errorCsvFile; + Optional errorChipSeed; + Optional powerAnalysis; + Optional simulationName; + Optional simulationProgressBar; + Optional storeMode; + Optional thermalSimulation; + Optional useMalloc; + Optional windowSize; }; void to_json(json &j, const SimConfig &c); diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp index 6c69daec..5ed4fa8f 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp @@ -100,4 +100,4 @@ void from_json(const json &j, PowerInfo &c) j_powerinfo.at("dram_die_channel3").get_to(c.channel3); } -} // namespace Configuration +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.h b/DRAMSys/library/src/common/configuration/ThermalConfig.h index 02c905b6..b7ed3238 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.h +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.h @@ -33,8 +33,8 @@ * Derek Christ */ -#ifndef THERMALCONFIG_H -#define THERMALCONFIG_H +#ifndef DRAMSYSCONFIGURATION_THERMALCONFIG_H +#define DRAMSYSCONFIGURATION_THERMALCONFIG_H #include diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 39b76790..2b9f4615 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -34,7 +34,6 @@ */ #include "TraceSetup.h" -#include "util.h" namespace DRAMSysConfiguration { @@ -61,12 +60,11 @@ void to_json(json &j, const TraceSetup &c) inititator_j["numRequests"] = generator->numRequests; inititator_j["rwRatio"] = generator->rwRatio; inititator_j["addressDistribution"] = generator->addressDistribution; - - from_optional("seed", inititator_j, generator->seed); - from_optional("maxPendingReadRequests", inititator_j, generator->maxPendingReadRequests); - from_optional("maxPendingWriteRequests", inititator_j, generator->maxPendingWriteRequests); - from_optional("minAddress", inititator_j, generator->minAddress); - from_optional("maxAddress", inititator_j, generator->maxAddress); + inititator_j["seed"] = generator->seed; + inititator_j["maxPendingReadRequests"] = generator->maxPendingReadRequests; + inititator_j["maxPendingWriteRequests"] = generator->maxPendingWriteRequests; + inititator_j["minAddress"] = generator->minAddress; + inititator_j["maxAddress"] = generator->maxAddress; } else if (const auto hammer = dynamic_cast(initiator.get())) { @@ -79,6 +77,7 @@ void to_json(json &j, const TraceSetup &c) inititator_j["type"] = "player"; } + remove_null_values(inititator_j); j.insert(j.end(), inititator_j); } } @@ -103,11 +102,20 @@ void from_json(const json &j, TraceSetup &c) initiator_j.at("rwRatio").get_to(generator->rwRatio); initiator_j.at("addressDistribution").get_to(generator->addressDistribution); - get_optional("seed", initiator_j, generator->seed); - get_optional("maxPendingReadRequests", initiator_j, generator->maxPendingReadRequests); - get_optional("maxPendingWriteRequests", initiator_j, generator->maxPendingWriteRequests); - get_optional("minAddress", initiator_j, generator->minAddress); - get_optional("maxAddress", initiator_j, generator->maxAddress); + if (initiator_j.contains("seed")) + initiator_j.at("seed").get_to(generator->seed); + + if (initiator_j.contains("maxPendingReadRequests")) + initiator_j.at("maxPendingReadRequests").get_to(generator->maxPendingReadRequests); + + if (initiator_j.contains("maxPendingWriteRequests")) + initiator_j.at("maxPendingWriteRequests").get_to(generator->maxPendingWriteRequests); + + if (initiator_j.contains("minAddress")) + initiator_j.at("minAddress").get_to(generator->minAddress); + + if (initiator_j.contains("maxAddress")) + initiator_j.at("maxAddress").get_to(generator->maxAddress); initiator = std::unique_ptr(generator); } @@ -128,4 +136,4 @@ void from_json(const json &j, TraceSetup &c) } } -} // namespace Configuration +} // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 61361bc2..6ac8156b 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -33,8 +33,10 @@ * Derek Christ */ -#ifndef TRACESETUP_H -#define TRACESETUP_H +#ifndef DRAMSYSCONFIGURATION_TRACESETUP_H +#define DRAMSYSCONFIGURATION_TRACESETUP_H + +#include "util.h" #include #include @@ -85,12 +87,12 @@ struct TraceGenerator : public TrafficInitiator unsigned int numRequests; double rwRatio; AddressDistribution addressDistribution; - std::pair addressIncrement; - std::pair seed; - std::pair maxPendingReadRequests; - std::pair maxPendingWriteRequests; - std::pair minAddress; - std::pair maxAddress; + Optional addressIncrement; + Optional seed; + Optional maxPendingReadRequests; + Optional maxPendingWriteRequests; + Optional minAddress; + Optional maxAddress; }; struct TraceHammer : public TrafficInitiator @@ -101,7 +103,7 @@ struct TraceHammer : public TrafficInitiator struct TraceSetup { - std::unordered_set> initiators; + std::unordered_set> initiators; }; void to_json(json &j, const TraceSetup &c); diff --git a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h index 80a18ecc..6179e986 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h @@ -33,8 +33,8 @@ * Derek Christ */ -#ifndef MEMARCHITECTURESPEC_H -#define MEMARCHITECTURESPEC_H +#ifndef DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H +#define DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H #include #include diff --git a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h index 8d125a44..07c2da40 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h @@ -33,8 +33,8 @@ * Derek Christ */ -#ifndef MEMPOWERSPEC_H -#define MEMPOWERSPEC_H +#ifndef DRAMSYSCONFIGURATION_MEMPOWERSPEC_H +#define DRAMSYSCONFIGURATION_MEMPOWERSPEC_H #include #include diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp index 29def6d8..e4407cfb 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp @@ -34,7 +34,6 @@ */ #include "MemSpec.h" -#include "util.h" namespace DRAMSysConfiguration { @@ -44,9 +43,10 @@ void to_json(json &j, const MemSpec &c) j = json{{"memarchitecturespec", c.memArchitectureSpec}, {"memoryId", c.memoryId}, {"memoryType", c.memoryType}, - {"memtimingspec", c.memTimingSpec}}; + {"memtimingspec", c.memTimingSpec}, + {"mempowerspec", c.memPowerSpec}}; - from_optional("mempowerspec", j, c.memPowerSpec); + remove_null_values(j); } void from_json(const json &j, MemSpec &c) @@ -58,7 +58,8 @@ void from_json(const json &j, MemSpec &c) j_memspecs.at("memoryType").get_to(c.memoryType); j_memspecs.at("memtimingspec").get_to(c.memTimingSpec); - get_optional("mempowerspec", j, c.memPowerSpec); + if (j_memspecs.contains("mempowerspec")) + j_memspecs.at("mempowerspec").get_to(c.memPowerSpec); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h index 248709b4..30568d0d 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h @@ -33,12 +33,13 @@ * Derek Christ */ -#ifndef MEMSPEC_H -#define MEMSPEC_H +#ifndef DRAMSYSCONFIGURATION_MEMSPEC_H +#define DRAMSYSCONFIGURATION_MEMSPEC_H #include "MemArchitectureSpec.h" #include "MemPowerSpec.h" #include "MemTimingSpec.h" +#include "util.h" #include @@ -54,7 +55,7 @@ struct MemSpec std::string memoryId; std::string memoryType; MemTimingSpec memTimingSpec; - std::pair memPowerSpec; + Optional memPowerSpec; }; void to_json(json &j, const MemSpec &c); diff --git a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h index 61ba7308..d06898be 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h @@ -33,8 +33,8 @@ * Derek Christ */ -#ifndef MEMTIMINGSPEC_H -#define MEMTIMINGSPEC_H +#ifndef DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H +#define DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H #include #include diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 1be7c5e5..9a4ce6a3 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -6,13 +6,13 @@ using json = nlohmann::json; DRAMSysConfiguration::AddressMapping getAddressMapping() { - return DRAMSysConfiguration::AddressMapping{{{0, 1}, true}, + return DRAMSysConfiguration::AddressMapping{{{0, 1}}, {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, {16}, - {{13, 14, 15}, true}, + {{13, 14, 15}}, {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}, - {{33}, true}, - {{}, false}}; + {{33}}, + {{}}}; } DRAMSysConfiguration::McConfig getMcConfig() @@ -29,14 +29,14 @@ DRAMSysConfiguration::McConfig getMcConfig() DRAMSysConfiguration::PowerDownPolicy::NoPowerDown, DRAMSysConfiguration::Arbiter::Simple, 128, - std::pair{false, true}}; + {}}; } DRAMSysConfiguration::SimConfig getSimConfig() { return DRAMSysConfiguration::SimConfig{ - 0, false, true, false, DRAMSysConfiguration::ECCControllerMode::Disabled, false, "error.csv", - 42, false, "ddr5", true, DRAMSysConfiguration::StoreMode::NoStorage, false, false, + 0, false, true, false, DRAMSysConfiguration::ECCControllerMode::Disabled, false, {"error.csv"}, + 42, false, {"ddr5"}, true, DRAMSysConfiguration::StoreMode::NoStorage, false, false, 1000}; } @@ -74,10 +74,10 @@ std::unique_ptr getTraceGeneratorRandom() gen->name = "MyTestGen"; gen->addressDistribution = DRAMSysConfiguration::AddressDistribution::Random; - gen->maxAddress = {1000, true}; - gen->maxPendingReadRequests = {8, true}; + gen->maxAddress = 1000; + gen->maxPendingReadRequests = 8; gen->rwRatio = 0.5; - gen->seed = {1337, true}; + gen->seed = 1337; gen->numRequests = 1000; return std::unique_ptr(gen); @@ -91,9 +91,9 @@ std::unique_ptr getTraceGeneratorSequentia gen->name = "MyTestGen"; gen->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; - gen->addressIncrement = {64, true}; - gen->maxAddress = {1000, true}; - gen->maxPendingReadRequests = {8, true}; + gen->addressIncrement = 64; + gen->maxAddress = 1000; + gen->maxPendingReadRequests = 8; gen->rwRatio = 0.5; gen->numRequests = 1000; @@ -115,13 +115,13 @@ std::unique_ptr getTraceHammer() DRAMSysConfiguration::TraceSetup getTraceSetup() { - std::unordered_set> initiators; + std::unordered_set> initiators; initiators.emplace(getTracePlayer()); initiators.emplace(getTraceGeneratorRandom()); initiators.emplace(getTraceGeneratorSequential()); initiators.emplace(getTraceHammer()); - return DRAMSysConfiguration::TraceSetup{std::move(initiators)}; + return DRAMSysConfiguration::TraceSetup{initiators}; } DRAMSysConfiguration::Configuration getConfig(const DRAMSysConfiguration::MemSpec &memSpec) @@ -132,9 +132,9 @@ DRAMSysConfiguration::Configuration getConfig(const DRAMSysConfiguration::MemSpe memSpec, getSimConfig(), "std::string_simulationId", - {getThermalConfig(), true}, + getThermalConfig(), // {{}, false}, works too - {getTraceSetup(), true}, + getTraceSetup(), }; } diff --git a/DRAMSys/library/src/common/configuration/util.h b/DRAMSys/library/src/common/configuration/util.h index 113c3265..c6090fa3 100644 --- a/DRAMSys/library/src/common/configuration/util.h +++ b/DRAMSys/library/src/common/configuration/util.h @@ -33,8 +33,8 @@ * Derek Christ */ -#ifndef UTIL_H -#define UTIL_H +#ifndef DRAMSYSCONFIGURATION_UTIL_H +#define DRAMSYSCONFIGURATION_UTIL_H #include #include @@ -43,35 +43,91 @@ namespace DRAMSysConfiguration { using json = nlohmann::json; -/** - * Inspired from https://github.com/nlohmann/json/issues/1749#issuecomment-770748811 - */ template -void get_optional(const std::string &name, const json &j, std::pair &val) +class Optional : public std::pair { - auto it = j.find(name); - if (it != j.end()) +public: + Optional() : std::pair{{}, false} { - val.first = it->template get(); - val.second = true; } - else + Optional(const T &v) : std::pair{v, true} { - val.second = false; } -} + + bool isValid() const + { + return this->second; + } + + const T &getValue() const + { + assert(this->second == true); + return this->first; + } + + void setValue(const T &v) + { + this->first = v; + this->second = true; + } + + void invalidate() + { + this->second = false; + } +}; template -void from_optional(const std::string &name, json &j, const std::pair &val) +void invalidateEnum(T &value) { - if (val.second) - { - j[name] = val.first; - } + if (value.isValid() && value.getValue() == T::first_type::Invalid) + value.invalidate(); } json get_config_json(const json &j, const std::string &configPath, const std::string &objectName); +inline void remove_null_values(json &j) +{ + std::vector keysToRemove; + + for (const auto &element : j.items()) + { + if (element.value() == nullptr) + keysToRemove.emplace_back(element.key()); + } + + std::for_each(keysToRemove.begin(), keysToRemove.end(), [&](const std::string &key) { j.erase(key); }); +} + } // namespace DRAMSysConfiguration +/** + * Inspired from + * https://json.nlohmann.me/features/arbitrary_types/#how-can-i-use-get-for-non-default-constructiblenon-copyable-types + */ +namespace nlohmann +{ + +template +void to_json(nlohmann::json &j, const DRAMSysConfiguration::Optional &v) +{ + if (v.isValid()) + j = v.getValue(); + else + j = nullptr; +} + +template +void from_json(const nlohmann::json &j, DRAMSysConfiguration::Optional &v) +{ + if (j.is_null()) + v = {}; + else + { + v = {j.get()}; + } +} + +} // namespace nlohmann + #endif From ce7121b428cfd4d4c4a6e8c1fded465c606b887f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 2 Nov 2021 16:52:36 +0100 Subject: [PATCH 04/23] Port to the new Json configuration library The DRAMSysLibrary and the Simulator were now ported to support the new configuration library. --- DRAMSys/library/CMakeLists.txt | 2 +- DRAMSys/library/src/common/TlmRecorder.cpp | 10 +- .../common/configuration/AddressMapping.cpp | 4 + .../src/common/configuration/AddressMapping.h | 1 + .../src/common/configuration/CMakeLists.txt | 2 +- .../common/configuration/Configuration.cpp | 19 +- .../src/common/configuration/Configuration.h | 4 +- .../src/common/configuration/McConfig.cpp | 5 + .../src/common/configuration/McConfig.h | 4 + .../common/configuration/ThermalConfig.cpp | 21 +- .../src/common/configuration/ThermalConfig.h | 6 +- .../src/common/configuration/TraceSetup.cpp | 16 +- .../src/common/configuration/TraceSetup.h | 20 +- .../configuration/memspec/MemPowerSpec.h | 2 +- .../common/configuration/memspec/MemSpec.cpp | 5 + .../common/configuration/memspec/MemSpec.h | 2 + .../common/configuration/tests/simpletest.cpp | 5 +- .../library/src/common/configuration/util.cpp | 5 +- DRAMSys/library/src/common/utils.cpp | 84 --- DRAMSys/library/src/common/utils.h | 7 - .../src/configuration/Configuration.cpp | 691 +++++++++++------- .../library/src/configuration/Configuration.h | 22 +- .../src/configuration/TemperatureSimConfig.h | 48 +- .../src/configuration/memspec/MemSpec.cpp | 18 +- .../src/configuration/memspec/MemSpec.h | 6 +- .../src/configuration/memspec/MemSpecDDR3.cpp | 100 +-- .../src/configuration/memspec/MemSpecDDR3.h | 7 +- .../src/configuration/memspec/MemSpecDDR4.cpp | 138 ++-- .../src/configuration/memspec/MemSpecDDR4.h | 3 +- .../src/configuration/memspec/MemSpecDDR5.cpp | 143 ++-- .../src/configuration/memspec/MemSpecDDR5.h | 3 +- .../configuration/memspec/MemSpecGDDR5.cpp | 95 ++- .../src/configuration/memspec/MemSpecGDDR5.h | 3 +- .../configuration/memspec/MemSpecGDDR5X.cpp | 95 ++- .../src/configuration/memspec/MemSpecGDDR5X.h | 3 +- .../configuration/memspec/MemSpecGDDR6.cpp | 101 ++- .../src/configuration/memspec/MemSpecGDDR6.h | 3 +- .../src/configuration/memspec/MemSpecHBM2.cpp | 81 +- .../src/configuration/memspec/MemSpecHBM2.h | 3 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 83 ++- .../src/configuration/memspec/MemSpecLPDDR4.h | 3 +- .../configuration/memspec/MemSpecLPDDR5.cpp | 91 ++- .../src/configuration/memspec/MemSpecLPDDR5.h | 2 +- .../configuration/memspec/MemSpecSTTMRAM.cpp | 67 +- .../configuration/memspec/MemSpecSTTMRAM.h | 3 +- .../configuration/memspec/MemSpecWideIO.cpp | 114 +-- .../src/configuration/memspec/MemSpecWideIO.h | 3 +- .../configuration/memspec/MemSpecWideIO2.cpp | 75 +- .../configuration/memspec/MemSpecWideIO2.h | 3 +- .../library/src/simulation/AddressDecoder.cpp | 102 +-- .../library/src/simulation/AddressDecoder.h | 8 +- DRAMSys/library/src/simulation/Arbiter.cpp | 18 +- DRAMSys/library/src/simulation/Arbiter.h | 8 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 49 +- DRAMSys/library/src/simulation/DRAMSys.h | 20 +- .../src/simulation/DRAMSysRecordable.cpp | 32 +- .../src/simulation/DRAMSysRecordable.h | 10 +- .../src/simulation/TemperatureController.cpp | 4 +- .../src/simulation/TemperatureController.h | 2 +- DRAMSys/simulator/TraceSetup.cpp | 270 +++---- DRAMSys/simulator/TraceSetup.h | 5 +- DRAMSys/simulator/main.cpp | 22 +- 62 files changed, 1354 insertions(+), 1427 deletions(-) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 391b6179..eb7334c8 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -322,5 +322,5 @@ endif() target_link_libraries(DRAMSysLibrary PUBLIC ${SYSTEMC_LIBRARY} PRIVATE DRAMPower - PRIVATE DRAMSysConfiguration + PUBLIC DRAMSysConfiguration ) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index c056de77..e64d7ebe 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -348,14 +348,8 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 6, static_cast(Configuration::getInstance().memSpec->tCK.value())); sqlite3_bind_text(insertGeneralInfoStatement, 7, "PS", 2, nullptr); - std::fstream mcconfig_stream, memspec_stream; - mcconfig_stream.open(mcconfig, std::ios::in); - memspec_stream.open(memspec, std::ios::in); - std::string mcconfig_dump((std::istreambuf_iterator(mcconfig_stream)), (std::istreambuf_iterator())); - std::string memspec_dump((std::istreambuf_iterator(memspec_stream)), (std::istreambuf_iterator())); - - sqlite3_bind_text(insertGeneralInfoStatement, 8, mcconfig_dump.c_str(), static_cast(mcconfig_dump.length()), nullptr); - sqlite3_bind_text(insertGeneralInfoStatement, 9, memspec_dump.c_str(), static_cast(memspec_dump.length()), nullptr); + sqlite3_bind_text(insertGeneralInfoStatement, 8, mcconfig.c_str(), static_cast(mcconfig.length()), nullptr); + sqlite3_bind_text(insertGeneralInfoStatement, 9, memspec.c_str(), static_cast(memspec.length()), nullptr); sqlite3_bind_text(insertGeneralInfoStatement, 10, traces.c_str(), static_cast(traces.length()), nullptr); if (Configuration::getInstance().enableWindowing) sqlite3_bind_int64(insertGeneralInfoStatement, 11, static_cast((Configuration::getInstance().memSpec->tCK diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp index 7b2237cc..1d865804 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.cpp +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -52,6 +52,7 @@ void to_json(json &j, const AddressMapping &m) {"CHANNEL_BIT", m.channelBits}, {"BYTE_BIT", m.byteBits}, {"BANKGROUP_BIT", m.bankGroupBits}, + {"RANK_BIT", m.rankBits}, {"XOR", m.xorBits}}; j["CONGEN"] = congen; @@ -71,6 +72,9 @@ void from_json(const json &j, AddressMapping &m) congen.at("BANK_BIT").get_to(m.bankBits); congen.at("ROW_BIT").get_to(m.rowBits); + if (congen.contains("RANK_BIT")) + congen.at("RANK_BIT").get_to(m.rankBits); + if (congen.contains("CHANNEL_BIT")) congen.at("CHANNEL_BIT").get_to(m.channelBits); diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index ffcc3ca2..a0ab60ff 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -64,6 +64,7 @@ struct AddressMapping Optional> bankGroupBits; std::unordered_set rowBits; Optional> channelBits; + Optional> rankBits; Optional> xorBits; }; diff --git a/DRAMSys/library/src/common/configuration/CMakeLists.txt b/DRAMSys/library/src/common/configuration/CMakeLists.txt index bd199eae..314d0f14 100644 --- a/DRAMSys/library/src/common/configuration/CMakeLists.txt +++ b/DRAMSys/library/src/common/configuration/CMakeLists.txt @@ -55,7 +55,7 @@ add_library(DRAMSysConfiguration STATIC util.cpp ) -target_compile_definitions(DRAMSysConfiguration PRIVATE DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources") +target_compile_definitions(DRAMSysConfiguration PUBLIC DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources") target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) diff --git a/DRAMSys/library/src/common/configuration/Configuration.cpp b/DRAMSys/library/src/common/configuration/Configuration.cpp index c610f579..f2dd99eb 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.cpp +++ b/DRAMSys/library/src/common/configuration/Configuration.cpp @@ -35,11 +35,14 @@ #include "Configuration.h" +#include #include namespace DRAMSysConfiguration { +std::string Configuration::resourceDirectory; + void to_json(json &j, const Configuration &c) { j = json{{"addressmapping", c.addressMapping}, {"mcconfig", c.mcConfig}, {"memspec", c.memSpec}, @@ -64,11 +67,21 @@ void from_json(const json &j, Configuration &c) j.at("tracesetup").get_to(c.traceSetup); } -Configuration from_path(const std::string &path) +Configuration from_path(const std::string &path, const std::string &resourceDirectory) { + Configuration::resourceDirectory = resourceDirectory; + std::ifstream file(path); - json simulation = json::parse(file).at("simulation"); - return simulation.get(); + + if (file.is_open()) + { + json simulation = json::parse(file).at("simulation"); + return simulation.get(); + } + else + { + throw std::runtime_error("Failed to open file " + path); + } } } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h index 676036ec..c5588c2a 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.h +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -71,12 +71,14 @@ struct Configuration std::string simulationId; Optional thermalConfig; Optional traceSetup; + + static std::string resourceDirectory; }; void to_json(json &j, const Configuration &p); void from_json(const json &j, Configuration &p); -Configuration from_path(const std::string &path); +Configuration from_path(const std::string &path, const std::string &resourceDirectory = DRAMSysResourceDirectory); } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp index 50684665..86648204 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.cpp +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -111,4 +111,9 @@ void from_json(const json &j, McConfig &c) invalidateEnum(c.arbiter); } +std::string dump(const McConfig &c) +{ + return json{c}.dump(); +} + } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index 649d81bb..701b5d09 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -117,6 +117,7 @@ enum class RefreshPolicy NoRefresh, AllBank, PerBank, + Per2Bank, SameBank, Invalid = -1 }; @@ -124,6 +125,7 @@ enum class RefreshPolicy NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicy, {{RefreshPolicy::Invalid, nullptr}, {RefreshPolicy::AllBank, "AllBank"}, {RefreshPolicy::PerBank, "PerBank"}, + {RefreshPolicy::Per2Bank, "Per2Bank"}, {RefreshPolicy::SameBank, "SameBank"}}) enum class PowerDownPolicy @@ -170,6 +172,8 @@ struct McConfig void to_json(json &j, const McConfig &c); void from_json(const json &j, McConfig &c); +std::string dump(const McConfig &c); + } // namespace Configuration #endif // MCCONFIG_H diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp index 5ed4fa8f..b6305269 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp @@ -84,20 +84,25 @@ void from_json(const json &j, DramDieChannel &c) void to_json(json &j, const PowerInfo &c) { - j = json{{"dram_die_channel0", c.channel0}, - {"dram_die_channel1", c.channel1}, - {"dram_die_channel2", c.channel2}, - {"dram_die_channel3", c.channel3}}; + j = json{}; + + for (const auto &channel : c.channels) + { + j.emplace(channel.identifier, channel); + } } void from_json(const json &j, PowerInfo &c) { json j_powerinfo = get_config_json(j, thermalConfigPath, "powerInfo"); - j_powerinfo.at("dram_die_channel0").get_to(c.channel0); - j_powerinfo.at("dram_die_channel1").get_to(c.channel1); - j_powerinfo.at("dram_die_channel2").get_to(c.channel2); - j_powerinfo.at("dram_die_channel3").get_to(c.channel3); + for (const auto &entry : j_powerinfo.items()) + { + DramDieChannel channel; + j_powerinfo.at(entry.key()).get_to(channel); + + c.channels.push_back(channel); + } } } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.h b/DRAMSys/library/src/common/configuration/ThermalConfig.h index b7ed3238..1bb063ce 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.h +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.h @@ -78,6 +78,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(ThermalSimUnit, {{ThermalSimUnit::Invalid, nullptr} struct DramDieChannel { + std::string identifier; double init_pow; double threshold; }; @@ -87,10 +88,7 @@ void from_json(const json &j, DramDieChannel &c); struct PowerInfo { - DramDieChannel channel0; - DramDieChannel channel1; - DramDieChannel channel2; - DramDieChannel channel3; + std::vector channels; }; void to_json(json &j, const PowerInfo &c); diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 2b9f4615..ce9a98fc 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -53,6 +53,8 @@ void to_json(json &j, const TraceSetup &c) inititator_j["name"] = initiator->name; inititator_j["clkMhz"] = initiator->clkMhz; + inititator_j["maxPendingReadRequests"] = initiator->maxPendingReadRequests; + inititator_j["maxPendingWriteRequests"] = initiator->maxPendingWriteRequests; if (const auto generator = dynamic_cast(initiator.get())) { @@ -61,8 +63,6 @@ void to_json(json &j, const TraceSetup &c) inititator_j["rwRatio"] = generator->rwRatio; inititator_j["addressDistribution"] = generator->addressDistribution; inititator_j["seed"] = generator->seed; - inititator_j["maxPendingReadRequests"] = generator->maxPendingReadRequests; - inititator_j["maxPendingWriteRequests"] = generator->maxPendingWriteRequests; inititator_j["minAddress"] = generator->minAddress; inititator_j["maxAddress"] = generator->maxAddress; } @@ -105,12 +105,6 @@ void from_json(const json &j, TraceSetup &c) if (initiator_j.contains("seed")) initiator_j.at("seed").get_to(generator->seed); - if (initiator_j.contains("maxPendingReadRequests")) - initiator_j.at("maxPendingReadRequests").get_to(generator->maxPendingReadRequests); - - if (initiator_j.contains("maxPendingWriteRequests")) - initiator_j.at("maxPendingWriteRequests").get_to(generator->maxPendingWriteRequests); - if (initiator_j.contains("minAddress")) initiator_j.at("minAddress").get_to(generator->minAddress); @@ -132,6 +126,12 @@ void from_json(const json &j, TraceSetup &c) initiator_j.at("name").get_to(initiator->name); initiator_j.at("clkMhz").get_to(initiator->clkMhz); + if (initiator_j.contains("maxPendingReadRequests")) + initiator_j.at("maxPendingReadRequests").get_to(initiator->maxPendingReadRequests); + + if (initiator_j.contains("maxPendingWriteRequests")) + initiator_j.at("maxPendingWriteRequests").get_to(initiator->maxPendingWriteRequests); + c.initiators.emplace(std::move(initiator)); } } diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 6ac8156b..f8062b2e 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -74,8 +74,10 @@ struct TrafficInitiator { virtual ~TrafficInitiator() = 0; - unsigned int clkMhz; + uint64_t clkMhz; std::string name; + Optional maxPendingReadRequests; + Optional maxPendingWriteRequests; }; struct TracePlayer : public TrafficInitiator @@ -84,21 +86,19 @@ struct TracePlayer : public TrafficInitiator struct TraceGenerator : public TrafficInitiator { - unsigned int numRequests; + uint64_t numRequests; double rwRatio; AddressDistribution addressDistribution; - Optional addressIncrement; - Optional seed; - Optional maxPendingReadRequests; - Optional maxPendingWriteRequests; - Optional minAddress; - Optional maxAddress; + Optional addressIncrement; + Optional seed; + Optional minAddress; + Optional maxAddress; }; struct TraceHammer : public TrafficInitiator { - unsigned int numRequests; - unsigned int rowIncrement; + uint64_t numRequests; + uint64_t rowIncrement; }; struct TraceSetup diff --git a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h index 07c2da40..513dd750 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h @@ -45,7 +45,7 @@ using json = nlohmann::json; struct MemPowerSpec { - std::unordered_map entries; + std::unordered_map entries; }; void to_json(json &j, const MemPowerSpec &c); diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp index e4407cfb..9e433c89 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp @@ -62,4 +62,9 @@ void from_json(const json &j, MemSpec &c) j_memspecs.at("mempowerspec").get_to(c.memPowerSpec); } +std::string dump(const MemSpec &c) +{ + return json{c}.dump(); +} + } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h index 30568d0d..0fde0fa8 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h @@ -61,6 +61,8 @@ struct MemSpec void to_json(json &j, const MemSpec &c); void from_json(const json &j, MemSpec &c); +std::string dump(const MemSpec &c); + } // namespace Configuration #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 9a4ce6a3..07d259c5 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -12,6 +12,7 @@ DRAMSysConfiguration::AddressMapping getAddressMapping() {{13, 14, 15}}, {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}, {{33}}, + {{}}, {{}}}; } @@ -42,12 +43,14 @@ DRAMSysConfiguration::SimConfig getSimConfig() DRAMSysConfiguration::ThermalConfig getThermalConfig() { + std::vector channels {{"dram_die_channel0", 0.0, 1.0}, {"dram_die_channel1", 0.0, 1.0}, {"dram_die_channel2", 0.0, 1.0}, {"dram_die_channel3", 0.0, 1.0}}; + return DRAMSysConfiguration::ThermalConfig{ DRAMSysConfiguration::TemperatureScale::Celsius, 89, 100, DRAMSysConfiguration::ThermalSimUnit::Microseconds, - DRAMSysConfiguration::PowerInfo{{0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}}, + DRAMSysConfiguration::PowerInfo{channels}, "127.0.0.1", 118800, 10, diff --git a/DRAMSys/library/src/common/configuration/util.cpp b/DRAMSys/library/src/common/configuration/util.cpp index d4d3ef29..26ce32e1 100644 --- a/DRAMSys/library/src/common/configuration/util.cpp +++ b/DRAMSys/library/src/common/configuration/util.cpp @@ -34,9 +34,10 @@ */ #include "util.h" +#include "Configuration.h" #include - +#include namespace DRAMSysConfiguration { @@ -51,7 +52,7 @@ json get_config_json(const json &j, const std::string &configPath, const std::st std::string jsonFileName; j.get_to(jsonFileName); - std::ifstream file(std::string(DRAMSysResourceDirectory) + "/" + configPath + "/" + jsonFileName); + std::ifstream file(std::string(Configuration::resourceDirectory) + "/" + configPath + "/" + jsonFileName); json j_object = json::parse(file); return j_object.at(objectName); } diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 8427a84a..239c11d2 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -43,7 +43,6 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; bool TimeInterval::timeIsInInterval(const sc_time &time) const { @@ -71,89 +70,6 @@ std::string getPhaseName(const tlm_phase &phase) return oss.str(); } -json parseJSON(const std::string &path) -{ - std::ifstream file(path); - if (file.is_open()) - { - json j = json::parse(file, nullptr, false); - if (!j.is_discarded()) - return j; - else - throw std::invalid_argument("JSON parse error in file '" + path + "'."); - } - else - throw std::invalid_argument("Failed to open file '" + path + "'."); -} - -bool parseBool(json &spec, const std::string &name) -{ - json param = spec[name]; - if (!param.empty()) - { - if (param.is_boolean()) - return param; - else - throw std::invalid_argument("Expected type for parameter '" + name + "': bool"); - } - else - { - SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is false.").c_str()); - return false; - } -} - -unsigned int parseUint(json &spec, const std::string &name) -{ - json param = spec[name]; - if (!param.empty()) - { - if (param.is_number_unsigned()) - return param; - else - throw std::invalid_argument("Expected type for parameter '" + name + "': unsigned int"); - } - else - { - SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is 1.").c_str()); - return 1; - } -} - -double parseUdouble(json &spec, const std::string &name) -{ - json param = spec[name]; - if (!param.empty()) - { - if (param.is_number() && (param > 0)) - return param; - else - throw std::invalid_argument("Expected type for parameter '" + name + "': positive double"); - } - else - { - SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is 1.").c_str()); - return 1; - } -} - -std::string parseString(json &spec, const std::string &name) -{ - json param = spec[name]; - if (!param.empty()) - { - if (param.is_string()) - return param; - else - throw std::invalid_argument("Expected type for parameter '" + name + "': string"); - } - else - { - SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist.").c_str()); - return {}; - } -} - void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank) { payload.set_address(0); diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index 184b6efe..8cc7e25f 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -44,7 +44,6 @@ #include #include #include "dramExtensions.h" -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class TimeInterval { @@ -63,12 +62,6 @@ constexpr const char headline[] = std::string getPhaseName(const tlm::tlm_phase &phase); -nlohmann::json parseJSON(const std::string &path); -bool parseBool(nlohmann::json &spec, const std::string &name); -unsigned int parseUint(nlohmann::json &spec, const std::string &name); -double parseUdouble(nlohmann::json &spec, const std::string &name); -std::string parseString(nlohmann::json &spec, const std::string &name); - void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0)); diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index d9de822b..ac9614d3 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -55,10 +55,6 @@ #include "memspec/MemSpecSTTMRAM.h" using namespace sc_core; -using json = nlohmann::json; - -std::string Configuration::memspecUri; -std::string Configuration::mcconfigUri; enum sc_time_unit string2TimeUnit(const std::string &s) { @@ -81,218 +77,211 @@ enum sc_time_unit string2TimeUnit(const std::string &s) } } -void Configuration::setParameter(const std::string &name, const nlohmann::json &value) -{ - // MCConfig - if (name == "PagePolicy") - { - if (value == "Open") - pagePolicy = PagePolicy::Open; - else if (value == "Closed") - pagePolicy = PagePolicy::Closed; - else if (value == "OpenAdaptive") - pagePolicy = PagePolicy::OpenAdaptive; - else if (value == "ClosedAdaptive") - pagePolicy = PagePolicy::ClosedAdaptive; - else - SC_REPORT_FATAL("Configuration", "Unsupported page policy!"); - } - else if (name == "Scheduler") - { - if (value == "Fifo") - scheduler = Scheduler::Fifo; - else if (value == "FrFcfs") - scheduler = Scheduler::FrFcfs; - else if (value == "FrFcfsGrp") - scheduler = Scheduler::FrFcfsGrp; - else - SC_REPORT_FATAL("Configuration", "Unsupported scheduler!"); - } - else if (name == "SchedulerBuffer") - { - if (value == "Bankwise") - schedulerBuffer = SchedulerBuffer::Bankwise; - else if (value == "ReadWrite") - schedulerBuffer = SchedulerBuffer::ReadWrite; - else if (value == "Shared") - schedulerBuffer = SchedulerBuffer::Shared; - else - SC_REPORT_FATAL("Configuration", "Unsupported scheduler buffer!"); - } - else if (name == "RequestBufferSize") - { - requestBufferSize = value; - if (requestBufferSize == 0) - SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); - } - else if (name == "CmdMux") - { - if (value == "Oldest") - cmdMux = CmdMux::Oldest; - else if (value == "Strict") - cmdMux = CmdMux::Strict; - else - SC_REPORT_FATAL("Configuration", "Unsupported cmd mux!"); - } - else if (name == "RespQueue") - { - if (value == "Fifo") - respQueue = RespQueue::Fifo; - else if (value == "Reorder") - respQueue = RespQueue::Reorder; - else - SC_REPORT_FATAL("Configuration", "Unsupported response queue!"); - } - else if (name == "Arbiter") - { - if (value == "Simple") - arbiter = Arbiter::Simple; - else if (value == "Fifo") - arbiter = Arbiter::Fifo; - else if (value == "Reorder") - arbiter = Arbiter::Reorder; - else - SC_REPORT_FATAL("Configuration", "Unsupported arbiter!"); - } - else if (name == "RefreshPolicy") - { - if (value == "NoRefresh") - refreshPolicy = RefreshPolicy::NoRefresh; - else if (value == "AllBank" || value == "Rankwise") - refreshPolicy = RefreshPolicy::AllBank; - else if (value == "PerBank" || value == "Bankwise") - refreshPolicy = RefreshPolicy::PerBank; - else if (value == "Per2Bank") - refreshPolicy = RefreshPolicy::Per2Bank; - else if (value == "SameBank" || value == "Groupwise") - refreshPolicy = RefreshPolicy::SameBank; - else - SC_REPORT_FATAL("Configuration", "Unsupported refresh policy!"); - } - else if (name == "RefreshMaxPostponed") - refreshMaxPostponed = value; - else if (name == "RefreshMaxPulledin") - refreshMaxPulledin = value; - else if (name == "PowerDownPolicy") - { - if (value == "NoPowerDown") - powerDownPolicy = PowerDownPolicy::NoPowerDown; - else if (value == "Staggered") - powerDownPolicy = PowerDownPolicy::Staggered; - else - SC_REPORT_FATAL("Configuration", "Unsupported power down policy!"); - } - else if (name == "RefreshManagement") - refreshManagement = value; - else if (name == "PowerDownTimeout") - powerDownTimeout = value; - else if (name == "MaxActiveTransactions") - maxActiveTransactions = value; - else if (name == "ArbitrationDelayFw") - arbitrationDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; - else if (name == "ArbitrationDelayBw") - arbitrationDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; - else if (name == "ThinkDelayFw") - thinkDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; - else if (name == "ThinkDelayBw") - thinkDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; - else if (name == "PhyDelayFw") - phyDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; - else if (name == "PhyDelayBw") - phyDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; - //SimConfig------------------------------------------------ - else if (name == "SimulationName") - simulationName = value; - else if (name == "DatabaseRecording") - databaseRecording = value; - else if (name == "PowerAnalysis") - powerAnalysis = value; - else if (name == "EnableWindowing") - enableWindowing = value; - else if (name == "WindowSize") - { - windowSize = value; - if (windowSize == 0) - SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); - } - else if (name == "Debug") - debug = value; - else if (name == "ThermalSimulation") - thermalSimulation = value; - else if (name == "SimulationProgressBar") - simulationProgressBar = value; - else if (name == "AddressOffset") - addressOffset = value; - else if (name == "UseMalloc") - useMalloc = value; - else if (name == "CheckTLM2Protocol") - checkTLM2Protocol = value; - else if (name == "ECCControllerMode") - { - if (value == "Disabled") - eccMode = ECCMode::Disabled; - else if (value == "Hamming") - eccMode = ECCMode::Hamming; - else - SC_REPORT_FATAL("Configuration", "Unsupported ECC mode!"); - } - // Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode - else if (name == "ErrorChipSeed") - errorChipSeed = value; - else if (name == "ErrorCSVFile") - errorCSVFile = value; - else if (name == "StoreMode") - { - if (value == "NoStorage") - storeMode = StoreMode::NoStorage; - else if (value == "Store") - storeMode = StoreMode::Store; - else if (value == "ErrorModel") - storeMode = StoreMode::ErrorModel; - else - SC_REPORT_FATAL("Configuration", "Unsupported store mode!"); - } - - // Temperature Simulation related - else if (name == "TemperatureScale") - { - if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") - SC_REPORT_FATAL("Configuration", - ("Invalid value for parameter " + name + ".").c_str()); - temperatureSim.temperatureScale = value; - } - else if (name == "StaticTemperatureDefaultValue") - temperatureSim.staticTemperatureDefaultValue = value; - else if (name == "ThermalSimPeriod") - temperatureSim.thermalSimPeriod = value; - else if (name == "ThermalSimUnit") - temperatureSim.thermalSimUnit = string2TimeUnit(value); - else if (name == "PowerInfoFile") - { - temperatureSim.powerInfoFile = value; - temperatureSim.parsePowerInfoFile(); - } - else if (name == "IceServerIp") - temperatureSim.iceServerIp = value; - else if (name == "IceServerPort") - temperatureSim.iceServerPort = value; - else if (name == "SimPeriodAdjustFactor") - temperatureSim.simPeriodAdjustFactor = value; - else if (name == "NPowStableCyclesToIncreasePeriod") - temperatureSim.nPowStableCyclesToIncreasePeriod = value; - else if (name == "GenerateTemperatureMap") - temperatureSim.generateTemperatureMap = value; - else if (name == "GeneratePowerMap") - temperatureSim.generatePowerMap = value; - else - SC_REPORT_FATAL("Configuration", - ("Parameter " + name + " not defined in Configuration").c_str()); -} - -void Configuration::setPathToResources(const std::string &path) -{ - temperatureSim.setPathToResources(path); -} +// void Configuration::setParameter(const std::string &name, const nlohmann::json &value) +// { +// MCConfig +// if (name == "PagePolicy") +// { +// if (value == "Open") +// pagePolicy = PagePolicy::Open; +// else if (value == "Closed") +// pagePolicy = PagePolicy::Closed; +// else if (value == "OpenAdaptive") +// pagePolicy = PagePolicy::OpenAdaptive; +// else if (value == "ClosedAdaptive") +// pagePolicy = PagePolicy::ClosedAdaptive; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported page policy!"); +// } +// else if (name == "Scheduler") +// { +// if (value == "Fifo") +// scheduler = Scheduler::Fifo; +// else if (value == "FrFcfs") +// scheduler = Scheduler::FrFcfs; +// else if (value == "FrFcfsGrp") +// scheduler = Scheduler::FrFcfsGrp; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported scheduler!"); +// } +// else if (name == "SchedulerBuffer") +// { +// if (value == "Bankwise") +// schedulerBuffer = SchedulerBuffer::Bankwise; +// else if (value == "ReadWrite") +// schedulerBuffer = SchedulerBuffer::ReadWrite; +// else if (value == "Shared") +// schedulerBuffer = SchedulerBuffer::Shared; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported scheduler buffer!"); +// } +// else if (name == "RequestBufferSize") +// { +// requestBufferSize = value; +// if (requestBufferSize == 0) +// SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); +// } +// else if (name == "CmdMux") +// { +// if (value == "Oldest") +// cmdMux = CmdMux::Oldest; +// else if (value == "Strict") +// cmdMux = CmdMux::Strict; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported cmd mux!"); +// } +// else if (name == "RespQueue") +// { +// if (value == "Fifo") +// respQueue = RespQueue::Fifo; +// else if (value == "Reorder") +// respQueue = RespQueue::Reorder; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported response queue!"); +// } +// else if (name == "Arbiter") +// { +// if (value == "Simple") +// arbiter = Arbiter::Simple; +// else if (value == "Fifo") +// arbiter = Arbiter::Fifo; +// else if (value == "Reorder") +// arbiter = Arbiter::Reorder; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported arbiter!"); +// } +// else if (name == "RefreshPolicy") +// { +// if (value == "NoRefresh") +// refreshPolicy = RefreshPolicy::NoRefresh; +// else if (value == "AllBank" || value == "Rankwise") +// refreshPolicy = RefreshPolicy::AllBank; +// else if (value == "PerBank" || value == "Bankwise") +// refreshPolicy = RefreshPolicy::PerBank; +// else if (value == "SameBank" || value == "Groupwise") +// refreshPolicy = RefreshPolicy::SameBank; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported refresh policy!"); +// } +// else if (name == "RefreshMaxPostponed") +// refreshMaxPostponed = value; +// else if (name == "RefreshMaxPulledin") +// refreshMaxPulledin = value; +// else if (name == "PowerDownPolicy") +// { +// if (value == "NoPowerDown") +// powerDownPolicy = PowerDownPolicy::NoPowerDown; +// else if (value == "Staggered") +// powerDownPolicy = PowerDownPolicy::Staggered; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported power down policy!"); +// } +// else if (name == "RefreshManagement") +// refreshManagement = value; +// else if (name == "PowerDownTimeout") +// powerDownTimeout = value; +// else if (name == "MaxActiveTransactions") +// maxActiveTransactions = value; +// else if (name == "ArbitrationDelayFw") +// arbitrationDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; +// else if (name == "ArbitrationDelayBw") +// arbitrationDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; +// else if (name == "ThinkDelayFw") +// thinkDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; +// else if (name == "ThinkDelayBw") +// thinkDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; +// else if (name == "PhyDelayFw") +// phyDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; +// else if (name == "PhyDelayBw") +// phyDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; +// SimConfig------------------------------------------------ +// else if (name == "SimulationName") +// simulationName = value; +// else if (name == "DatabaseRecording") +// databaseRecording = value; +// else if (name == "PowerAnalysis") +// powerAnalysis = value; +// else if (name == "EnableWindowing") +// enableWindowing = value; +// else if (name == "WindowSize") +// { +// windowSize = value; +// if (windowSize == 0) +// SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); +// } +// else if (name == "Debug") +// debug = value; +// else if (name == "ThermalSimulation") +// thermalSimulation = value; +// else if (name == "SimulationProgressBar") +// simulationProgressBar = value; +// else if (name == "AddressOffset") +// addressOffset = value; +// else if (name == "UseMalloc") +// useMalloc = value; +// else if (name == "CheckTLM2Protocol") +// checkTLM2Protocol = value; +// else if (name == "ECCControllerMode") +// { +// if (value == "Disabled") +// eccMode = ECCMode::Disabled; +// else if (value == "Hamming") +// eccMode = ECCMode::Hamming; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported ECC mode!"); +// } +// Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode +// else if (name == "ErrorChipSeed") +// errorChipSeed = value; +// else if (name == "ErrorCSVFile") +// errorCSVFile = value; +// else if (name == "StoreMode") +// { +// if (value == "NoStorage") +// storeMode = StoreMode::NoStorage; +// else if (value == "Store") +// storeMode = StoreMode::Store; +// else if (value == "ErrorModel") +// storeMode = StoreMode::ErrorModel; +// else +// SC_REPORT_FATAL("Configuration", "Unsupported store mode!"); +// } +// +// Temperature Simulation related +// else if (name == "TemperatureScale") +// { +// if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") +// SC_REPORT_FATAL("Configuration", +// ("Invalid value for parameter " + name + ".").c_str()); +// temperatureSim.temperatureScale = value; +// } +// else if (name == "StaticTemperatureDefaultValue") +// temperatureSim.staticTemperatureDefaultValue = value; +// else if (name == "ThermalSimPeriod") +// temperatureSim.thermalSimPeriod = value; +// else if (name == "ThermalSimUnit") +// temperatureSim.thermalSimUnit = string2TimeUnit(value); +// else if (name == "PowerInfoFile") +// { +// temperatureSim.powerInfoFile = value; +// temperatureSim.parsePowerInfoFile(); +// } +// else if (name == "IceServerIp") +// temperatureSim.iceServerIp = value; +// else if (name == "IceServerPort") +// temperatureSim.iceServerPort = value; +// else if (name == "SimPeriodAdjustFactor") +// temperatureSim.simPeriodAdjustFactor = value; +// else if (name == "NPowStableCyclesToIncreasePeriod") +// temperatureSim.nPowStableCyclesToIncreasePeriod = value; +// else if (name == "GenerateTemperatureMap") +// temperatureSim.generateTemperatureMap = value; +// else if (name == "GeneratePowerMap") +// temperatureSim.generatePowerMap = value; +// else +// SC_REPORT_FATAL("Configuration", +// ("Parameter " + name + " not defined in Configuration").c_str()); +// } // Changes the number of bytes depeding on the ECC Controller. This function is needed for modules which get data directly or indirectly from the ECC Controller unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const @@ -300,73 +289,267 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const // Manipulate the number of bytes only if there is an ECC Controller selected if (eccMode == ECCMode::Disabled) return nBytes; - else // if (eccMode == ECCMode::Hamming) + else // if (eccMode == DRAMSysConfiguration::ECCControllerMode::Hamming) { assert(pECC != nullptr); return pECC->AllocationSize(nBytes); } } -void Configuration::loadSimConfig(Configuration &config, const std::string &simconfigUri) +void Configuration::loadSimConfig(Configuration &config, const DRAMSysConfiguration::SimConfig &simConfig) { - json doc = parseJSON(simconfigUri); - if (doc["simconfig"].empty()) - SC_REPORT_FATAL("Configuration", "simconfig is empty."); - for (auto& x : doc["simconfig"].items()) - config.setParameter(x.key(), x.value()); + // TODO document all default values... + + if (simConfig.addressOffset.isValid()) + config.addressOffset = simConfig.addressOffset.getValue(); + + if (simConfig.addressOffset.isValid()) + config.checkTLM2Protocol = simConfig.checkTLM2Protocol.getValue(); + + if (simConfig.databaseRecording.isValid()) + config.databaseRecording = simConfig.databaseRecording.getValue(); + + if (simConfig.debug.isValid()) + config.debug = simConfig.debug.getValue(); + + if (simConfig.eccControllerMode.isValid()) + config.eccMode = [=] { + auto mode = simConfig.eccControllerMode.getValue(); + + if (mode == DRAMSysConfiguration::ECCControllerMode::Disabled) + return ECCMode::Disabled; + else + return ECCMode::Hamming; + }(); + + if (simConfig.enableWindowing.isValid()) + config.enableWindowing = simConfig.enableWindowing.getValue(); + + if (simConfig.powerAnalysis.isValid()) + config.powerAnalysis = simConfig.powerAnalysis.getValue(); + + if (simConfig.simulationName.isValid()) + config.simulationName = simConfig.simulationName.getValue(); + + if (simConfig.simulationProgressBar.isValid()) + config.simulationProgressBar = simConfig.simulationProgressBar.getValue(); + + if (simConfig.thermalSimulation.isValid()) + config.thermalSimulation = simConfig.thermalSimulation.getValue(); + + if (simConfig.useMalloc.isValid()) + config.useMalloc = simConfig.useMalloc.getValue(); + + if (simConfig.windowSize.isValid()) + config.windowSize = simConfig.windowSize.getValue(); + + + if (simConfig.errorCsvFile.isValid()) + config.errorCSVFile = simConfig.errorCsvFile.getValue(); + + if (simConfig.errorChipSeed.isValid()) + config.errorChipSeed = simConfig.errorChipSeed.getValue(); + + if (simConfig.storeMode.isValid()) + config.storeMode = [=] { + auto mode = simConfig.storeMode.getValue(); + + if (mode == DRAMSysConfiguration::StoreMode::NoStorage) + return StoreMode::NoStorage; + else if (mode == DRAMSysConfiguration::StoreMode::Store) + return StoreMode::Store; + else + return StoreMode::ErrorModel; + }(); } -void Configuration::loadTemperatureSimConfig(Configuration &config, const std::string &thermalsimconfigUri) +void Configuration::loadTemperatureSimConfig(Configuration &config, const DRAMSysConfiguration::ThermalConfig &thermalConfig) { - json doc = parseJSON(thermalsimconfigUri); - if (doc["thermalsimconfig"].empty()) - SC_REPORT_FATAL("Configuration", "thermalsimconfig is empty."); - for (auto& x : doc["thermalsimconfig"].items()) - config.setParameter(x.key(), x.value()); + config.temperatureSim.temperatureScale = [=] { + if (thermalConfig.temperatureScale == DRAMSysConfiguration::TemperatureScale::Celsius) + return TemperatureSimConfig::TemperatureScale::Celsius; + else if (thermalConfig.temperatureScale == DRAMSysConfiguration::TemperatureScale::Fahrenheit) + return TemperatureSimConfig::TemperatureScale::Fahrenheit; + else + return TemperatureSimConfig::TemperatureScale::Kelvin; + }(); + + config.temperatureSim.staticTemperatureDefaultValue = thermalConfig.staticTemperatureDefaultValue; + config.temperatureSim.thermalSimPeriod = thermalConfig.thermalSimPeriod; + + config.temperatureSim.thermalSimUnit = [=] { + if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Seconds) + return sc_core::SC_SEC; + else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Milliseconds) + return sc_core::SC_MS; + else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Microseconds) + return sc_core::SC_US; + else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Nanoseconds) + return sc_core::SC_NS; + else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Picoseconds) + return sc_core::SC_PS; + else + return sc_core::SC_FS; + }(); + + for (const auto &channel : thermalConfig.powerInfo.channels) + { + config.temperatureSim.powerInitialValues.push_back(channel.init_pow); + config.temperatureSim.powerThresholds.push_back(channel.threshold); + } + + config.temperatureSim.iceServerIp = thermalConfig.iceServerIp; + config.temperatureSim.iceServerPort = thermalConfig.iceServerPort; + config.temperatureSim.simPeriodAdjustFactor = thermalConfig.simPeriodAdjustFactor; + config.temperatureSim.nPowStableCyclesToIncreasePeriod = thermalConfig.nPowStableCyclesToIncreasePeriod; + config.temperatureSim.generateTemperatureMap = thermalConfig.generateTemperatureMap; + config.temperatureSim.generatePowerMap = thermalConfig.generatePowerMap; + + config.temperatureSim.showTemperatureSimConfig(); } -void Configuration::loadMCConfig(Configuration &config, const std::string &_mcconfigUri) +void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfiguration::McConfig &mcConfig) { - Configuration::mcconfigUri = _mcconfigUri; - json doc = parseJSON(_mcconfigUri); - if (doc["mcconfig"].empty()) - SC_REPORT_FATAL("Configuration", "mcconfig is empty."); - for (auto& x : doc["mcconfig"].items()) - config.setParameter(x.key(), x.value()); + if (mcConfig.pagePolicy.isValid()) + config.pagePolicy = [=] { + auto policy = mcConfig.pagePolicy.getValue(); + + if (policy == DRAMSysConfiguration::PagePolicy::Open) + return PagePolicy::Open; + else if (policy == DRAMSysConfiguration::PagePolicy::OpenAdaptive) + return PagePolicy::OpenAdaptive; + else if (policy == DRAMSysConfiguration::PagePolicy::Closed) + return PagePolicy::Closed; + else + return PagePolicy::ClosedAdaptive; + }(); + + if (mcConfig.scheduler.isValid()) + config.scheduler = [=] { + auto scheduler = mcConfig.scheduler.getValue(); + + if (scheduler == DRAMSysConfiguration::Scheduler::Fifo) + return Scheduler::Fifo; + else if (scheduler == DRAMSysConfiguration::Scheduler::FrFcfs) + return Scheduler::FrFcfs; + else + return Scheduler::FrFcfsGrp; + }(); + + if (mcConfig.schedulerBuffer.isValid()) + config.schedulerBuffer = [=] { + auto schedulerBuffer = mcConfig.schedulerBuffer.getValue(); + + if (schedulerBuffer == DRAMSysConfiguration::SchedulerBuffer::Bankwise) + return SchedulerBuffer::Bankwise; + else if (schedulerBuffer == DRAMSysConfiguration::SchedulerBuffer::ReadWrite) + return SchedulerBuffer::ReadWrite; + else + return SchedulerBuffer::Shared; + }(); + + if (mcConfig.requestBufferSize.isValid()) + config.requestBufferSize = mcConfig.requestBufferSize.getValue(); + + if (mcConfig.cmdMux.isValid()) + config.cmdMux = [=] { + auto cmdMux = mcConfig.cmdMux.getValue(); + + if (cmdMux == DRAMSysConfiguration::CmdMux::Oldest) + return CmdMux::Oldest; + else + return CmdMux::Strict; + }(); + + if (mcConfig.respQueue.isValid()) + config.respQueue = [=] { + auto respQueue = mcConfig.respQueue.getValue(); + + if (respQueue == DRAMSysConfiguration::RespQueue::Fifo) + return RespQueue::Fifo; + else + return RespQueue::Reorder; + }(); + + if (mcConfig.refreshPolicy.isValid()) + config.refreshPolicy = [=] { + auto policy = mcConfig.refreshPolicy.getValue(); + + if (policy == DRAMSysConfiguration::RefreshPolicy::NoRefresh) + return RefreshPolicy::NoRefresh; + else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank) + return RefreshPolicy::AllBank; + else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank) + return RefreshPolicy::PerBank; + else if (policy == DRAMSysConfiguration::RefreshPolicy::Per2Bank) + return RefreshPolicy::Per2Bank; + else + return RefreshPolicy::SameBank; + }(); + + if (mcConfig.refreshMaxPostponed.isValid()) + config.refreshMaxPostponed = mcConfig.refreshMaxPostponed.getValue(); + + if (mcConfig.refreshMaxPulledin.isValid()) + config.refreshMaxPulledin = mcConfig.refreshMaxPulledin.getValue(); + + if (mcConfig.powerDownPolicy.isValid()) + config.powerDownPolicy = [=] { + auto policy = mcConfig.powerDownPolicy.getValue(); + + if (policy == DRAMSysConfiguration::PowerDownPolicy::NoPowerDown) + return PowerDownPolicy::NoPowerDown; + else + return PowerDownPolicy::Staggered; + }(); + + if (mcConfig.arbiter.isValid()) + config.arbiter = [=] { + auto arbiter = mcConfig.arbiter.getValue(); + + if (arbiter == DRAMSysConfiguration::Arbiter::Simple) + return Arbiter::Simple; + else if (arbiter == DRAMSysConfiguration::Arbiter::Fifo) + return Arbiter::Fifo; + else + return Arbiter::Reorder; + }(); + + if (mcConfig.maxActiveTransactions.isValid()) + config.maxActiveTransactions = mcConfig.maxActiveTransactions.getValue(); + + if (mcConfig.refreshManagement.isValid()) + config.refreshManagement = mcConfig.refreshManagement.getValue(); } -void Configuration::loadMemSpec(Configuration &config, const std::string &_memspecUri) +void Configuration::loadMemSpec(Configuration &config, const DRAMSysConfiguration::MemSpec &memSpecConfig) { - Configuration::memspecUri = _memspecUri; - json doc = parseJSON(_memspecUri); - json jMemSpec = doc["memspec"]; - - std::string memoryType = jMemSpec["memoryType"]; + std::string memoryType = memSpecConfig.memoryType; if (memoryType == "DDR3") - memSpec = new MemSpecDDR3(jMemSpec); + config.memSpec = new MemSpecDDR3(memSpecConfig); else if (memoryType == "DDR4") - memSpec = new MemSpecDDR4(jMemSpec); + config.memSpec = new MemSpecDDR4(memSpecConfig); else if (memoryType == "DDR5") - memSpec = new MemSpecDDR5(jMemSpec); + config.memSpec = new MemSpecDDR5(memSpecConfig); else if (memoryType == "LPDDR4") - memSpec = new MemSpecLPDDR4(jMemSpec); + config.memSpec = new MemSpecLPDDR4(memSpecConfig); else if (memoryType == "LPDDR5") - memSpec = new MemSpecLPDDR5(jMemSpec); + config.memSpec = new MemSpecLPDDR5(memSpecConfig); else if (memoryType == "WIDEIO_SDR") - memSpec = new MemSpecWideIO(jMemSpec); + config.memSpec = new MemSpecWideIO(memSpecConfig); else if (memoryType == "WIDEIO2") - memSpec = new MemSpecWideIO2(jMemSpec); + config.memSpec = new MemSpecWideIO2(memSpecConfig); else if (memoryType == "HBM2") - memSpec = new MemSpecHBM2(jMemSpec); + config.memSpec = new MemSpecHBM2(memSpecConfig); else if (memoryType == "GDDR5") - memSpec = new MemSpecGDDR5(jMemSpec); + config.memSpec = new MemSpecGDDR5(memSpecConfig); else if (memoryType == "GDDR5X") - memSpec = new MemSpecGDDR5X(jMemSpec); + config.memSpec = new MemSpecGDDR5X(memSpecConfig); else if (memoryType == "GDDR6") - memSpec = new MemSpecGDDR6(jMemSpec); + config.memSpec = new MemSpecGDDR6(memSpecConfig); else if (memoryType == "STT-MRAM") - memSpec = new MemSpecSTTMRAM(jMemSpec); + config.memSpec = new MemSpecSTTMRAM(memSpecConfig); else SC_REPORT_FATAL("Configuration", "Unsupported DRAM type"); } diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index a7538f24..54c16727 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -42,7 +42,7 @@ #define CONFIGURATION_H #include - +#include #include #include "memspec/MemSpec.h" #include "../error/eccbaseclass.h" @@ -62,9 +62,6 @@ private: Configuration &operator = (const Configuration &); public: - static std::string memspecUri; - static std::string mcconfigUri; - // MCConfig: enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open; enum class Scheduler {Fifo, FrFcfs, FrFcfsGrp} scheduler = Scheduler::FrFcfs; @@ -102,26 +99,23 @@ public: bool useMalloc = false; unsigned long long int addressOffset = 0; - // MemSpec (from DRAM-Power) - const MemSpec *memSpec = nullptr; - - void setParameter(const std::string &name, const nlohmann::json &value); - //Configs for Seed, csv file and StorageMode unsigned int errorChipSeed = 0; std::string errorCSVFile = "not defined."; enum class StoreMode {NoStorage, Store, ErrorModel} storeMode = StoreMode::NoStorage; + // MemSpec (from DRAM-Power) + const MemSpec *memSpec = nullptr; + // Temperature Simulation related TemperatureSimConfig temperatureSim; unsigned int adjustNumBytesAfterECC(unsigned bytes) const; - void setPathToResources(const std::string &path); - static void loadMCConfig(Configuration &config, const std::string &_mcconfigUri); - static void loadSimConfig(Configuration &config, const std::string &simconfigUri); - void loadMemSpec(Configuration &config, const std::string &_memspecUri); - static void loadTemperatureSimConfig(Configuration &config, const std::string &simconfigUri); + static void loadMCConfig(Configuration &config, const DRAMSysConfiguration::McConfig &mcConfig); + static void loadSimConfig(Configuration &config, const DRAMSysConfiguration::SimConfig &simConfig); + static void loadMemSpec(Configuration &config, const DRAMSysConfiguration::MemSpec &memSpec); + static void loadTemperatureSimConfig(Configuration &config, const DRAMSysConfiguration::ThermalConfig &thermalConfig); }; #endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/configuration/TemperatureSimConfig.h index 48f0169e..c7f94265 100644 --- a/DRAMSys/library/src/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/configuration/TemperatureSimConfig.h @@ -40,7 +40,7 @@ #include #include - +#include #include #include #include "../common/DebugManager.h" @@ -48,13 +48,7 @@ struct TemperatureSimConfig { // Temperature Scale - std::string temperatureScale; - std::string pathToResources; - - void setPathToResources(std::string path) - { - pathToResources = std::move(path); - } + enum class TemperatureScale {Celsius, Fahrenheit, Kelvin} temperatureScale; // Static Temperature Simulation parameters int staticTemperatureDefaultValue; @@ -70,47 +64,9 @@ struct TemperatureSimConfig bool generatePowerMap; // Power related information - std::string powerInfoFile; std::vector powerInitialValues; std::vector powerThresholds; - void parsePowerInfoFile() - { - PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile); - - powerInfoFile = pathToResources - + "/configs/thermalsim/" - + powerInfoFile; - - // Load the JSON file into memory and parse it - nlohmann::json powInfoElem = parseJSON(powerInfoFile); - - if (powInfoElem["powerInfo"].empty()) - { - // Invalid file - std::string errormsg = "Invalid Power Info File " + powerInfoFile; - PRINTDEBUGMESSAGE("TemperatureSimConfig", errormsg); - SC_REPORT_FATAL("Temperature Sim Config", errormsg.c_str()); - } - else - { - for (const auto& it : powInfoElem["powerInfo"].items()) - { - // Load initial power values for all devices - auto value = it.value(); - float pow = value["init_pow"]; - powerInitialValues.push_back(pow); - - // Load power thresholds for all devices - //Changes in power dissipation that exceed the threshods - //will make the thermal simulation to be executed more often) - float thr = value["threshold"]; - powerThresholds.push_back(thr); - } - } - showTemperatureSimConfig(); - } - void showTemperatureSimConfig() { NDEBUG_UNUSED(int i) = 0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index ee7b511b..09179655 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -37,9 +37,9 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpec::MemSpec(json &memspec, MemoryType memoryType, +MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec, + MemoryType memoryType, unsigned numberOfChannels, unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, @@ -53,16 +53,16 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType, numberOfBanks(numberOfBanks), numberOfBankGroups(numberOfBankGroups), numberOfDevices(numberOfDevices), - numberOfRows(parseUint(memspec["memarchitecturespec"], "nbrOfRows")), - numberOfColumns(parseUint(memspec["memarchitecturespec"], "nbrOfColumns")), - burstLength(parseUint(memspec["memarchitecturespec"], "burstLength")), - dataRate(parseUint(memspec["memarchitecturespec"], "dataRate")), - bitWidth(parseUint(memspec["memarchitecturespec"], "width")), + numberOfRows(memSpec.memArchitectureSpec.entries.at("nbrOfRows")), + numberOfColumns(memSpec.memArchitectureSpec.entries.at("nbrOfColumns")), + burstLength(memSpec.memArchitectureSpec.entries.at("burstLength")), + dataRate(memSpec.memArchitectureSpec.entries.at("dataRate")), + bitWidth(memSpec.memArchitectureSpec.entries.at("width")), dataBusWidth(bitWidth * numberOfDevices), bytesPerBurst((burstLength * dataBusWidth) / 8), - fCKMHz(parseUdouble(memspec["memtimingspec"], "clkMhz")), + fCKMHz(memSpec.memTimingSpec.entries.at("clkMhz")), tCK(sc_time(1.0 / fCKMHz, SC_US)), - memoryId(parseString(memspec, "memoryId")), + memoryId(memSpec.memoryId), memoryType(memoryType), burstDuration(tCK * (static_cast(burstLength) / dataRate)), memorySizeBytes(0) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 7448a9e7..0af08d5d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -40,11 +40,10 @@ #include #include - +#include #include #include #include "../../common/utils.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" #include "../../controller/Command.h" class MemSpec @@ -96,7 +95,8 @@ public: uint64_t getSimMemSizeInBytes() const; protected: - MemSpec(nlohmann::json &memspec, MemoryType memoryType, + MemSpec(const DRAMSysConfiguration::MemSpec &memSpec, + MemoryType memoryType, unsigned numberOfChannels, unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 1e599c99..ff1a05ca 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -40,63 +40,65 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecDDR3::MemSpecDDR3(json &memspec) - : MemSpec(memspec, MemoryType::DDR3, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), +MemSpecDDR3::MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::DDR3, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), 1, - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), tPD (tCKE), - tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")), - tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), - tAL (tCK * parseUint(memspec["memtimingspec"], "AL")), - tXPDLL (tCK * parseUint(memspec["memtimingspec"], "XPDLL")), - tXSDLL (tCK * parseUint(memspec["memtimingspec"], "XSDLL")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")), - iDD0 (parseUdouble(memspec["mempowerspec"], "idd0")), - iDD2N (parseUdouble(memspec["mempowerspec"], "idd2n")), - iDD3N (parseUdouble(memspec["mempowerspec"], "idd3n")), - iDD4R (parseUdouble(memspec["mempowerspec"], "idd4r")), - iDD4W (parseUdouble(memspec["mempowerspec"], "idd4w")), - iDD5 (parseUdouble(memspec["mempowerspec"], "idd5")), - iDD6 (parseUdouble(memspec["mempowerspec"], "idd6")), - vDD (parseUdouble(memspec["mempowerspec"], "vdd")), - iDD2P0 (parseUdouble(memspec["mempowerspec"], "idd2p0")), - iDD2P1 (parseUdouble(memspec["mempowerspec"], "idd2p1")), - iDD3P0 (parseUdouble(memspec["mempowerspec"], "idd3p0")), - iDD3P1 (parseUdouble(memspec["mempowerspec"], "idd3p1")) + tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")), + tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")), + tAL (tCK * memSpec.memTimingSpec.entries.at("AL")), + tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")), + tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")), + tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")), + tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")), + tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), + iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")), + iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")), + iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")), + iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")), + iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")), + iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")), + iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")), + vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")), + iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")), + iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")), + iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")), + iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels; + if (!memSpec.memPowerSpec.isValid()) + SC_REPORT_FATAL("MemSpec", "No power spec defined!"); + std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; std::cout << " Memory type: " << "DDR3" << std::endl; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 711df6d5..5924afff 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -36,14 +36,15 @@ #ifndef MEMSPECDDR3_H #define MEMSPECDDR3_H -#include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" + +#include +#include class MemSpecDDR3 final : public MemSpec { public: - explicit MemSpecDDR3(nlohmann::json &memspec); + explicit MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tCKE; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index b8b119de..c1176f80 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -40,81 +40,83 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecDDR4::MemSpecDDR4(json &memspec) - : MemSpec(memspec, MemoryType::DDR4, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), +MemSpecDDR4::MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::DDR4, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), tPD (tCKE), - tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tRPRE (tCK * parseUint(memspec["memtimingspec"], "RPRE")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tREFI ((parseUint(memspec["memtimingspec"], "REFM") == 4) ? - (tCK * (static_cast(parseUint(memspec["memtimingspec"], "REFI")) / 4)) : - ((parseUint(memspec["memtimingspec"], "REFM") == 2) ? - (tCK * (static_cast(parseUint(memspec["memtimingspec"], "REFI")) / 2)) : - (tCK * parseUint(memspec["memtimingspec"], "REFI")))), - tRFC ((parseUint(memspec["memtimingspec"], "REFM") == 4) ? - (tCK * parseUint(memspec["memtimingspec"], "RFC4")) : - ((parseUint(memspec["memtimingspec"], "REFM") == 2) ? - (tCK * parseUint(memspec["memtimingspec"], "RFC2")) : - (tCK * parseUint(memspec["memtimingspec"], "RFC")))), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tCCD_S (tCK * parseUint(memspec["memtimingspec"], "CCD_S")), - tCCD_L (tCK * parseUint(memspec["memtimingspec"], "CCD_L")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tRRD_S (tCK * parseUint(memspec["memtimingspec"], "RRD_S")), - tRRD_L (tCK * parseUint(memspec["memtimingspec"], "RRD_L")), - tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")), - tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")), - tAL (tCK * parseUint(memspec["memtimingspec"], "AL")), - tXPDLL (tCK * parseUint(memspec["memtimingspec"], "XPDLL")), - tXSDLL (tCK * parseUint(memspec["memtimingspec"], "XSDLL")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")), - iDD0 (parseUdouble(memspec["mempowerspec"], "idd0")), - iDD2N (parseUdouble(memspec["mempowerspec"], "idd2n")), - iDD3N (parseUdouble(memspec["mempowerspec"], "idd3n")), - iDD4R (parseUdouble(memspec["mempowerspec"], "idd4r")), - iDD4W (parseUdouble(memspec["mempowerspec"], "idd4w")), - iDD5 (parseUdouble(memspec["mempowerspec"], "idd5")), - iDD6 (parseUdouble(memspec["mempowerspec"], "idd6")), - vDD (parseUdouble(memspec["mempowerspec"], "vdd")), - iDD02 (parseUdouble(memspec["mempowerspec"], "idd02")), - iDD2P0 (parseUdouble(memspec["mempowerspec"], "idd2p0")), - iDD2P1 (parseUdouble(memspec["mempowerspec"], "idd2p1")), - iDD3P0 (parseUdouble(memspec["mempowerspec"], "idd3p0")), - iDD3P1 (parseUdouble(memspec["mempowerspec"], "idd3p1")), - iDD62 (parseUdouble(memspec["mempowerspec"], "idd62")), - vDD2 (parseUdouble(memspec["mempowerspec"], "vdd2")) + tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tRPRE (tCK * memSpec.memTimingSpec.entries.at("RPRE")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tREFI ((memSpec.memTimingSpec.entries.at("REFM") == 4) ? + (tCK * (static_cast(memSpec.memTimingSpec.entries.at("REFI")) / 4)) : + ((memSpec.memTimingSpec.entries.at("REFM") == 2) ? + (tCK * (static_cast(memSpec.memTimingSpec.entries.at("REFI")) / 2)) : + (tCK * memSpec.memTimingSpec.entries.at("REFI")))), + tRFC ((memSpec.memTimingSpec.entries.at("REFM") == 4) ? + (tCK * memSpec.memTimingSpec.entries.at("RFC4")) : + ((memSpec.memTimingSpec.entries.at("REFM") == 2) ? + (tCK * memSpec.memTimingSpec.entries.at("RFC2")) : + (tCK * memSpec.memTimingSpec.entries.at("RFC")))), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tCCD_S (tCK * memSpec.memTimingSpec.entries.at("CCD_S")), + tCCD_L (tCK * memSpec.memTimingSpec.entries.at("CCD_L")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tRRD_S (tCK * memSpec.memTimingSpec.entries.at("RRD_S")), + tRRD_L (tCK * memSpec.memTimingSpec.entries.at("RRD_L")), + tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), + tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")), + tAL (tCK * memSpec.memTimingSpec.entries.at("AL")), + tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")), + tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")), + tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")), + tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")), + tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), + iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")), + iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")), + iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")), + iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")), + iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")), + iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")), + iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")), + vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")), + iDD02 (memSpec.memPowerSpec.getValue().entries.at("idd02")), + iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")), + iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")), + iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")), + iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")), + iDD62 (memSpec.memPowerSpec.getValue().entries.at("idd62")), + vDD2 (memSpec.memPowerSpec.getValue().entries.at("vdd2")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels; + if (!memSpec.memPowerSpec.isValid()) + SC_REPORT_FATAL("MemSpec", "No power spec defined!"); + std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; std::cout << " Memory type: " << "DDR4" << std::endl; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 14adddd7..67f3fe24 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecDDR4 final : public MemSpec { public: - explicit MemSpecDDR4(nlohmann::json &memspec); + explicit MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tCKE; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 40648435..f42c4b14 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -40,84 +40,83 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecDDR5::MemSpecDDR5(json &memspec) - : MemSpec(memspec, MemoryType::DDR5, - parseUint(memspec["memarchitecturespec"], "nbrOfChannels"), - parseUint(memspec["memarchitecturespec"], "nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - numberOfDIMMRanks(parseUint(memspec["memarchitecturespec"], "nbrOfDIMMRanks")), - physicalRanksPerDIMMRank(parseUint(memspec["memarchitecturespec"], "nbrOfPhysicalRanks")), +MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::DDR5, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + numberOfDIMMRanks(memSpec.memArchitectureSpec.entries.at("nbrOfDIMMRanks")), + physicalRanksPerDIMMRank(memSpec.memArchitectureSpec.entries.at("nbrOfPhysicalRanks")), numberOfPhysicalRanks(physicalRanksPerDIMMRank * numberOfDIMMRanks), - logicalRanksPerPhysicalRank(parseUint(memspec["memarchitecturespec"], "nbrOfLogicalRanks")), + logicalRanksPerPhysicalRank(memSpec.memArchitectureSpec.entries.at("nbrOfLogicalRanks")), numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks), - cmdMode(parseUint(memspec["memarchitecturespec"], "cmdMode")), - refMode(parseUint(memspec["memarchitecturespec"], "refMode")), - RAAIMT(parseUint(memspec["memarchitecturespec"], "RAAIMT")), - RAAMMT(parseUint(memspec["memarchitecturespec"], "RAAMMT")), - RAACDR(parseUint(memspec["memarchitecturespec"], "RAACDR")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), + cmdMode(memSpec.memArchitectureSpec.entries.at("cmdMode")), + refMode(memSpec.memArchitectureSpec.entries.at("refMode")), + RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")), + RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")), + RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), tRC (tRAS + tRP), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tRPRE (tCK * parseUint(memspec["memtimingspec"], "RPRE")), - tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), - tRDDQS (tCK * parseUint(memspec["memtimingspec"], "RDDQS")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), - tWPST (tCK * parseUint(memspec["memtimingspec"], "WPST")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tCCD_L_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_slr")), - tCCD_L_WR_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_WR_slr")), - tCCD_L_WR2_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_WR2_slr")), - tCCD_S_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_S_slr")), - tCCD_S_WR_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_S_WR_slr")), - tCCD_dlr (tCK * parseUint(memspec["memtimingspec"], "CCD_dlr")), - tCCD_WR_dlr (tCK * parseUint(memspec["memtimingspec"], "CCD_WR_dlr")), - tCCD_WR_dpr (tCK * parseUint(memspec["memtimingspec"], "CCD_WR_dpr")), - tRRD_L_slr (tCK * parseUint(memspec["memtimingspec"], "RRD_L_slr")), - tRRD_S_slr (tCK * parseUint(memspec["memtimingspec"], "RRD_S_slr")), - tRRD_dlr (tCK * parseUint(memspec["memtimingspec"], "RRD_dlr")), - tFAW_slr (tCK * parseUint(memspec["memtimingspec"], "FAW_slr")), - tFAW_dlr (tCK * parseUint(memspec["memtimingspec"], "FAW_dlr")), - tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")), - tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")), - tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_slr") - : tCK * parseUint(memspec["memtimingspec"], "RFC2_slr")), - tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_dlr") - : tCK * parseUint(memspec["memtimingspec"], "RFC2_dlr")), - tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_dpr") - : tCK * parseUint(memspec["memtimingspec"], "RFC2_dpr")), - tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"], "RFCsb_slr")), - tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"], "RFCsb_dlr")), - tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "REFI1") - : tCK * parseUint(memspec["memtimingspec"], "REFI2")), - tREFIsb (tCK * parseUint(memspec["memtimingspec"], "REFISB")), - tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"], "REFSBRD_slr")), - tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"], "REFSBRD_dlr")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")), - tCPDED (tCK * parseUint(memspec["memtimingspec"], "CPDED")), - tPD (tCK * parseUint(memspec["memtimingspec"], "PD")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tRPRE (tCK * memSpec.memTimingSpec.entries.at("RPRE")), + tRPST (tCK * memSpec.memTimingSpec.entries.at("RPST")), + tRDDQS (tCK * memSpec.memTimingSpec.entries.at("RDDQS")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")), + tWPST (tCK * memSpec.memTimingSpec.entries.at("WPST")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tCCD_L_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_slr")), + tCCD_L_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR_slr")), + tCCD_L_WR2_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR2_slr")), + tCCD_S_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_slr")), + tCCD_S_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_WR_slr")), + tCCD_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_dlr")), + tCCD_WR_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_WR_dlr")), + tCCD_WR_dpr (tCK * memSpec.memTimingSpec.entries.at("CCD_WR_dpr")), + tRRD_L_slr (tCK * memSpec.memTimingSpec.entries.at("RRD_L_slr")), + tRRD_S_slr (tCK * memSpec.memTimingSpec.entries.at("RRD_S_slr")), + tRRD_dlr (tCK * memSpec.memTimingSpec.entries.at("RRD_dlr")), + tFAW_slr (tCK * memSpec.memTimingSpec.entries.at("FAW_slr")), + tFAW_dlr (tCK * memSpec.memTimingSpec.entries.at("FAW_dlr")), + tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")), + tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), + tRFC_slr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_slr") + : tCK * memSpec.memTimingSpec.entries.at("RFC2_slr")), + tRFC_dlr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dlr") + : tCK * memSpec.memTimingSpec.entries.at("RFC2_dlr")), + tRFC_dpr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dpr") + : tCK * memSpec.memTimingSpec.entries.at("RFC2_dpr")), + tRFCsb_slr (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), + tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), + tREFI ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("REFI1") + : tCK * memSpec.memTimingSpec.entries.at("REFI2")), + tREFIsb (tCK * memSpec.memTimingSpec.entries.at("REFISB")), + tREFSBRD_slr (tCK * memSpec.memTimingSpec.entries.at("REFSBRD_slr")), + tREFSBRD_dlr (tCK * memSpec.memTimingSpec.entries.at("REFSBRD_dlr")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), + tCPDED (tCK * memSpec.memTimingSpec.entries.at("CPDED")), + tPD (tCK * memSpec.memTimingSpec.entries.at("PD")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")), + tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")), + tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")), shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK), longCmdOffset (cmdMode == 2 ? 3 * tCK : 1 * tCK), - tBURST16(tCK * 8), - tBURST32(tCK * 16) + tBURST16 (tCK * 8), + tBURST32 (tCK * 16) { if (cmdMode == 1) { diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index 44e344f8..39b05e8c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecDDR5 final : public MemSpec { public: - explicit MemSpecDDR5(nlohmann::json &memspec); + explicit MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec); const unsigned numberOfDIMMRanks; const unsigned physicalRanksPerDIMMRank; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index f498f21b..13318e7b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -40,55 +40,54 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecGDDR5::MemSpecGDDR5(json &memspec) - : MemSpec(memspec, MemoryType::GDDR5, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")), - tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")), - tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")), - tCL (tCK * parseUint(memspec["memtimingspec"], "CL")), - tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")), - tWCK2CK (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")), - tWCK2DQO (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")), - tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWCK2DQI (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), - tPD (tCK * parseUint(memspec["memtimingspec"], "PD")), - tXPN (tCK * parseUint(memspec["memtimingspec"], "XPN")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tREFIPB (tCK * parseUint(memspec["memtimingspec"], "REFIPB")), - tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")), - tRFCPB (tCK * parseUint(memspec["memtimingspec"], "RFCPB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - t32AW (tCK * parseUint(memspec["memtimingspec"], "32AW")), - tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")), - tLK (tCK * parseUint(memspec["memtimingspec"], "LK")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) +MemSpecGDDR5::MemSpecGDDR5(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::GDDR5, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")), + tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")), + tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")), + tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")), + tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")), + tCL (tCK * memSpec.memTimingSpec.entries.at("CL")), + tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")), + tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")), + tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")), + tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")), + tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), + tPD (tCK * memSpec.memTimingSpec.entries.at("PD")), + tXPN (tCK * memSpec.memTimingSpec.entries.at("XPN")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")), + tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")), + tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")), + tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")), + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + t32AW (tCK * memSpec.memTimingSpec.entries.at("32AW")), + tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")), + tLK (tCK * memSpec.memTimingSpec.entries.at("LK")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index b66df343..bd8dc580 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecGDDR5 final : public MemSpec { public: - explicit MemSpecGDDR5(nlohmann::json &memspec); + explicit MemSpecGDDR5(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tRP; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index af98befb..ea04e6b8 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -39,55 +39,54 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) - : MemSpec(memspec, MemoryType::GDDR5X, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")), - tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")), - tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")), - tRL (tCK * parseUint(memspec["memtimingspec"], "CL")), - tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")), - tWCK2CK (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")), - tWCK2DQO (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")), - tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWCK2DQI (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), - tPD (tCK * parseUint(memspec["memtimingspec"], "PD")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tREFIPB (tCK * parseUint(memspec["memtimingspec"], "REFIPB")), - tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")), - tRFCPB (tCK * parseUint(memspec["memtimingspec"], "RFCPB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - t32AW (tCK * parseUint(memspec["memtimingspec"], "32AW")), - tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")), - tLK (tCK * parseUint(memspec["memtimingspec"], "LK")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) +MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::GDDR5X, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")), + tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")), + tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")), + tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")), + tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")), + tRL (tCK * memSpec.memTimingSpec.entries.at("CL")), + tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")), + tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")), + tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")), + tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")), + tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), + tPD (tCK * memSpec.memTimingSpec.entries.at("PD")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")), + tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")), + tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")), + tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")), + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + t32AW (tCK * memSpec.memTimingSpec.entries.at("32AW")), + tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")), + tLK (tCK * memSpec.memTimingSpec.entries.at("LK")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("TRS")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index 4d181f12..002d8221 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecGDDR5X final : public MemSpec { public: - explicit MemSpecGDDR5X(nlohmann::json &memspec); + explicit MemSpecGDDR5X(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tRP; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index a7690dba..86a54674 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -40,58 +40,57 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecGDDR6::MemSpecGDDR6(json &memspec) - : MemSpec(memspec, MemoryType::GDDR6, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - per2BankOffset(parseUint(memspec["memarchitecturespec"], "per2BankOffset")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")), - tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")), - tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")), - tWCK2CK (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")), - tWCK2DQO (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")), - tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWCK2DQI (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")), - tPD (tCK * parseUint(memspec["memtimingspec"], "PD")), - tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIpb")), - tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCab")), - tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCpb")), - tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")), - tLK (tCK * parseUint(memspec["memtimingspec"], "LK")), - tACTPDE (tCK * parseUint(memspec["memtimingspec"], "ACTPDE")), - tPREPDE (tCK * parseUint(memspec["memtimingspec"], "PREPDE")), - tREFPDE (tCK * parseUint(memspec["memtimingspec"], "REFPDE")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) +MemSpecGDDR6::MemSpecGDDR6(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::GDDR6, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + per2BankOffset(memSpec.memArchitectureSpec.entries.at("per2BankOffset")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")), + tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")), + tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")), + tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")), + tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")), + tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")), + tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")), + tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")), + tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")), + tPD (tCK * memSpec.memTimingSpec.entries.at("PD")), + tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIpb")), + tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCab")), + tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCpb")), + tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")), + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")), + tLK (tCK * memSpec.memTimingSpec.entries.at("LK")), + tACTPDE (tCK * memSpec.memTimingSpec.entries.at("ACTPDE")), + tPREPDE (tCK * memSpec.memTimingSpec.entries.at("PREPDE")), + tREFPDE (tCK * memSpec.memTimingSpec.entries.at("REFPDE")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index 8deb3605..7d75362b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" struct MemSpecGDDR6 final : public MemSpec { public: - explicit MemSpecGDDR6(nlohmann::json &memspec); + explicit MemSpecGDDR6(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tRP; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 6d382555..852af18e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -40,50 +40,49 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecHBM2::MemSpecHBM2(json &memspec) - : MemSpec(memspec, MemoryType::HBM2, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")), - tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")), - tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")), - tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tPL (tCK * parseUint(memspec["memtimingspec"], "PL")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")), - tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")), - tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")), - tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")), - tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), +MemSpecHBM2::MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::HBM2, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")), + tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")), + tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")), + tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tPL (tCK * memSpec.memTimingSpec.entries.at("PL")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")), + tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")), + tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")), + tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")), + tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), tPD (tCKE), tCKESR (tCKE + tCK), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")), - tRFCSB (tCK * parseUint(memspec["memtimingspec"], "RFCSB")), - tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tREFISB (tCK * parseUint(memspec["memtimingspec"], "REFISB")) + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")), + tRFCSB (tCK * memSpec.memTimingSpec.entries.at("RFCSB")), + tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tREFISB (tCK * memSpec.memTimingSpec.entries.at("REFISB")) { commandLengthInCycles[Command::ACT] = 2; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 5eeb6355..565f7eeb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecHBM2 final : public MemSpec { public: - explicit MemSpecHBM2(nlohmann::json &memspec); + explicit MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tDQSCK; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 53647408..a1b81479 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -40,50 +40,49 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) - : MemSpec(memspec, MemoryType::LPDDR4, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), +MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::LPDDR4, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), 1, - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIPB")), - tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCAB")), - tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCPB")), - tRPab (tCK * parseUint(memspec["memtimingspec"], "RPAB")), - tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPPB")), - tRCab (tCK * parseUint(memspec["memtimingspec"], "RCAB")), - tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCPB")), - tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")), - tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), - tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), - tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tSR (tCK * parseUint(memspec["memtimingspec"], "SR")), - tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")), - tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), - tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIPB")), + tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCAB")), + tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")), + tRPab (tCK * memSpec.memTimingSpec.entries.at("RPAB")), + tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPPB")), + tRCab (tCK * memSpec.memTimingSpec.entries.at("RCAB")), + tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCPB")), + tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")), + tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tRPST (tCK * memSpec.memTimingSpec.entries.at("RPST")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tDQSS (tCK * memSpec.memTimingSpec.entries.at("DQSS")), + tDQS2DQ (tCK * memSpec.memTimingSpec.entries.at("DQS2DQ")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")), + tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tSR (tCK * memSpec.memTimingSpec.entries.at("SR")), + tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")), + tESCKE (tCK * memSpec.memTimingSpec.entries.at("ESCKE")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), + tCMDCKE (tCK * memSpec.memTimingSpec.entries.at("CMDCKE")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")) { commandLengthInCycles[Command::ACT] = 4; commandLengthInCycles[Command::PREPB] = 2; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 129328ae..05fd8ad2 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecLPDDR4 final : public MemSpec { public: - explicit MemSpecLPDDR4(nlohmann::json &memspec); + explicit MemSpecLPDDR4(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tREFI; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp index 50532945..95fcfd9c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp @@ -40,44 +40,43 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecLPDDR5::MemSpecLPDDR5(json &memspec) - : MemSpec(memspec, MemoryType::LPDDR5, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - per2BankOffset(parseUint(memspec["memarchitecturespec"], "per2BankOffset")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIpb")), - tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCab")), - tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCpb")), - tRPab (tCK * parseUint(memspec["memtimingspec"], "RPab")), - tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPpb")), - tRCab (tCK * parseUint(memspec["memtimingspec"], "RCab")), - tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCpb")), - tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")), +MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::LPDDR5, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + / memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + per2BankOffset(memSpec.memArchitectureSpec.entries.at("per2BankOffset")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIpb")), + tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCab")), + tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCpb")), + tRPab (tCK * memSpec.memTimingSpec.entries.at("RPab")), + tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPpb")), + tRCab (tCK * memSpec.memTimingSpec.entries.at("RCab")), + tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCpb")), + tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")), //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), //tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), //tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRBTP (tCK * parseUint(memspec["memtimingspec"], "RBTP")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), + tRBTP (tCK * memSpec.memTimingSpec.entries.at("RBTP")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), //tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), //tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), //tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), //tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), //tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), @@ -86,20 +85,20 @@ MemSpecLPDDR5::MemSpecLPDDR5(json &memspec) //tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")), //tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), //tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")), - BL_n_min_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_min_16")), - BL_n_max_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_max_16")), - BL_n_L_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_L_16")), - BL_n_S_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_S_16")), - BL_n_min_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_min_32")), - BL_n_max_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_max_32")), - BL_n_L_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_L_32")), - BL_n_S_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_S_32")), - tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")), - tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")), - tWCK2DQO(tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")), - tpbR2act(tCK * parseUint(memspec["memtimingspec"], "pbR2act")), - tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "pbR2pbR")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) + BL_n_min_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_min_16")), + BL_n_max_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_max_16")), + BL_n_L_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_L_16")), + BL_n_S_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_S_16")), + BL_n_min_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_min_32")), + BL_n_max_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_max_32")), + BL_n_L_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_L_32")), + BL_n_S_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_S_32")), + tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")), + tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), + tWCK2DQO(tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")), + tpbR2act(tCK * memSpec.memTimingSpec.entries.at("pbR2act")), + tpbR2pbR(tCK * memSpec.memTimingSpec.entries.at("pbR2pbR")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")) { commandLengthInCycles[Command::ACT] = 2; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.h index 48fc7b2c..1635b384 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.h @@ -43,7 +43,7 @@ class MemSpecLPDDR5 final : public MemSpec { public: - explicit MemSpecLPDDR5(nlohmann::json &memspec); + explicit MemSpecLPDDR5(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tREFI; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp index 198f5de7..586b2ac5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp @@ -40,43 +40,42 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecSTTMRAM::MemSpecSTTMRAM(json &memspec) - : MemSpec(memspec, MemoryType::STTMRAM, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), +MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::STTMRAM, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), 1, - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), tPD (tCKE), - tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tXS (tCK * parseUint(memspec["memtimingspec"], "XS")), - tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")), - tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), - tAL (tCK * parseUint(memspec["memtimingspec"], "AL")), - tXPDLL (tCK * parseUint(memspec["memtimingspec"], "XPDLL")), - tXSDLL (tCK * parseUint(memspec["memtimingspec"], "XSDLL")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) + tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tXS (tCK * memSpec.memTimingSpec.entries.at("XS")), + tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")), + tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")), + tAL (tCK * memSpec.memTimingSpec.entries.at("AL")), + tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")), + tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")), + tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")), + tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h index e30b22b2..72749afc 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecSTTMRAM final : public MemSpec { public: - explicit MemSpecSTTMRAM(nlohmann::json &memspec); + explicit MemSpecSTTMRAM(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tCKE; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index e363d1a5..e5ba6610 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -40,69 +40,71 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecWideIO::MemSpecWideIO(json &memspec) - : MemSpec(memspec, MemoryType::WideIO, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), +MemSpecWideIO::MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::WideIO, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), 1, - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), - tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tAC (tCK * parseUint(memspec["memtimingspec"], "AC")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tRC (tCK * parseUint(memspec["memtimingspec"], "RC")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")), - tCCD_R (tCK * parseUint(memspec["memtimingspec"], "CCD_R")), - tCCD_W (tCK * parseUint(memspec["memtimingspec"], "CCD_W")), - tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")), - tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")), - tRP (tCK * parseUint(memspec["memtimingspec"], "RP")), - tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")), - tTAW (tCK * parseUint(memspec["memtimingspec"], "TAW")), - tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")), - iDD0 (parseUdouble(memspec["mempowerspec"], "idd0")), - iDD2N (parseUdouble(memspec["mempowerspec"], "idd2n")), - iDD3N (parseUdouble(memspec["mempowerspec"], "idd3n")), - iDD4R (parseUdouble(memspec["mempowerspec"], "idd4r")), - iDD4W (parseUdouble(memspec["mempowerspec"], "idd4w")), - iDD5 (parseUdouble(memspec["mempowerspec"], "idd5")), - iDD6 (parseUdouble(memspec["mempowerspec"], "idd6")), - vDD (parseUdouble(memspec["mempowerspec"], "vdd")), - iDD02 (parseUdouble(memspec["mempowerspec"], "idd02")), - iDD2P0 (parseUdouble(memspec["mempowerspec"], "idd2p0")), - iDD2P02 (parseUdouble(memspec["mempowerspec"], "idd2p02")), - iDD2P1 (parseUdouble(memspec["mempowerspec"], "idd2p1")), - iDD2P12 (parseUdouble(memspec["mempowerspec"], "idd2p12")), - iDD2N2 (parseUdouble(memspec["mempowerspec"], "idd2n2")), - iDD3P0 (parseUdouble(memspec["mempowerspec"], "idd3p0")), - iDD3P02 (parseUdouble(memspec["mempowerspec"], "idd3p02")), - iDD3P1 (parseUdouble(memspec["mempowerspec"], "idd3p1")), - iDD3P12 (parseUdouble(memspec["mempowerspec"], "idd3p12")), - iDD3N2 (parseUdouble(memspec["mempowerspec"], "idd3n2")), - iDD4R2 (parseUdouble(memspec["mempowerspec"], "idd4r2")), - iDD4W2 (parseUdouble(memspec["mempowerspec"], "idd4w2")), - iDD52 (parseUdouble(memspec["mempowerspec"], "idd52")), - iDD62 (parseUdouble(memspec["mempowerspec"], "idd62")), - vDD2 (parseUdouble(memspec["mempowerspec"], "vdd2")) + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), + tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tAC (tCK * memSpec.memTimingSpec.entries.at("AC")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tRC (tCK * memSpec.memTimingSpec.entries.at("RC")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")), + tCCD_R (tCK * memSpec.memTimingSpec.entries.at("CCD_R")), + tCCD_W (tCK * memSpec.memTimingSpec.entries.at("CCD_W")), + tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")), + tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")), + tRP (tCK * memSpec.memTimingSpec.entries.at("RP")), + tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")), + tTAW (tCK * memSpec.memTimingSpec.entries.at("TAW")), + tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), + iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")), + iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")), + iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")), + iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")), + iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")), + iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")), + iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")), + vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")), + iDD02 (memSpec.memPowerSpec.getValue().entries.at("idd02")), + iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")), + iDD2P02 (memSpec.memPowerSpec.getValue().entries.at("idd2p02")), + iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")), + iDD2P12 (memSpec.memPowerSpec.getValue().entries.at("idd2p12")), + iDD2N2 (memSpec.memPowerSpec.getValue().entries.at("idd2n2")), + iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")), + iDD3P02 (memSpec.memPowerSpec.getValue().entries.at("idd3p02")), + iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")), + iDD3P12 (memSpec.memPowerSpec.getValue().entries.at("idd3p12")), + iDD3N2 (memSpec.memPowerSpec.getValue().entries.at("idd3n2")), + iDD4R2 (memSpec.memPowerSpec.getValue().entries.at("idd4r2")), + iDD4W2 (memSpec.memPowerSpec.getValue().entries.at("idd4w2")), + iDD52 (memSpec.memPowerSpec.getValue().entries.at("idd52")), + iDD62 (memSpec.memPowerSpec.getValue().entries.at("idd62")), + vDD2 (memSpec.memPowerSpec.getValue().entries.at("vdd2")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels; + if (!memSpec.memPowerSpec.isValid()) + SC_REPORT_FATAL("MemSpec", "No power spec defined!"); + std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; std::cout << " Memory type: " << "Wide I/O" << std::endl; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 3b952621..afce3e92 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecWideIO final : public MemSpec { public: - explicit MemSpecWideIO(nlohmann::json &memspec); + explicit MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tCKE; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 275529e4..736548e1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -40,46 +40,45 @@ using namespace sc_core; using namespace tlm; -using json = nlohmann::json; -MemSpecWideIO2::MemSpecWideIO2(json &memspec) - : MemSpec(memspec, MemoryType::WideIO2, - parseUint(memspec["memarchitecturespec"],"nbrOfChannels"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), +MemSpecWideIO2::MemSpecWideIO2(const DRAMSysConfiguration::MemSpec &memSpec) + : MemSpec(memSpec, MemoryType::WideIO2, + memSpec.memArchitectureSpec.entries.at("nbrOfChannels"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), 1, - parseUint(memspec["memarchitecturespec"],"nbrOfBanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfBanks") - * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"],"nbrOfDevices")), - tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), - tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), - tRL (tCK * parseUint(memspec["memtimingspec"], "RL")), - tWL (tCK * parseUint(memspec["memtimingspec"], "WL")), - tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCPB")), - tRCab (tCK * parseUint(memspec["memtimingspec"], "RCAB")), - tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")), - tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")), - tXP (tCK * parseUint(memspec["memtimingspec"], "XP")), - tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")), - tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")), - tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPPB")), - tRPab (tCK * parseUint(memspec["memtimingspec"], "RPAB")), - tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")), - tWR (tCK * parseUint(memspec["memtimingspec"], "WR")), - tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), - tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")), - tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")), - tREFI (tCK * static_cast(parseUint(memspec["memtimingspec"], "REFI") - * parseUdouble(memspec["memtimingspec"], "REFM"))), - tREFIpb (tCK * static_cast(parseUint(memspec["memtimingspec"], "REFIPB") - * parseUdouble(memspec["memtimingspec"], "REFM"))), - tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCAB")), - tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCPB")), - tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")) + memSpec.memArchitectureSpec.entries.at("nbrOfBanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfBanks") + * memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfRanks"), + memSpec.memArchitectureSpec.entries.at("nbrOfDevices")), + tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")), + tDQSS (tCK * memSpec.memTimingSpec.entries.at("DQSS")), + tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")), + tRL (tCK * memSpec.memTimingSpec.entries.at("RL")), + tWL (tCK * memSpec.memTimingSpec.entries.at("WL")), + tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCPB")), + tRCab (tCK * memSpec.memTimingSpec.entries.at("RCAB")), + tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")), + tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")), + tXP (tCK * memSpec.memTimingSpec.entries.at("XP")), + tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")), + tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")), + tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")), + tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPPB")), + tRPab (tCK * memSpec.memTimingSpec.entries.at("RPAB")), + tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")), + tWR (tCK * memSpec.memTimingSpec.entries.at("WR")), + tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")), + tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")), + tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")), + tREFI (tCK * static_cast(memSpec.memTimingSpec.entries.at("REFI") + * memSpec.memTimingSpec.entries.at("REFM"))), + tREFIpb (tCK * static_cast(memSpec.memTimingSpec.entries.at("REFIPB") + * memSpec.memTimingSpec.entries.at("REFM"))), + tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCAB")), + tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")), + tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index e2fff51a..78ea7611 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -38,12 +38,11 @@ #include #include "MemSpec.h" -#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp" class MemSpecWideIO2 final : public MemSpec { public: - explicit MemSpecWideIO2(nlohmann::json &memspec); + explicit MemSpecWideIO2(const DRAMSysConfiguration::MemSpec &memSpec); // Memspec Variables: const sc_core::sc_time tDQSCK; diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index d08ea36f..7e18bf11 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -44,87 +44,35 @@ #include "../common/utils.h" #include "../configuration/Configuration.h" -using json = nlohmann::json; - -unsigned int AddressDecoder::getUnsignedAttrFromJson(json &obj, const std::string &strName) +AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addressMapping) { - if (!obj[strName].empty()) + if (addressMapping.channelBits.isValid()) { - if (obj[strName].is_number_unsigned()) - { - return obj[strName]; - } - else - { - SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is not a number.").c_str()); - return static_cast(-1); - } - } - else - { - SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is empty or not found.").c_str()); - return static_cast(-1); - } -} - -std::vector AddressDecoder::getAttrToVectorFromJson(json &obj, const std::string &strName) -{ - std::vector vParameter; - if (!obj[strName].empty()) - { - for (const auto& it : obj[strName].items()) - { - auto valor = it.value(); - if (valor.is_number_unsigned()) - vParameter.push_back(it.value()); - else - SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is not a number.").c_str()); - } - } - return vParameter; -} - -AddressDecoder::AddressDecoder(const std::string &pathToAddressMapping) -{ - json addrFile = parseJSON(pathToAddressMapping); - json mapping; - if (addrFile["CONGEN"].empty()) - SC_REPORT_FATAL("AddressDecorder", "Root node name differs from \"CONGEN\". File format not supported."); - - // Load address mapping - if (!addrFile["CONGEN"]["SOLUTION"].empty()) - { - bool foundID0 = false; - for (const auto& it : addrFile["CONGEN"]["SOLUTION"].items()) - { - if (getUnsignedAttrFromJson(it.value(), "ID") == 0) - { - foundID0 = true; - mapping = it.value(); - break; - } - } - if (!foundID0) - SC_REPORT_FATAL("AddressDecoder", "No mapping with ID 0 was found."); - } - else - mapping = addrFile["CONGEN"]; - - for (const auto& xorItem : mapping["XOR"].items()) - { - auto value = xorItem.value(); - if (!value.empty()) - vXor.emplace_back(getUnsignedAttrFromJson(value, "FIRST"), - getUnsignedAttrFromJson(value, "SECOND")); + auto channelBits = addressMapping.channelBits.getValue(); + std::copy(channelBits.begin(), channelBits.end(), std::back_inserter(vChannelBits)); } - vChannelBits = getAttrToVectorFromJson(mapping,"CHANNEL_BIT"); - vRankBits = getAttrToVectorFromJson(mapping,"RANK_BIT"); - vBankGroupBits = getAttrToVectorFromJson(mapping,"BANKGROUP_BIT"); - vBankBits = getAttrToVectorFromJson(mapping,"BANK_BIT"); - vRowBits = getAttrToVectorFromJson(mapping,"ROW_BIT"); - vColumnBits = getAttrToVectorFromJson(mapping,"COLUMN_BIT"); - vByteBits = getAttrToVectorFromJson(mapping,"BYTE_BIT"); + if (addressMapping.rankBits.isValid()) + { + auto rankBits = addressMapping.rankBits.getValue(); + std::copy(rankBits.begin(), rankBits.end(), std::back_inserter(vRankBits)); + } + + if (addressMapping.bankGroupBits.isValid()) + { + auto bankBroupBits = addressMapping.bankGroupBits.getValue(); + std::copy(bankBroupBits.begin(), bankBroupBits.end(), std::back_inserter(vBankGroupBits)); + } + + if (addressMapping.byteBits.isValid()) + { + auto byteBits = addressMapping.byteBits.getValue(); + std::copy(byteBits.begin(), byteBits.end(), std::back_inserter(vByteBits)); + } + + std::copy(addressMapping.bankBits.begin(), addressMapping.bankBits.end(), std::back_inserter(vBankBits)); + std::copy(addressMapping.rowBits.begin(), addressMapping.rowBits.end(), std::back_inserter(vRowBits)); + std::copy(addressMapping.coloumnBits.begin(), addressMapping.coloumnBits.end(), std::back_inserter(vColumnBits)); unsigned channels = std::lround(std::pow(2.0, vChannelBits.size())); unsigned ranks = std::lround(std::pow(2.0, vRankBits.size())); diff --git a/DRAMSys/library/src/simulation/AddressDecoder.h b/DRAMSys/library/src/simulation/AddressDecoder.h index 4a971469..a88bf290 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.h +++ b/DRAMSys/library/src/simulation/AddressDecoder.h @@ -40,8 +40,7 @@ #include #include - -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" +#include struct DecodedAddress { @@ -67,14 +66,11 @@ struct DecodedAddress class AddressDecoder { public: - explicit AddressDecoder(const std::string &pathToAddressMapping); + explicit AddressDecoder(const DRAMSysConfiguration::AddressMapping &addressMapping); DecodedAddress decodeAddress(uint64_t addr); void print(); private: - static std::vector getAttrToVectorFromJson(nlohmann::json &obj, const std::string &strName); - static unsigned int getUnsignedAttrFromJson(nlohmann::json &obj, const std::string &strName); - unsigned banksPerGroup; unsigned bankgroupsPerRank; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 9e973b37..7b51d18e 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -40,10 +40,12 @@ #include "AddressDecoder.h" #include "../configuration/Configuration.h" +#include + using namespace sc_core; using namespace tlm; -Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping) : +Arbiter::Arbiter(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) : sc_module(name), payloadEventQueue(this, &Arbiter::peqCallback), tCK(Configuration::getInstance().memSpec->tCK), arbitrationDelayFw(Configuration::getInstance().arbitrationDelayFw), @@ -53,21 +55,21 @@ Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMap tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw); tSocket.register_transport_dbg(this, &Arbiter::transport_dbg); - addressDecoder = new AddressDecoder(pathToAddressMapping); + addressDecoder = new AddressDecoder(addressMapping); addressDecoder->print(); bytesPerBeat = Configuration::getInstance().memSpec->dataBusWidth / 8; } -ArbiterSimple::ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping) : - Arbiter(name, pathToAddressMapping) {} +ArbiterSimple::ArbiterSimple(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) : + Arbiter(name, addressMapping) {} -ArbiterFifo::ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping) : - Arbiter(name, pathToAddressMapping), +ArbiterFifo::ArbiterFifo(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) : + Arbiter(name, addressMapping), maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {} -ArbiterReorder::ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping) : - Arbiter(name, pathToAddressMapping), +ArbiterReorder::ArbiterReorder(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) : + Arbiter(name, addressMapping), maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {} Arbiter::~Arbiter() diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 99f07323..09150b14 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -64,7 +64,7 @@ public: ~Arbiter() override; protected: - Arbiter(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); + Arbiter(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping); SC_HAS_PROCESS(Arbiter); void end_of_elaboration() override; @@ -98,7 +98,7 @@ protected: class ArbiterSimple final : public Arbiter { public: - ArbiterSimple(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); + ArbiterSimple(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping); SC_HAS_PROCESS(ArbiterSimple); private: @@ -111,7 +111,7 @@ private: class ArbiterFifo final : public Arbiter { public: - ArbiterFifo(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); + ArbiterFifo(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping); SC_HAS_PROCESS(ArbiterFifo); private: @@ -131,7 +131,7 @@ private: class ArbiterReorder final : public Arbiter { public: - ArbiterReorder(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping); + ArbiterReorder(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping); SC_HAS_PROCESS(ArbiterReorder); private: diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 796a46d1..7bf032a8 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -43,7 +43,6 @@ #include #include "DRAMSys.h" -#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp" #include "../common/DebugManager.h" #include "../common/utils.h" #include "../simulation/TemperatureController.h" @@ -63,14 +62,12 @@ #include "../controller/Controller.h" DRAMSys::DRAMSys(const sc_core::sc_module_name &name, - const std::string &simulationToRun, - const std::string &pathToResources) - : DRAMSys(name, simulationToRun, pathToResources, true) + const DRAMSysConfiguration::Configuration &config) + : DRAMSys(name, config, true) {} DRAMSys::DRAMSys(const sc_core::sc_module_name &name, - const std::string &simulationToRun, - const std::string &pathToResources, + const DRAMSysConfiguration::Configuration &config, bool initAndBind) : sc_module(name), tSocket("DRAMSys_tSocket") { @@ -79,31 +76,13 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name, logo(); - // Read Configuration Setup: - nlohmann::json simulationdoc = parseJSON(simulationToRun); - - Configuration::getInstance().setPathToResources(pathToResources); - // Load config and initialize modules - Configuration::getInstance().loadMemSpec(Configuration::getInstance(), - pathToResources - + "configs/memspecs/" - + std::string(simulationdoc["simulation"]["memspec"])); + Configuration::getInstance().loadMemSpec(Configuration::getInstance(), config.memSpec); + Configuration::loadMCConfig(Configuration::getInstance(), config.mcConfig); + Configuration::loadSimConfig(Configuration::getInstance(), config.simConfig); - Configuration::loadMCConfig(Configuration::getInstance(), - pathToResources - + "configs/mcconfigs/" - + std::string(simulationdoc["simulation"]["mcconfig"])); - - Configuration::loadSimConfig(Configuration::getInstance(), - pathToResources - + "configs/simulator/" - + std::string(simulationdoc["simulation"]["simconfig"])); - - Configuration::loadTemperatureSimConfig(Configuration::getInstance(), - pathToResources - + "configs/thermalsim/" - + std::string(simulationdoc["simulation"]["thermalconfig"])); + if (config.thermalConfig.isValid()) + Configuration::loadTemperatureSimConfig(Configuration::getInstance(), config.thermalConfig.getValue()); // Setup the debug manager: setupDebugManager(Configuration::getInstance().simulationName); @@ -111,8 +90,7 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name, if (initAndBind) { // Instantiate all internal DRAMSys modules: - std::string amconfig = simulationdoc["simulation"]["addressmapping"]; - instantiateModules(pathToResources, amconfig); + instantiateModules(config.addressMapping); // Connect all internal DRAMSys modules: bindSockets(); report(headline); @@ -174,8 +152,7 @@ void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName)) #endif } -void DRAMSys::instantiateModules(const std::string &pathToResources, - const std::string &amconfig) +void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &addressMapping) { // The first call to getInstance() creates the Temperature Controller. // The same instance will be accessed by all other modules. @@ -193,11 +170,11 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create arbiter if (config.arbiter == Configuration::Arbiter::Simple) - arbiter = new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig); + arbiter = new ArbiterSimple("arbiter", addressMapping); else if (config.arbiter == Configuration::Arbiter::Fifo) - arbiter = new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig); + arbiter = new ArbiterFifo("arbiter", addressMapping); else if (config.arbiter == Configuration::Arbiter::Reorder) - arbiter = new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig); + arbiter = new ArbiterReorder("arbiter", addressMapping); // Create controllers and DRAMs MemSpec::MemoryType memoryType = config.memSpec->memoryType; diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index cb6063c9..ebc9a412 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -40,18 +40,19 @@ #ifndef DRAMSYS_H #define DRAMSYS_H -#include - -#include #include "dram/Dram.h" #include "Arbiter.h" #include "ReorderBuffer.h" -#include -#include #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" #include "../controller/ControllerIF.h" +#include +#include +#include +#include +#include + class DRAMSys : public sc_core::sc_module { public: @@ -62,15 +63,13 @@ public: SC_HAS_PROCESS(DRAMSys); DRAMSys(const sc_core::sc_module_name &name, - const std::string &simulationToRun, - const std::string &pathToResources); + const DRAMSysConfiguration::Configuration &config); ~DRAMSys() override; protected: DRAMSys(const sc_core::sc_module_name &name, - const std::string &simulationToRun, - const std::string &pathToResources, + const DRAMSysConfiguration::Configuration &config, bool initAndBind); //TLM 2.0 Protocol Checkers @@ -97,8 +96,7 @@ protected: private: static void logo(); - void instantiateModules(const std::string &pathToResources, - const std::string &amconfig); + void instantiateModules(const DRAMSysConfiguration::AddressMapping &addressMapping); void bindSockets(); static void setupDebugManager(const std::string &traceName); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 62fbc6b1..0eeac935 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -55,27 +55,22 @@ using namespace sc_core; DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name, - const std::string &simulationToRun, - const std::string &pathToResources) - : DRAMSys(name, simulationToRun, pathToResources, false) + const DRAMSysConfiguration::Configuration &configuration) + : DRAMSys(name, configuration, false) { - // Read Configuration Setup: - nlohmann::json simulationdoc = parseJSON(simulationToRun); - // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. std::string traceName; - if (!simulationdoc["simulation"]["simulationid"].empty()) + if (!configuration.simulationId.empty()) { - std::string sid = simulationdoc["simulation"]["simulationid"]; + std::string sid = configuration.simulationId; traceName = sid + '_' + Configuration::getInstance().simulationName; } else traceName = Configuration::getInstance().simulationName; - std::string amconfig = simulationdoc["simulation"]["addressmapping"]; - instantiateModules(traceName, pathToResources, amconfig); + instantiateModules(traceName, configuration); bindSockets(); report(headline); } @@ -93,7 +88,7 @@ DRAMSysRecordable::~DRAMSysRecordable() delete rec; } -void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName) +void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const DRAMSysConfiguration::Configuration &configuration) { // Create TLM Recorders, one per channel. for (std::size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) @@ -104,8 +99,8 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName) TlmRecorder *tlmRecorder = new TlmRecorder(recorderName, dbName); - tlmRecorder->recordMcConfig(Configuration::mcconfigUri); - tlmRecorder->recordMemspec(Configuration::memspecUri); + tlmRecorder->recordMcConfig(DRAMSysConfiguration::dump(configuration.mcConfig)); + tlmRecorder->recordMemspec(DRAMSysConfiguration::dump(configuration.memSpec)); std::string traceNames = Configuration::getInstance().simulationName; tlmRecorder->recordTraceNames(traceNames); @@ -115,8 +110,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName) } void DRAMSysRecordable::instantiateModules(const std::string &traceName, - const std::string &pathToResources, - const std::string &amconfig) + const DRAMSysConfiguration::Configuration &configuration) { // The first call to getInstance() creates the Temperature Controller. // The same instance will be accessed by all other modules. @@ -126,7 +120,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create and properly initialize TLM recorders. // They need to be ready before creating some modules. - setupTlmRecorders(traceName); + setupTlmRecorders(traceName, configuration); // Create new ECC Controller if (config.eccMode == Configuration::ECCMode::Hamming) @@ -139,11 +133,11 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create arbiter if (config.arbiter == Configuration::Arbiter::Simple) - arbiter = new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig); + arbiter = new ArbiterSimple("arbiter", configuration.addressMapping); else if (config.arbiter == Configuration::Arbiter::Fifo) - arbiter = new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig); + arbiter = new ArbiterFifo("arbiter", configuration.addressMapping); else if (config.arbiter == Configuration::Arbiter::Reorder) - arbiter = new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig); + arbiter = new ArbiterReorder("arbiter", configuration.addressMapping); // Create controllers and DRAMs MemSpec::MemoryType memoryType = config.memSpec->memoryType; diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.h b/DRAMSys/library/src/simulation/DRAMSysRecordable.h index 876b3d6f..570fa50d 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.h +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.h @@ -39,12 +39,13 @@ #include "DRAMSys.h" #include "../common/TlmRecorder.h" +#include + class DRAMSysRecordable : public DRAMSys { public: DRAMSysRecordable(const sc_core::sc_module_name &name, - const std::string &simulationToRun, - const std::string &pathToResources); + const DRAMSysConfiguration::Configuration &configuration); ~DRAMSysRecordable() override; @@ -53,11 +54,10 @@ private: // They generate the output databases. std::vector tlmRecorders; - void setupTlmRecorders(const std::string &traceName); + void setupTlmRecorders(const std::string &traceName, const DRAMSysConfiguration::Configuration &configuration); void instantiateModules(const std::string &traceName, - const std::string &pathToResources, - const std::string &amconfig); + const DRAMSysConfiguration::Configuration &configuration); void bindSockets(); }; diff --git a/DRAMSys/library/src/simulation/TemperatureController.cpp b/DRAMSys/library/src/simulation/TemperatureController.cpp index 3aa92634..3634663f 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.cpp +++ b/DRAMSys/library/src/simulation/TemperatureController.cpp @@ -43,9 +43,9 @@ using namespace sc_core; double TemperatureController::temperatureConvert(double tKelvin) { - if (temperatureScale == "Celsius") { + if (temperatureScale == TemperatureSimConfig::TemperatureScale::Celsius) { return tKelvin - 273.15; - } else if (temperatureScale == "Fahrenheit") { + } else if (temperatureScale == TemperatureSimConfig::TemperatureScale::Fahrenheit) { return (tKelvin - 273.15) * 1.8 + 32; } diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index ac5e96e4..8ad01896 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -115,7 +115,7 @@ public: double getTemperature(int deviceId, float currentPower); private: - std::string temperatureScale; + TemperatureSimConfig::TemperatureScale temperatureScale; double temperatureConvert(double tKelvin); double staticTemperature; diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 829473f1..2ec971ef 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -43,186 +43,128 @@ using namespace sc_core; using namespace tlm; -TraceSetup::TraceSetup(const std::string &uri, +TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, const std::string &pathToResources, std::vector &players) { - // Load Simulation: - nlohmann::json simulationdoc = parseJSON(uri); + if (traceSetup.initiators.empty()) + SC_REPORT_FATAL("TraceSetup", "No traffic initiators specified"); - if (simulationdoc["simulation"].empty()) - SC_REPORT_FATAL("TraceSetup", - "Cannot load simulation: simulation node expected"); - - // Load TrafficInitiators: - if (simulationdoc["simulation"]["tracesetup"].empty()) - SC_REPORT_FATAL("TraceSetup", "tracesetup is empty"); - for (auto &it : simulationdoc["simulation"]["tracesetup"].items()) + for (const auto &inititator : traceSetup.initiators) { - nlohmann::json value = it.value(); - if (!value.empty()) - { - sc_time playerClk; - if (!value["clkMhz"].is_number() || value["clkMhz"] <= 0) - SC_REPORT_FATAL("TraceSetup", "Frequency is not a positive number."); + double frequencyMHz = inititator->clkMhz; + sc_time playerClk = sc_time(1.0 / frequencyMHz, SC_US); - double frequencyMHz = value["clkMhz"]; - playerClk = sc_time(1.0 / frequencyMHz, SC_US); + std::string name = inititator->name; - if (!value["name"].is_string()) - SC_REPORT_FATAL("TraceSetup", "No trace name defined."); - - std::string name = value["name"]; - - unsigned int maxPendingReadRequests = 0; - unsigned int maxPendingWriteRequests = 0; - - if (value["maxPendingReadRequests"].is_number_unsigned()) - maxPendingReadRequests = value["maxPendingReadRequests"]; - - if (value["maxPendingWriteRequests"].is_number_unsigned()) - maxPendingWriteRequests = value["maxPendingWriteRequests"]; - - std::string type; - - // Defaulting to type "player" when not specified - if (!value["type"].is_string()) - type = "player"; + unsigned int maxPendingReadRequests = [=]() -> unsigned int { + if (inititator->maxPendingReadRequests.isValid()) + return inititator->maxPendingReadRequests.getValue(); else - type = value["type"]; + return 0; + }(); - if (type == "player") - { - size_t pos = name.rfind('.'); - if (pos == std::string::npos) - throw std::runtime_error("Name of the trace file does not contain a valid extension."); + unsigned int maxPendingWriteRequests = [=]() -> unsigned int { + if (inititator->maxPendingWriteRequests.isValid()) + return inititator->maxPendingWriteRequests.getValue(); + else + return 0; + }(); - // Get the extension and make it lower case - std::string ext = name.substr(pos + 1); - std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); + if (std::dynamic_pointer_cast(inititator)) + { + size_t pos = name.rfind('.'); + if (pos == std::string::npos) + throw std::runtime_error("Name of the trace file does not contain a valid extension."); - std::stringstream stlFileStream; - stlFileStream << pathToResources << "traces/" << name; - std::string stlFile = stlFileStream.str(); - std::string moduleName = name; + // Get the extension and make it lower case + std::string ext = name.substr(pos + 1); + std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); - // replace all '.' to '_' - std::replace(moduleName.begin(), moduleName.end(), '.', '_'); + std::stringstream stlFileStream; + stlFileStream << pathToResources << "traces/" << name; + std::string stlFile = stlFileStream.str(); + std::string moduleName = name; - StlPlayer *player; - if (ext == "stl") - player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, - maxPendingReadRequests, maxPendingWriteRequests, this, false); - else if (ext == "rstl") - player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, - maxPendingReadRequests, maxPendingWriteRequests, this, true); - else - throw std::runtime_error("Unsupported file extension in " + name); + // replace all '.' to '_' + std::replace(moduleName.begin(), moduleName.end(), '.', '_'); - players.push_back(player); + StlPlayer *player; + if (ext == "stl") + player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, + maxPendingReadRequests, maxPendingWriteRequests, this, false); + else if (ext == "rstl") + player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, + maxPendingReadRequests, maxPendingWriteRequests, this, true); + else + throw std::runtime_error("Unsupported file extension in " + name); - totalTransactions += player->getNumberOfLines(); - } - else if (type == "generator") - { - if (!value["numRequests"].is_number_unsigned()) - SC_REPORT_FATAL("TraceSetup", "Number of requests is not a number."); - - uint64_t numRequests = value["numRequests"]; - - if (!value["rwRatio"].is_number() || value["rwRatio"] < 0 || value["rwRatio"] > 1) - SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); - - float rwRatio = value["rwRatio"]; - - if (!value["addressDistribution"].is_string()) - SC_REPORT_FATAL("TraceSetup", "Address distribution not defined."); - - std::string addressDistribution = value["addressDistribution"]; - if (addressDistribution != "sequential" && addressDistribution != "random") - SC_REPORT_FATAL("TraceSetup", "Address distribution must either be sequential or random."); - - unsigned int seed = 0; - if (!value["seed"].empty()) - { - if (value["seed"].is_number_unsigned()) - seed = value["seed"]; - else - SC_REPORT_FATAL("TraceSetup", "Seed is not an unsigned number."); - } - - uint64_t minAddress = 0; - if (!value["minAddress"].empty()) - { - if (value["minAddress"].is_number_unsigned()) - { - minAddress = value["minAddress"]; - if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) - SC_REPORT_FATAL("TraceSetup", "minAddress is out of range."); - } - else - SC_REPORT_FATAL("TraceSetup", "minAddress is not an unsigned number."); - } - - uint64_t maxAddress = Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; - if (!value["maxAddress"].empty()) - { - if (value["maxAddress"].is_number_unsigned()) - { - maxAddress = value["maxAddress"]; - if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) - SC_REPORT_FATAL("TraceSetup", "maxAddress is out of range."); - } - else - SC_REPORT_FATAL("TraceSetup", "maxAddress is not an unsigned number."); - } - - if (maxAddress < minAddress) - SC_REPORT_FATAL("TraceSetup", "maxAddress is smaller than minAddress."); - - TrafficInitiator* generator; - - if (addressDistribution == "sequential") - { - uint64_t addressIncrement = 0x0; - if (!value["addressIncrement"].is_number_unsigned()) - SC_REPORT_FATAL("TraceSetup", "Address increment is not an unsigned number."); - else - addressIncrement = value["addressIncrement"]; - - generator = new TrafficGeneratorSequential(name.c_str(), playerClk, numRequests, - maxPendingReadRequests, maxPendingWriteRequests, - minAddress, maxAddress, rwRatio, addressIncrement, seed, - this); - } - else - { - generator = new TrafficGeneratorRandom(name.c_str(), playerClk, numRequests, - maxPendingReadRequests, maxPendingWriteRequests, - minAddress, maxAddress, rwRatio, seed, this); - } - - players.push_back(generator); - - totalTransactions += numRequests; - } - else if (type == "hammer") - { - if (!value["numRequests"].is_number_unsigned()) - SC_REPORT_FATAL("TraceSetup", "Number of requests is not a number."); - uint64_t numRequests = value["numRequests"]; - - if (!value["rowIncrement"].is_number_unsigned()) - SC_REPORT_FATAL("TraceSetup", "Row increment is not a number."); - uint64_t rowIncrement = value["rowIncrement"]; - - TrafficInitiator* generator = new TrafficGeneratorHammer(name.c_str(), playerClk, numRequests, - rowIncrement, this); - players.push_back(generator); - } + players.push_back(player); + totalTransactions += player->getNumberOfLines(); + } + else if (auto generator = std::dynamic_pointer_cast(inititator)) + { + uint64_t numRequests = generator->numRequests; + double rwRatio = generator->rwRatio; + + if (rwRatio < 0 || rwRatio > 1) + SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); + + uint64_t minAddress = [=]() -> uint64_t { + if (generator->minAddress.isValid()) + return generator->minAddress.getValue(); + else + return 0; + }(); + + uint64_t maxAddress = [=]() -> uint64_t { + if (generator->maxAddress.isValid()) + return generator->maxAddress.getValue(); + else + return 0; + }(); + + if (maxAddress < minAddress) + SC_REPORT_FATAL("TraceSetup", "maxAddress is smaller than minAddress."); + + unsigned int seed = [=]() -> unsigned int { + if (generator->seed.isValid()) + return generator->seed.getValue(); + else + return 0; + }(); + + if (generator->addressDistribution == DRAMSysConfiguration::AddressDistribution::Sequential) + { + uint64_t addressIncrement = [=]() -> uint64_t { + if (generator->addressIncrement.isValid()) + return generator->addressIncrement.getValue(); + else + return 0x0; + }(); + + players.push_back(new TrafficGeneratorSequential(name.c_str(), playerClk, numRequests, + maxPendingReadRequests, maxPendingWriteRequests, + minAddress, maxAddress, rwRatio, addressIncrement, seed, + this)); + } + else if (generator->addressDistribution == DRAMSysConfiguration::AddressDistribution::Random) + { + players.push_back(new TrafficGeneratorRandom(name.c_str(), playerClk, numRequests, + maxPendingReadRequests, maxPendingWriteRequests, + minAddress, maxAddress, rwRatio, seed, this)); + } + + totalTransactions += numRequests; + } + else if (auto hammer = std::dynamic_pointer_cast(inititator)) + { + uint64_t numRequests = hammer->numRequests; + uint64_t rowIncrement = hammer->rowIncrement; + + players.push_back(new TrafficGeneratorHammer(name.c_str(), playerClk, numRequests, + rowIncrement, this)); } - else - SC_REPORT_FATAL("TraceSetup", "Empty trace setup item."); } remainingTransactions = totalTransactions; diff --git a/DRAMSys/simulator/TraceSetup.h b/DRAMSys/simulator/TraceSetup.h index b5ad6435..4ff6e138 100644 --- a/DRAMSys/simulator/TraceSetup.h +++ b/DRAMSys/simulator/TraceSetup.h @@ -39,8 +39,9 @@ #include #include - +#include #include + #include "MemoryManager.h" class TrafficInitiator; @@ -48,7 +49,7 @@ class TrafficInitiator; class TraceSetup { public: - TraceSetup(const std::string &uri, + TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, const std::string &pathToResources, std::vector &devices); diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 6671baaf..b5e0c900 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -41,15 +41,15 @@ #include #include #include - +#include #include + #include "simulation/DRAMSys.h" #include "TraceSetup.h" #include "TrafficInitiator.h" #ifdef RECORDING #include "simulation/DRAMSysRecordable.h" -#include "common/third_party/nlohmann/single_include/nlohmann/json.hpp" using json = nlohmann::json; #endif @@ -97,21 +97,23 @@ int sc_main(int argc, char **argv) std::vector players; + DRAMSysConfiguration::Configuration conf = DRAMSysConfiguration::from_path(simulationJson, resources); + // Instantiate DRAMSys: DRAMSys *dramSys; -#ifdef RECORDING - json simulationdoc = parseJSON(simulationJson); - json simulatordoc = parseJSON(resources + "configs/simulator/" - + std::string(simulationdoc["simulation"]["simconfig"])); - if (simulatordoc["simconfig"]["DatabaseRecording"]) - dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources); +#ifdef RECORDING + if (conf.simConfig.databaseRecording.isValid() && conf.simConfig.databaseRecording.getValue()) + dramSys = new DRAMSysRecordable("DRAMSys", conf); else #endif - dramSys = new DRAMSys("DRAMSys", simulationJson, resources); + dramSys = new DRAMSys("DRAMSys", conf); + + if (!conf.traceSetup.isValid()) + SC_REPORT_FATAL("sc_main", "No tracesetup section provided."); // Instantiate STL Players: - TraceSetup *setup = new TraceSetup(simulationJson, resources, players); + TraceSetup *setup = new TraceSetup(conf.traceSetup.getValue(), resources, players); // Bind STL Players with DRAMSys: for (size_t i = 0; i < players.size(); i++) From 7d21f3befe4178815a97c56268aeed94ca1ef99d Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 4 Nov 2021 12:08:23 +0100 Subject: [PATCH 05/23] Add a converter for the new json format --- .../common/configuration/AddressMapping.cpp | 2 + .../src/common/configuration/McConfig.cpp | 4 +- .../common/configuration/memspec/MemSpec.cpp | 4 +- .../common/configuration/tests/CMakeLists.txt | 3 + .../common/configuration/tests/converter.cpp | 58 +++++++++++++++++++ .../common/configuration/tests/simpletest.cpp | 35 +++++++++++ 6 files changed, 104 insertions(+), 2 deletions(-) create mode 100644 DRAMSys/library/src/common/configuration/tests/converter.cpp diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp index 1d865804..8ab105c0 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.cpp +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -55,6 +55,8 @@ void to_json(json &j, const AddressMapping &m) {"RANK_BIT", m.rankBits}, {"XOR", m.xorBits}}; + remove_null_values(congen); + j["CONGEN"] = congen; } diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp index 86648204..4a28278c 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.cpp +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -113,7 +113,9 @@ void from_json(const json &j, McConfig &c) std::string dump(const McConfig &c) { - return json{c}.dump(); + json json_mcconfig; + json_mcconfig["mcconfig"] = c; + return json_mcconfig.dump(); } } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp index 9e433c89..7453b42a 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp @@ -64,7 +64,9 @@ void from_json(const json &j, MemSpec &c) std::string dump(const MemSpec &c) { - return json{c}.dump(); + json json_memspec; + json_memspec["memspec"] = c; + return json_memspec.dump(); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt b/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt index 0b9890b0..621a7230 100644 --- a/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt +++ b/DRAMSys/library/src/common/configuration/tests/CMakeLists.txt @@ -1,2 +1,5 @@ add_executable(simpletest simpletest.cpp) target_link_libraries(simpletest PRIVATE DRAMSysConfiguration nlohmann_json::nlohmann_json) + +add_executable(converter converter.cpp) +target_link_libraries(converter PRIVATE DRAMSysConfiguration nlohmann_json::nlohmann_json) diff --git a/DRAMSys/library/src/common/configuration/tests/converter.cpp b/DRAMSys/library/src/common/configuration/tests/converter.cpp new file mode 100644 index 00000000..08516eb5 --- /dev/null +++ b/DRAMSys/library/src/common/configuration/tests/converter.cpp @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include +#include +#include +#include + +int main(int argc, char **argv) +{ + if (argc != 2) + { + std::cerr << "Must specify a simulation json as single argument.\n"; + return -1; + } + + std::string pathToJson = argv[1]; + auto configuration = DRAMSysConfiguration::from_path(pathToJson); + nlohmann::json json; + json["simulation"] = configuration; + + std::ofstream output(pathToJson + "_converted.json"); + output << json.dump(4); + + return 0; +} diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 07d259c5..221b062c 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -1,3 +1,38 @@ +/* + * Copyright (c) 2021, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + #include #include #include From 3d0e321075c4456f42d5382dd2acbb8ff0a683dd Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 5 Nov 2021 09:35:25 +0100 Subject: [PATCH 06/23] Introduce a gui simulation dialog in TraceAnalyzer A simulation dialog is added to the TraceAnalyzer that can be used to directly load a json config, edit it and start a simulation based on the changes that were made, even without saving again. The simulation results are opened directly after suceeding. --- .../common/configuration/AddressMapping.cpp | 13 + .../src/common/configuration/AddressMapping.h | 3 + .../common/configuration/Configuration.cpp | 13 + .../src/common/configuration/Configuration.h | 3 + .../src/common/configuration/McConfig.cpp | 36 +- .../src/common/configuration/McConfig.h | 17 +- .../src/common/configuration/SimConfig.cpp | 13 + .../src/common/configuration/SimConfig.h | 3 + .../common/configuration/ThermalConfig.cpp | 13 + .../src/common/configuration/ThermalConfig.h | 3 + .../src/common/configuration/TraceSetup.cpp | 13 + .../src/common/configuration/TraceSetup.h | 3 + .../common/configuration/memspec/MemSpec.cpp | 10 +- .../common/configuration/memspec/MemSpec.h | 3 +- .../library/src/common/configuration/util.h | 10 + .../src/configuration/Configuration.cpp | 247 ++---------- DRAMSys/library/src/simulation/DRAMSys.cpp | 3 +- DRAMSys/traceAnalyzer/CMakeLists.txt | 3 + DRAMSys/traceAnalyzer/simulationdialog.cpp | 377 ++++++++++++++++++ DRAMSys/traceAnalyzer/simulationdialog.h | 100 +++++ DRAMSys/traceAnalyzer/simulationdialog.ui | 345 ++++++++++++++++ DRAMSys/traceAnalyzer/traceanalyzer.cpp | 12 + DRAMSys/traceAnalyzer/traceanalyzer.h | 1 + DRAMSys/traceAnalyzer/traceanalyzer.ui | 15 + 24 files changed, 1041 insertions(+), 218 deletions(-) create mode 100644 DRAMSys/traceAnalyzer/simulationdialog.cpp create mode 100644 DRAMSys/traceAnalyzer/simulationdialog.h create mode 100644 DRAMSys/traceAnalyzer/simulationdialog.ui diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp index 8ab105c0..c3a57881 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.cpp +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -101,4 +101,17 @@ void from_json(const json &j, XorPair &x) j.at("SECOND").get_to(x.second); } +void from_dump(const std::string &dump, AddressMapping &c) +{ + json json_addressmapping = json::parse(dump).at("addressmapping"); + json_addressmapping.get_to(c); +} + +std::string dump(const AddressMapping &c, unsigned int indentation) +{ + json json_addressmapping; + json_addressmapping["addressmapping"] = c; + return json_addressmapping.dump(indentation); +} + } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index a0ab60ff..28a6c097 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -71,6 +71,9 @@ struct AddressMapping void to_json(json &j, const AddressMapping &m); void from_json(const json &j, AddressMapping &m); +void from_dump(const std::string &dump, AddressMapping &c); +std::string dump(const AddressMapping &c, unsigned int indentation = -1); + } // namespace Configuration #endif // ADDRESSMAPPING_H diff --git a/DRAMSys/library/src/common/configuration/Configuration.cpp b/DRAMSys/library/src/common/configuration/Configuration.cpp index f2dd99eb..ed331aaf 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.cpp +++ b/DRAMSys/library/src/common/configuration/Configuration.cpp @@ -67,6 +67,19 @@ void from_json(const json &j, Configuration &c) j.at("tracesetup").get_to(c.traceSetup); } +void from_dump(const std::string &dump, Configuration &c) +{ + json json_simulation = json::parse(dump).at("simulation"); + json_simulation.get_to(c); +} + +std::string dump(const Configuration &c, unsigned int indentation) +{ + json json_simulation; + json_simulation["simulation"] = c; + return json_simulation.dump(indentation); +} + Configuration from_path(const std::string &path, const std::string &resourceDirectory) { Configuration::resourceDirectory = resourceDirectory; diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h index c5588c2a..7bbca42d 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.h +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -78,6 +78,9 @@ struct Configuration void to_json(json &j, const Configuration &p); void from_json(const json &j, Configuration &p); +void from_dump(const std::string &dump, Configuration &c); +std::string dump(const Configuration &c, unsigned int indentation = -1); + Configuration from_path(const std::string &path, const std::string &resourceDirectory = DRAMSysResourceDirectory); } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp index 4a28278c..945388d0 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.cpp +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -52,7 +52,13 @@ void to_json(json &j, const McConfig &c) {"PowerDownPolicy", c.powerDownPolicy}, {"Arbiter", c.arbiter}, {"MaxActiveTransactions", c.maxActiveTransactions}, - {"RefreshManagment", c.refreshManagement}}; + {"RefreshManagment", c.refreshManagement}, + {"ArbitrationDelayFw", c.arbitrationDelayFw}, + {"ArbitrationDelayBw", c.arbitrationDelayBw}, + {"ThinkDelayFw", c.thinkDelayFw}, + {"ThinkDelayBw", c.thinkDelayBw}, + {"PhyDelayFw", c.phyDelayFw}, + {"PhyDelayBw", c.phyDelayBw}}; remove_null_values(j); } @@ -100,6 +106,24 @@ void from_json(const json &j, McConfig &c) if (j_mcconfig.contains("RefreshManagment")) j_mcconfig.at("RefreshManagment").get_to(c.refreshManagement); + if (j_mcconfig.contains("ArbitrationDelayFw")) + j_mcconfig.at("ArbitrationDelayFw").get_to(c.arbitrationDelayFw); + + if (j_mcconfig.contains("ArbitrationDelayBw")) + j_mcconfig.at("ArbitrationDelayBw").get_to(c.arbitrationDelayBw); + + if (j_mcconfig.contains("ThinkDelayFw")) + j_mcconfig.at("ThinkDelayFw").get_to(c.thinkDelayFw); + + if (j_mcconfig.contains("ThinkDelayBw")) + j_mcconfig.at("ThinkDelayBw").get_to(c.thinkDelayBw); + + if (j_mcconfig.contains("PhyDelayFw")) + j_mcconfig.at("PhyDelayFw").get_to(c.phyDelayFw); + + if (j_mcconfig.contains("PhyDelayBw")) + j_mcconfig.at("PhyDelayBw").get_to(c.phyDelayBw); + invalidateEnum(c.pagePolicy); invalidateEnum(c.scheduler); invalidateEnum(c.schedulerBuffer); @@ -111,11 +135,17 @@ void from_json(const json &j, McConfig &c) invalidateEnum(c.arbiter); } -std::string dump(const McConfig &c) +void from_dump(const std::string &dump, McConfig &c) +{ + json json_mcconfig = json::parse(dump).at("mcconfig"); + json_mcconfig.get_to(c); +} + +std::string dump(const McConfig &c, unsigned int indentation) { json json_mcconfig; json_mcconfig["mcconfig"] = c; - return json_mcconfig.dump(); + return json_mcconfig.dump(indentation); } } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index 701b5d09..abc7bcd0 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -119,14 +119,20 @@ enum class RefreshPolicy PerBank, Per2Bank, SameBank, + Rankwise, + Bankwise, + Groupwise, Invalid = -1 }; NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicy, {{RefreshPolicy::Invalid, nullptr}, + {RefreshPolicy::NoRefresh, "NoRefresh"}, {RefreshPolicy::AllBank, "AllBank"}, {RefreshPolicy::PerBank, "PerBank"}, {RefreshPolicy::Per2Bank, "Per2Bank"}, - {RefreshPolicy::SameBank, "SameBank"}}) + {RefreshPolicy::Rankwise, "Rankwise"}, + {RefreshPolicy::Bankwise, "Bankwise"}, + {RefreshPolicy::Groupwise, "Groupwise"}}) enum class PowerDownPolicy { @@ -167,12 +173,19 @@ struct McConfig Optional arbiter; Optional maxActiveTransactions; Optional refreshManagement; + Optional arbitrationDelayFw; + Optional arbitrationDelayBw; + Optional thinkDelayFw; + Optional thinkDelayBw; + Optional phyDelayFw; + Optional phyDelayBw; }; void to_json(json &j, const McConfig &c); void from_json(const json &j, McConfig &c); -std::string dump(const McConfig &c); +void from_dump(const std::string &dump, McConfig &c); +std::string dump(const McConfig &c, unsigned int indentation = -1); } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/SimConfig.cpp b/DRAMSys/library/src/common/configuration/SimConfig.cpp index 34cc41ef..3459e64c 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.cpp +++ b/DRAMSys/library/src/common/configuration/SimConfig.cpp @@ -110,4 +110,17 @@ void from_json(const json &j, SimConfig &c) invalidateEnum(c.storeMode); } +void from_dump(const std::string &dump, SimConfig &c) +{ + json json_simconfig = json::parse(dump).at("simconfig"); + json_simconfig.get_to(c); +} + +std::string dump(const SimConfig &c, unsigned int indentation) +{ + json json_simconfig; + json_simconfig["simconfig"] = c; + return json_simconfig.dump(indentation); +} + } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/SimConfig.h b/DRAMSys/library/src/common/configuration/SimConfig.h index d0ca2fa5..f9bbbedd 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.h +++ b/DRAMSys/library/src/common/configuration/SimConfig.h @@ -92,6 +92,9 @@ struct SimConfig void to_json(json &j, const SimConfig &c); void from_json(const json &j, SimConfig &c); +void from_dump(const std::string &dump, SimConfig &c); +std::string dump(const SimConfig &c, unsigned int indentation = -1); + } // namespace Configuration #endif diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp index b6305269..fdcbd0e2 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp @@ -105,4 +105,17 @@ void from_json(const json &j, PowerInfo &c) } } +void from_dump(const std::string &dump, ThermalConfig &c) +{ + json json_thermalconfig = json::parse(dump).at("thermalconfig"); + json_thermalconfig.get_to(c); +} + +std::string dump(const ThermalConfig &c, unsigned int indentation) +{ + json json_thermalconfig; + json_thermalconfig["thermalconfig"] = c; + return json_thermalconfig.dump(indentation); +} + } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.h b/DRAMSys/library/src/common/configuration/ThermalConfig.h index 1bb063ce..44497346 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.h +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.h @@ -112,6 +112,9 @@ struct ThermalConfig void to_json(json &j, const ThermalConfig &c); void from_json(const json &j, ThermalConfig &c); +void from_dump(const std::string &dump, ThermalConfig &c); +std::string dump(const ThermalConfig &c, unsigned int indentation = -1); + } // namespace Configuration #endif // THERMALCONFIG_H diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index ce9a98fc..f2dd330e 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -136,4 +136,17 @@ void from_json(const json &j, TraceSetup &c) } } +void from_dump(const std::string &dump, TraceSetup &c) +{ + json json_tracesetup = json::parse(dump).at("tracesetup"); + json_tracesetup.get_to(c); +} + +std::string dump(const TraceSetup &c, unsigned int indentation) +{ + json json_tracesetup; + json_tracesetup["tracesetup"] = c; + return json_tracesetup.dump(indentation); +} + } // namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index f8062b2e..2a84bd61 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -109,6 +109,9 @@ struct TraceSetup void to_json(json &j, const TraceSetup &c); void from_json(const json &j, TraceSetup &c); +void from_dump(const std::string &dump, TraceSetup &c); +std::string dump(const TraceSetup &c, unsigned int indentation = -1); + } // namespace Configuration #endif diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp index 7453b42a..cc5dee89 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.cpp @@ -62,11 +62,17 @@ void from_json(const json &j, MemSpec &c) j_memspecs.at("mempowerspec").get_to(c.memPowerSpec); } -std::string dump(const MemSpec &c) +void from_dump(const std::string &dump, MemSpec &c) +{ + json json_memspec = json::parse(dump).at("memspec"); + json_memspec.get_to(c); +} + +std::string dump(const MemSpec &c, unsigned int indentation) { json json_memspec; json_memspec["memspec"] = c; - return json_memspec.dump(); + return json_memspec.dump(indentation); } } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h index 0fde0fa8..66c0a317 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h @@ -61,7 +61,8 @@ struct MemSpec void to_json(json &j, const MemSpec &c); void from_json(const json &j, MemSpec &c); -std::string dump(const MemSpec &c); +void from_dump(const std::string &dump, MemSpec &c); +std::string dump(const MemSpec &c, unsigned int indentation = -1); } // namespace Configuration diff --git a/DRAMSys/library/src/common/configuration/util.h b/DRAMSys/library/src/common/configuration/util.h index c6090fa3..5d61f9a7 100644 --- a/DRAMSys/library/src/common/configuration/util.h +++ b/DRAMSys/library/src/common/configuration/util.h @@ -75,6 +75,16 @@ public: { this->second = false; } + + /** + * This methods only purpose is to make a optional type + * valid so that it can be written to by reference. + */ + T &setByReference() + { + this->second = true; + return this->first; + } }; template diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index ac9614d3..4a003206 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -77,212 +77,6 @@ enum sc_time_unit string2TimeUnit(const std::string &s) } } -// void Configuration::setParameter(const std::string &name, const nlohmann::json &value) -// { -// MCConfig -// if (name == "PagePolicy") -// { -// if (value == "Open") -// pagePolicy = PagePolicy::Open; -// else if (value == "Closed") -// pagePolicy = PagePolicy::Closed; -// else if (value == "OpenAdaptive") -// pagePolicy = PagePolicy::OpenAdaptive; -// else if (value == "ClosedAdaptive") -// pagePolicy = PagePolicy::ClosedAdaptive; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported page policy!"); -// } -// else if (name == "Scheduler") -// { -// if (value == "Fifo") -// scheduler = Scheduler::Fifo; -// else if (value == "FrFcfs") -// scheduler = Scheduler::FrFcfs; -// else if (value == "FrFcfsGrp") -// scheduler = Scheduler::FrFcfsGrp; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported scheduler!"); -// } -// else if (name == "SchedulerBuffer") -// { -// if (value == "Bankwise") -// schedulerBuffer = SchedulerBuffer::Bankwise; -// else if (value == "ReadWrite") -// schedulerBuffer = SchedulerBuffer::ReadWrite; -// else if (value == "Shared") -// schedulerBuffer = SchedulerBuffer::Shared; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported scheduler buffer!"); -// } -// else if (name == "RequestBufferSize") -// { -// requestBufferSize = value; -// if (requestBufferSize == 0) -// SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); -// } -// else if (name == "CmdMux") -// { -// if (value == "Oldest") -// cmdMux = CmdMux::Oldest; -// else if (value == "Strict") -// cmdMux = CmdMux::Strict; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported cmd mux!"); -// } -// else if (name == "RespQueue") -// { -// if (value == "Fifo") -// respQueue = RespQueue::Fifo; -// else if (value == "Reorder") -// respQueue = RespQueue::Reorder; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported response queue!"); -// } -// else if (name == "Arbiter") -// { -// if (value == "Simple") -// arbiter = Arbiter::Simple; -// else if (value == "Fifo") -// arbiter = Arbiter::Fifo; -// else if (value == "Reorder") -// arbiter = Arbiter::Reorder; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported arbiter!"); -// } -// else if (name == "RefreshPolicy") -// { -// if (value == "NoRefresh") -// refreshPolicy = RefreshPolicy::NoRefresh; -// else if (value == "AllBank" || value == "Rankwise") -// refreshPolicy = RefreshPolicy::AllBank; -// else if (value == "PerBank" || value == "Bankwise") -// refreshPolicy = RefreshPolicy::PerBank; -// else if (value == "SameBank" || value == "Groupwise") -// refreshPolicy = RefreshPolicy::SameBank; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported refresh policy!"); -// } -// else if (name == "RefreshMaxPostponed") -// refreshMaxPostponed = value; -// else if (name == "RefreshMaxPulledin") -// refreshMaxPulledin = value; -// else if (name == "PowerDownPolicy") -// { -// if (value == "NoPowerDown") -// powerDownPolicy = PowerDownPolicy::NoPowerDown; -// else if (value == "Staggered") -// powerDownPolicy = PowerDownPolicy::Staggered; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported power down policy!"); -// } -// else if (name == "RefreshManagement") -// refreshManagement = value; -// else if (name == "PowerDownTimeout") -// powerDownTimeout = value; -// else if (name == "MaxActiveTransactions") -// maxActiveTransactions = value; -// else if (name == "ArbitrationDelayFw") -// arbitrationDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; -// else if (name == "ArbitrationDelayBw") -// arbitrationDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; -// else if (name == "ThinkDelayFw") -// thinkDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; -// else if (name == "ThinkDelayBw") -// thinkDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; -// else if (name == "PhyDelayFw") -// phyDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; -// else if (name == "PhyDelayBw") -// phyDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK; -// SimConfig------------------------------------------------ -// else if (name == "SimulationName") -// simulationName = value; -// else if (name == "DatabaseRecording") -// databaseRecording = value; -// else if (name == "PowerAnalysis") -// powerAnalysis = value; -// else if (name == "EnableWindowing") -// enableWindowing = value; -// else if (name == "WindowSize") -// { -// windowSize = value; -// if (windowSize == 0) -// SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); -// } -// else if (name == "Debug") -// debug = value; -// else if (name == "ThermalSimulation") -// thermalSimulation = value; -// else if (name == "SimulationProgressBar") -// simulationProgressBar = value; -// else if (name == "AddressOffset") -// addressOffset = value; -// else if (name == "UseMalloc") -// useMalloc = value; -// else if (name == "CheckTLM2Protocol") -// checkTLM2Protocol = value; -// else if (name == "ECCControllerMode") -// { -// if (value == "Disabled") -// eccMode = ECCMode::Disabled; -// else if (value == "Hamming") -// eccMode = ECCMode::Hamming; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported ECC mode!"); -// } -// Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode -// else if (name == "ErrorChipSeed") -// errorChipSeed = value; -// else if (name == "ErrorCSVFile") -// errorCSVFile = value; -// else if (name == "StoreMode") -// { -// if (value == "NoStorage") -// storeMode = StoreMode::NoStorage; -// else if (value == "Store") -// storeMode = StoreMode::Store; -// else if (value == "ErrorModel") -// storeMode = StoreMode::ErrorModel; -// else -// SC_REPORT_FATAL("Configuration", "Unsupported store mode!"); -// } -// -// Temperature Simulation related -// else if (name == "TemperatureScale") -// { -// if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") -// SC_REPORT_FATAL("Configuration", -// ("Invalid value for parameter " + name + ".").c_str()); -// temperatureSim.temperatureScale = value; -// } -// else if (name == "StaticTemperatureDefaultValue") -// temperatureSim.staticTemperatureDefaultValue = value; -// else if (name == "ThermalSimPeriod") -// temperatureSim.thermalSimPeriod = value; -// else if (name == "ThermalSimUnit") -// temperatureSim.thermalSimUnit = string2TimeUnit(value); -// else if (name == "PowerInfoFile") -// { -// temperatureSim.powerInfoFile = value; -// temperatureSim.parsePowerInfoFile(); -// } -// else if (name == "IceServerIp") -// temperatureSim.iceServerIp = value; -// else if (name == "IceServerPort") -// temperatureSim.iceServerPort = value; -// else if (name == "SimPeriodAdjustFactor") -// temperatureSim.simPeriodAdjustFactor = value; -// else if (name == "NPowStableCyclesToIncreasePeriod") -// temperatureSim.nPowStableCyclesToIncreasePeriod = value; -// else if (name == "GenerateTemperatureMap") -// temperatureSim.generateTemperatureMap = value; -// else if (name == "GeneratePowerMap") -// temperatureSim.generatePowerMap = value; -// else -// SC_REPORT_FATAL("Configuration", -// ("Parameter " + name + " not defined in Configuration").c_str()); -// } - // Changes the number of bytes depeding on the ECC Controller. This function is needed for modules which get data directly or indirectly from the ECC Controller unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const { @@ -343,6 +137,8 @@ void Configuration::loadSimConfig(Configuration &config, const DRAMSysConfigurat if (simConfig.windowSize.isValid()) config.windowSize = simConfig.windowSize.getValue(); + if (config.windowSize == 0) + SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); if (simConfig.errorCsvFile.isValid()) config.errorCSVFile = simConfig.errorCsvFile.getValue(); @@ -451,6 +247,9 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati if (mcConfig.requestBufferSize.isValid()) config.requestBufferSize = mcConfig.requestBufferSize.getValue(); + if (config.requestBufferSize == 0) + SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); + if (mcConfig.cmdMux.isValid()) config.cmdMux = [=] { auto cmdMux = mcConfig.cmdMux.getValue(); @@ -477,13 +276,13 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati if (policy == DRAMSysConfiguration::RefreshPolicy::NoRefresh) return RefreshPolicy::NoRefresh; - else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank) + else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank || policy == DRAMSysConfiguration::RefreshPolicy::Rankwise) return RefreshPolicy::AllBank; - else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank) + else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank || policy == DRAMSysConfiguration::RefreshPolicy::Bankwise) return RefreshPolicy::PerBank; else if (policy == DRAMSysConfiguration::RefreshPolicy::Per2Bank) return RefreshPolicy::Per2Bank; - else + else // if (policy == DRAMSysConfiguration::RefreshPolicy::SameBank || policy == DRAMSysConfiguration::RefreshPolicy::Groupwise) return RefreshPolicy::SameBank; }(); @@ -520,6 +319,36 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati if (mcConfig.refreshManagement.isValid()) config.refreshManagement = mcConfig.refreshManagement.getValue(); + + if (mcConfig.arbitrationDelayFw.isValid()) + { + config.arbitrationDelayFw = std::round(sc_time(mcConfig.arbitrationDelayFw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + } + + if (mcConfig.arbitrationDelayBw.isValid()) + { + config.arbitrationDelayBw = std::round(sc_time(mcConfig.arbitrationDelayBw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + } + + if (mcConfig.thinkDelayFw.isValid()) + { + config.thinkDelayFw = std::round(sc_time(mcConfig.thinkDelayFw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + } + + if (mcConfig.thinkDelayBw.isValid()) + { + config.thinkDelayBw = std::round(sc_time(mcConfig.thinkDelayBw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + } + + if (mcConfig.phyDelayFw.isValid()) + { + config.phyDelayFw = std::round(sc_time(mcConfig.phyDelayFw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + } + + if (mcConfig.phyDelayBw.isValid()) + { + config.phyDelayBw = std::round(sc_time(mcConfig.phyDelayBw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + } } void Configuration::loadMemSpec(Configuration &config, const DRAMSysConfiguration::MemSpec &memSpecConfig) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 7bf032a8..3578b62b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -77,7 +77,8 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name, logo(); // Load config and initialize modules - Configuration::getInstance().loadMemSpec(Configuration::getInstance(), config.memSpec); + // Important: The memSpec needs to be the first configuration to be loaded! + Configuration::loadMemSpec(Configuration::getInstance(), config.memSpec); Configuration::loadMCConfig(Configuration::getInstance(), config.mcConfig); Configuration::loadSimConfig(Configuration::getInstance(), config.simConfig); diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 28e71f52..31cf682c 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -100,6 +100,7 @@ add_executable(TraceAnalyzer presentation/traceselector.cpp businessObjects/configmodels.cpp businessObjects/commentmodel.cpp + simulationdialog.cpp selectmetrics.ui preferences.ui @@ -108,6 +109,7 @@ add_executable(TraceAnalyzer tracefiletab.ui queryeditor.ui traceanalyzer.ui + simulationdialog.ui scripts/memUtil.py scripts/metrics.py @@ -131,4 +133,5 @@ target_link_libraries(TraceAnalyzer PRIVATE ${QWT_LIBRARY} PRIVATE Qt5::Widgets PRIVATE Qt5::Sql + PRIVATE DRAMSysConfiguration ) diff --git a/DRAMSys/traceAnalyzer/simulationdialog.cpp b/DRAMSys/traceAnalyzer/simulationdialog.cpp new file mode 100644 index 00000000..1cea4728 --- /dev/null +++ b/DRAMSys/traceAnalyzer/simulationdialog.cpp @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2021s, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#include "simulationdialog.h" + +#include +#include +#include +#include +#include +#include + +SimulationDialog::SimulationDialog(QWidget *parent) : QWidget(parent), ui(new Ui::SimulationDialog) +{ + ui->setupUi(this); + + showStopButton(false); + + // Try to find path to DRAMSys + { + QFileInfo fileInfo; + + fileInfo.setFile("../simulator/DRAMSys"); + if (fileInfo.isFile()) + ui->dramSysPath->setText(fileInfo.absoluteFilePath()); + + fileInfo.setFile("../simulator/DRAMSys.exe"); + if (fileInfo.isFile()) + ui->dramSysPath->setText(fileInfo.absoluteFilePath()); + + fileInfo.setFile("simulator/DRAMSys"); + if (fileInfo.isFile()) + ui->dramSysPath->setText(fileInfo.absoluteFilePath()); + + fileInfo.setFile("simulator/DRAMSys.exe"); + if (fileInfo.isFile()) + ui->dramSysPath->setText(fileInfo.absoluteFilePath()); + } + + ui->outputDirLineEdit->setText(QDir::currentPath()); +} + +void SimulationDialog::on_browseDramSysButton_clicked() +{ + QString fileName = + QFileDialog::getOpenFileName(this, ui->browseDramSysButton->text(), {}, "DRAMSys executable (*)"); + ui->dramSysPath->setText(fileName); +} + +void SimulationDialog::on_browseConfigButton_clicked() +{ + QString fileName = + QFileDialog::getOpenFileName(this, ui->browseConfigButton->text(), {}, "Configuration file (*.json)"); + ui->jsonPath->setText(fileName); + + loadConfigurationFromPath(); +} + +void SimulationDialog::on_simulateButton_clicked() +{ + saveConfiguration(temporaryConfigurationFile); + + ui->tabWidget->setCurrentWidget(ui->outputTab); + ui->progressBar->setEnabled(true); + ui->progressBar->setValue(0); + + showStopButton(true); + + // Spawn the DRAMSys process + simulatorProcess = new QProcess(this); + + QObject::connect(simulatorProcess, &QIODevice::readyRead, this, + [=] + { + QByteArray msg = simulatorProcess->read(4096); + msg = msg.trimmed(); + processMessage(msg.toStdString()); + }); + + QObject::connect(simulatorProcess, QOverload::of(&QProcess::finished), this, + [=](int exitCode, QProcess::ExitStatus exitStatus) + { + Q_UNUSED(exitStatus) + + showStopButton(false); + + // Clear all the contents so that the user is not asked + // next time to overwrite the temp file. + temporaryConfigurationFile.resize(0); + + if (exitCode == 0) + { + ui->progressBar->setValue(100); + + QMessageBox msgBox; + msgBox.setText("Simulation done."); + msgBox.setInformativeText("Do you want to open the results?"); + msgBox.setStandardButtons(QMessageBox::Open | QMessageBox::Cancel); + msgBox.setDefaultButton(QMessageBox::Open); + int ret = msgBox.exec(); + + if (ret == QMessageBox::Open) + { + auto results = getSimulationResults(); + openSimulationResults(results); + } + } + }); + + simulatorProcess->setWorkingDirectory(ui->outputDirLineEdit->text()); + simulatorProcess->start(ui->dramSysPath->text(), QStringList(temporaryConfigurationFile.fileName())); +} + +void SimulationDialog::on_reloadButton_clicked() +{ + loadConfigurationFromPath(); + + ui->outputPlainTextEdit->clear(); +} + +void SimulationDialog::on_saveButton_clicked() +{ + QFile file(ui->jsonPath->text()); + saveConfiguration(file); +} + +void SimulationDialog::on_stopButton_clicked() +{ + if (simulatorProcess) + simulatorProcess->terminate(); +} + +void SimulationDialog::showStopButton(bool val) +{ + ui->simulateButton->setVisible(!val); + ui->stopButton->setVisible(val); +} + +void SimulationDialog::saveConfiguration(QFile &file) +{ + if (!file.open(QIODevice::ReadWrite | QIODevice::Text)) + return; + + if (file.size() != 0) + { + QMessageBox msgBox; + msgBox.setText("The configuration file will be overwritten."); + msgBox.setInformativeText("Do you want to save your changes?"); + msgBox.setStandardButtons(QMessageBox::Save | QMessageBox::Cancel); + msgBox.setDefaultButton(QMessageBox::Save); + int ret = msgBox.exec(); + + if (ret != QMessageBox::Save) + return; + } + + QTextStream out(&file); + + loadConfigurationFromTextFields(); + + std::string dump = DRAMSysConfiguration::dump(configuration, 4); + out << dump.c_str(); +} + +void SimulationDialog::processMessage(const std::string &msg) +{ + // Get percentages + QRegularExpression re("(\\d+(\\.\\d+)?|\\.\\d+) ?%"); + QRegularExpressionMatch match = re.match(msg.c_str()); + + if (match.hasMatch()) + { + unsigned int percentage = match.captured(1).toUInt(); + + ui->progressBar->setValue(percentage); + } + + ui->outputPlainTextEdit->appendPlainText(msg.c_str()); +} + +void SimulationDialog::loadConfigurationFromTextFields() +{ + using namespace DRAMSysConfiguration; + + AddressMapping addressMapping; + McConfig mcConfig; + MemSpec memSpec; + SimConfig simConfig; + std::string simulationId; + Optional thermalConfig; + Optional traceSetup; + + simulationId = ui->simulationIdLineEdit->text().toStdString(); + + try + { + from_dump(ui->addressMappingTextEdit->toPlainText().toStdString(), addressMapping); + from_dump(ui->mcConfigTextEdit->toPlainText().toStdString(), mcConfig); + from_dump(ui->memSpecTextEdit->toPlainText().toStdString(), memSpec); + from_dump(ui->simConfigTextEdit->toPlainText().toStdString(), simConfig); + + if (!ui->thermalConfigTextEdit->toPlainText().toStdString().empty()) + from_dump(ui->thermalConfigTextEdit->toPlainText().toStdString(), thermalConfig.setByReference()); + + if (!ui->traceSetupTextEdit->toPlainText().toStdString().empty()) + from_dump(ui->traceSetupTextEdit->toPlainText().toStdString(), traceSetup.setByReference()); + } + catch (const std::exception &e) + { + qWarning() << "Error while parsing json:" << e.what(); + return; + } + + configuration = DRAMSysConfiguration::Configuration{addressMapping, mcConfig, memSpec, simConfig, + simulationId, thermalConfig, traceSetup}; + + loadConfiguration(); +} + +void SimulationDialog::loadConfigurationFromPath() +{ + QFileInfo fileInfo(ui->jsonPath->text()); + + if (!fileInfo.isFile()) + return; + + try + { + configuration = DRAMSysConfiguration::from_path(ui->jsonPath->text().toStdString()); + } + catch (const std::exception &e) + { + qWarning() << "Error while parsing json:" << e.what(); + return; + } + + loadConfiguration(); +} + +void SimulationDialog::loadConfiguration() +{ + ui->simulationIdLabel->setEnabled(true); + ui->simulationId->setEnabled(true); + ui->simulationId->setText(configuration.simulationId.c_str()); + + ui->simulationIdLineEdit->setText(configuration.simulationId.c_str()); + + loadSimConfig(); + loadMcConfig(); + loadMemSpec(); + loadAddressMapping(); + loadThermalConfig(); + loadTraceSetup(); + loadPreview(); +} + +void SimulationDialog::loadSimConfig() +{ + ui->simConfigTextEdit->clear(); + + std::string dump = DRAMSysConfiguration::dump(configuration.simConfig, 4); + ui->simConfigTextEdit->setText(dump.c_str()); +} + +void SimulationDialog::loadMcConfig() +{ + ui->mcConfigTextEdit->clear(); + + std::string dump = DRAMSysConfiguration::dump(configuration.mcConfig, 4); + ui->mcConfigTextEdit->setText(dump.c_str()); +} + +void SimulationDialog::loadMemSpec() +{ + ui->memSpecTextEdit->clear(); + + std::string dump = DRAMSysConfiguration::dump(configuration.memSpec, 4); + ui->memSpecTextEdit->setText(dump.c_str()); +} + +void SimulationDialog::loadAddressMapping() +{ + ui->addressMappingTextEdit->clear(); + + std::string dump = DRAMSysConfiguration::dump(configuration.addressMapping, 4); + ui->addressMappingTextEdit->setText(dump.c_str()); +} + +void SimulationDialog::loadThermalConfig() +{ + ui->thermalConfigTextEdit->clear(); + + if (configuration.thermalConfig.isValid()) + { + std::string dump = DRAMSysConfiguration::dump(configuration.thermalConfig.getValue(), 4); + ui->thermalConfigTextEdit->setText(dump.c_str()); + } +} + +void SimulationDialog::loadTraceSetup() +{ + ui->traceSetupTextEdit->clear(); + + if (configuration.traceSetup.isValid()) + { + std::string dump = DRAMSysConfiguration::dump(configuration.traceSetup.getValue(), 4); + ui->traceSetupTextEdit->setText(dump.c_str()); + } +} + +void SimulationDialog::loadPreview() +{ + ui->previewTextEdit->clear(); + + std::string dump = DRAMSysConfiguration::dump(configuration, 4); + ui->previewTextEdit->setText(dump.c_str()); +} + +QFileInfoList SimulationDialog::getSimulationResults() +{ + QFileInfoList list; + + // Get the path where the tracefiles are located + QDir baseDir(ui->outputDirLineEdit->text()); + + for (const auto &fileInfo : baseDir.entryInfoList()) + { + if (fileInfo.baseName().startsWith(configuration.simulationId.c_str())) + { + // Dont open tracefiles that are older than a few seconds + if (fileInfo.metadataChangeTime().secsTo(QDateTime::currentDateTime()) > 30) + continue; + + list << fileInfo; + } + } + + return list; +} + +void SimulationDialog::openSimulationResults(const QFileInfoList &fileInfos) +{ + for (const auto &fileInfo : fileInfos) + openFileRequested(fileInfo.absoluteFilePath()); +} diff --git a/DRAMSys/traceAnalyzer/simulationdialog.h b/DRAMSys/traceAnalyzer/simulationdialog.h new file mode 100644 index 00000000..c26fda33 --- /dev/null +++ b/DRAMSys/traceAnalyzer/simulationdialog.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2021s, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Derek Christ + */ + +#ifndef SIMULATIONDIALOG_H +#define SIMULATIONDIALOG_H + +#include "ui_simulationdialog.h" + +#include +#include +#include +#include +#include +#include +#include + +namespace Ui +{ +class SimulationDialog; +} + +class SimulationDialog : public QWidget +{ + Q_OBJECT + +public: + explicit SimulationDialog(QWidget *parent = nullptr); + +signals: + void openFileRequested(const QString &path); + +private Q_SLOTS: + void on_browseDramSysButton_clicked(); + void on_browseConfigButton_clicked(); + void on_simulateButton_clicked(); + void on_reloadButton_clicked(); + void on_saveButton_clicked(); + void on_stopButton_clicked(); + +private: + void loadConfigurationFromPath(); + void loadConfigurationFromTextFields(); + + void loadConfiguration(); + void loadSimConfig(); + void loadMcConfig(); + void loadMemSpec(); + void loadAddressMapping(); + void loadThermalConfig(); + void loadTraceSetup(); + void loadPreview(); + + void showStopButton(bool val); + void saveConfiguration(QFile &file); + void processMessage(const std::string &msg); + + QFileInfoList getSimulationResults(); + void openSimulationResults(const QFileInfoList &fileInfos); + + QTemporaryFile temporaryConfigurationFile; + DRAMSysConfiguration::Configuration configuration; + + QPointer simulatorProcess; + + Ui::SimulationDialog *ui; +}; + +#endif diff --git a/DRAMSys/traceAnalyzer/simulationdialog.ui b/DRAMSys/traceAnalyzer/simulationdialog.ui new file mode 100644 index 00000000..4041c770 --- /dev/null +++ b/DRAMSys/traceAnalyzer/simulationdialog.ui @@ -0,0 +1,345 @@ + + + SimulationDialog + + + + 0 + 0 + 884 + 522 + + + + + + + Simulation + + + + + + Simulation + + + + + + + + Browse... + + + + + + + Path to Json configuration... + + + + + + + Path to DRAMSys... + + + + + + + DRAMSys: + + + + + + + Browse... + + + + + + + Base configuration: + + + + + + + Path to output directory... + + + + + + + Browse... + + + + + + + Output directory: + + + + + + + + + + + false + + + Simulation Id: + + + + + + + false + + + + + + + + + + + + + + false + + + 0 + + + + + + + Start Simulation + + + + + + + Stop Simulation + + + + + + + + + + + + 0 + + + + SimConfig + + + + + + + + + + + + + + McConfig + + + + + + + + + + + + + + MemSpec + + + + + + + + + + + + + + ThermalConfig + + + + + + + + + + + + + + TraceSetup + + + + + + + + + + + + + + AddressMapping + + + + + + + + + + + + + + Preview Configuration + + + + + + + + + true + + + + + + + + Output + + + + + + + + + QPlainTextEdit::NoWrap + + + true + + + + + + + + + + + + + Reload + + + + + + + Qt::Horizontal + + + + 40 + 20 + + + + + + + + Simulation Id + + + + + + + Save + + + false + + + + + + + Close + + + + + + + + + + + closeButton + clicked() + SimulationDialog + close() + + + 836 + 507 + + + 830 + 575 + + + + + diff --git a/DRAMSys/traceAnalyzer/traceanalyzer.cpp b/DRAMSys/traceAnalyzer/traceanalyzer.cpp index b0159918..1cc0db53 100644 --- a/DRAMSys/traceAnalyzer/traceanalyzer.cpp +++ b/DRAMSys/traceAnalyzer/traceanalyzer.cpp @@ -37,8 +37,10 @@ */ #include "traceanalyzer.h" +#include "simulationdialog.h" #include "tracefiletab.h" #include "ui_traceanalyzer.h" + #include #include #include @@ -281,3 +283,13 @@ void TraceAnalyzer::closeEvent(QCloseEvent *event) event->accept(); } + +void TraceAnalyzer::on_actionSimulate_triggered() +{ + SimulationDialog *simulationDialog = new SimulationDialog(this); + simulationDialog->setWindowFlag(Qt::Window); + + QObject::connect(simulationDialog, &SimulationDialog::openFileRequested, this, &TraceAnalyzer::openTracefileTab); + + simulationDialog->show(); +} diff --git a/DRAMSys/traceAnalyzer/traceanalyzer.h b/DRAMSys/traceAnalyzer/traceanalyzer.h index a2aab12d..b5e8cdd1 100644 --- a/DRAMSys/traceAnalyzer/traceanalyzer.h +++ b/DRAMSys/traceAnalyzer/traceanalyzer.h @@ -97,6 +97,7 @@ private Q_SLOTS: void on_actionClose_triggered(); void on_actionClose_all_triggered(); void on_actionAbout_triggered(); + void on_actionSimulate_triggered(); public Q_SLOTS: void statusChanged(const QString &message); diff --git a/DRAMSys/traceAnalyzer/traceanalyzer.ui b/DRAMSys/traceAnalyzer/traceanalyzer.ui index f382563d..5fec0849 100644 --- a/DRAMSys/traceAnalyzer/traceanalyzer.ui +++ b/DRAMSys/traceAnalyzer/traceanalyzer.ui @@ -78,7 +78,14 @@ + + + &Run + + + + @@ -225,6 +232,14 @@ Save &as... + + + + + + &Simulate... + + From 5c300a2cfe59c5d4a833b97654d081d5046ca361 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 9 Nov 2021 11:13:45 +0100 Subject: [PATCH 07/23] Fix compilation failure --- DRAMSys/library/src/common/configuration/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/common/configuration/CMakeLists.txt b/DRAMSys/library/src/common/configuration/CMakeLists.txt index 314d0f14..92a23505 100644 --- a/DRAMSys/library/src/common/configuration/CMakeLists.txt +++ b/DRAMSys/library/src/common/configuration/CMakeLists.txt @@ -59,4 +59,4 @@ target_compile_definitions(DRAMSysConfiguration PUBLIC DRAMSysResourceDirectory= target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) -target_link_libraries(DRAMSysConfiguration PRIVATE nlohmann_json::nlohmann_json) +target_link_libraries(DRAMSysConfiguration PUBLIC nlohmann_json::nlohmann_json) From 71eed44060d7e362fc6052be4bb6b2b99ef4ddf2 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 9 Nov 2021 14:38:26 +0100 Subject: [PATCH 08/23] Make resource path configurable in TraceAnalyzer --- DRAMSys/simulator/TraceSetup.cpp | 2 +- DRAMSys/traceAnalyzer/simulationdialog.cpp | 26 ++++- DRAMSys/traceAnalyzer/simulationdialog.h | 2 + DRAMSys/traceAnalyzer/simulationdialog.ui | 115 +++++++++++++++------ 4 files changed, 110 insertions(+), 35 deletions(-) diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 2ec971ef..40d80cb4 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -82,7 +82,7 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); std::stringstream stlFileStream; - stlFileStream << pathToResources << "traces/" << name; + stlFileStream << pathToResources << "/traces/" << name; std::string stlFile = stlFileStream.str(); std::string moduleName = name; diff --git a/DRAMSys/traceAnalyzer/simulationdialog.cpp b/DRAMSys/traceAnalyzer/simulationdialog.cpp index 1cea4728..32ae659a 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.cpp +++ b/DRAMSys/traceAnalyzer/simulationdialog.cpp @@ -88,6 +88,24 @@ void SimulationDialog::on_browseConfigButton_clicked() loadConfigurationFromPath(); } +void SimulationDialog::on_browseOutputButton_clicked() +{ + QString fileName = + QFileDialog::getExistingDirectory(this, ui->browseOutputButton->text(), {}); + ui->outputDirLineEdit->setText(fileName); + + loadConfigurationFromPath(); +} + +void SimulationDialog::on_browseResourceDirButton_clicked() +{ + QString fileName = + QFileDialog::getExistingDirectory(this, ui->browseResourceDirButton->text(), {}); + ui->resourceDirLineEdit->setText(fileName); + + loadConfigurationFromPath(); +} + void SimulationDialog::on_simulateButton_clicked() { saveConfiguration(temporaryConfigurationFile); @@ -139,8 +157,14 @@ void SimulationDialog::on_simulateButton_clicked() } }); + QStringList argumentList; + argumentList << temporaryConfigurationFile.fileName(); + + if (!ui->resourceDirLineEdit->text().isEmpty()) + argumentList << ui->resourceDirLineEdit->text(); + simulatorProcess->setWorkingDirectory(ui->outputDirLineEdit->text()); - simulatorProcess->start(ui->dramSysPath->text(), QStringList(temporaryConfigurationFile.fileName())); + simulatorProcess->start(ui->dramSysPath->text(), argumentList); } void SimulationDialog::on_reloadButton_clicked() diff --git a/DRAMSys/traceAnalyzer/simulationdialog.h b/DRAMSys/traceAnalyzer/simulationdialog.h index c26fda33..b7355480 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.h +++ b/DRAMSys/traceAnalyzer/simulationdialog.h @@ -64,6 +64,8 @@ signals: private Q_SLOTS: void on_browseDramSysButton_clicked(); void on_browseConfigButton_clicked(); + void on_browseOutputButton_clicked(); + void on_browseResourceDirButton_clicked(); void on_simulateButton_clicked(); void on_reloadButton_clicked(); void on_saveButton_clicked(); diff --git a/DRAMSys/traceAnalyzer/simulationdialog.ui b/DRAMSys/traceAnalyzer/simulationdialog.ui index 4041c770..f3dda234 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.ui +++ b/DRAMSys/traceAnalyzer/simulationdialog.ui @@ -6,8 +6,8 @@ 0 0 - 884 - 522 + 920 + 620 @@ -25,36 +25,18 @@ - - + + - Browse... + - - - - - Path to Json configuration... + Path to resource directory... (optional) - - - - Path to DRAMSys... - - - - - - - DRAMSys: - - - - - + + Browse... @@ -67,17 +49,17 @@ - - - - Path to output directory... + + + + Browse... - - + + - Browse... + DRAMSys: @@ -88,6 +70,48 @@ + + + + Path to DRAMSys... + + + + + + + Browse... + + + + + + + Browse... + + + + + + + Path to output directory... + + + + + + + Path to Json configuration... + + + + + + + Resource directory: + + + @@ -323,6 +347,31 @@ + + dramSysPath + outputDirLineEdit + jsonPath + resourceDirLineEdit + browseDramSysButton + browseOutputButton + browseConfigButton + browseResourceDirButton + simulateButton + stopButton + tabWidget + reloadButton + simulationIdLineEdit + saveButton + closeButton + simConfigTextEdit + outputPlainTextEdit + memSpecTextEdit + thermalConfigTextEdit + traceSetupTextEdit + addressMappingTextEdit + mcConfigTextEdit + previewTextEdit + From bb0aba0758cc30a0ff893015e3aeca2cde2bbbc9 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 9 Nov 2021 15:24:19 +0100 Subject: [PATCH 09/23] Various fixes - Don't use unordered sets for addressmapping - Don't use unordered sets for tracesetup - XOR bits weren't added - NoRefresh policy was fixed --- .../src/common/configuration/AddressMapping.h | 15 +++++++-------- .../src/common/configuration/TraceSetup.cpp | 2 +- .../library/src/common/configuration/TraceSetup.h | 3 +-- .../src/common/configuration/tests/simpletest.cpp | 10 +++++----- DRAMSys/library/src/simulation/AddressDecoder.cpp | 8 ++++++++ 5 files changed, 22 insertions(+), 16 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index 28a6c097..72884f1f 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -39,7 +39,6 @@ #include "util.h" #include -#include namespace DRAMSysConfiguration { @@ -58,13 +57,13 @@ void from_json(const json &j, XorPair &x); struct AddressMapping { - Optional> byteBits; - std::unordered_set coloumnBits; - std::unordered_set bankBits; - Optional> bankGroupBits; - std::unordered_set rowBits; - Optional> channelBits; - Optional> rankBits; + Optional> byteBits; + std::vector coloumnBits; + std::vector bankBits; + Optional> bankGroupBits; + std::vector rowBits; + Optional> channelBits; + Optional> rankBits; Optional> xorBits; }; diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index f2dd330e..33cf0f8b 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -132,7 +132,7 @@ void from_json(const json &j, TraceSetup &c) if (initiator_j.contains("maxPendingWriteRequests")) initiator_j.at("maxPendingWriteRequests").get_to(initiator->maxPendingWriteRequests); - c.initiators.emplace(std::move(initiator)); + c.initiators.emplace_back(std::move(initiator)); } } diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 2a84bd61..edc61d8c 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -40,7 +40,6 @@ #include #include -#include namespace DRAMSysConfiguration { @@ -103,7 +102,7 @@ struct TraceHammer : public TrafficInitiator struct TraceSetup { - std::unordered_set> initiators; + std::vector> initiators; }; void to_json(json &j, const TraceSetup &c); diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 221b062c..de8ff9a4 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -153,11 +153,11 @@ std::unique_ptr getTraceHammer() DRAMSysConfiguration::TraceSetup getTraceSetup() { - std::unordered_set> initiators; - initiators.emplace(getTracePlayer()); - initiators.emplace(getTraceGeneratorRandom()); - initiators.emplace(getTraceGeneratorSequential()); - initiators.emplace(getTraceHammer()); + std::vector> initiators; + initiators.emplace_back(getTracePlayer()); + initiators.emplace_back(getTraceGeneratorRandom()); + initiators.emplace_back(getTraceGeneratorSequential()); + initiators.emplace_back(getTraceHammer()); return DRAMSysConfiguration::TraceSetup{initiators}; } diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index 7e18bf11..824f45ce 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -70,6 +70,14 @@ AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addre std::copy(byteBits.begin(), byteBits.end(), std::back_inserter(vByteBits)); } + if (addressMapping.xorBits.isValid()) + { + for (const auto &xorBit : addressMapping.xorBits.getValue()) + { + vXor.emplace_back(xorBit.first, xorBit.second); + } + } + std::copy(addressMapping.bankBits.begin(), addressMapping.bankBits.end(), std::back_inserter(vBankBits)); std::copy(addressMapping.rowBits.begin(), addressMapping.rowBits.end(), std::back_inserter(vRowBits)); std::copy(addressMapping.coloumnBits.begin(), addressMapping.coloumnBits.end(), std::back_inserter(vColumnBits)); From 335993e9fe7e5a66e7157647f11632ffd0334579 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 12 Nov 2021 09:25:13 +0100 Subject: [PATCH 10/23] Update authors --- DRAMSys/library/CMakeLists.txt | 1 + DRAMSys/library/src/common/TlmRecorder.cpp | 1 + DRAMSys/library/src/common/utils.cpp | 1 + DRAMSys/library/src/common/utils.h | 1 + DRAMSys/library/src/configuration/Configuration.cpp | 3 +-- DRAMSys/library/src/configuration/Configuration.h | 1 + DRAMSys/library/src/configuration/TemperatureSimConfig.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpec.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpec.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h | 1 + DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp | 1 + DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h | 1 + DRAMSys/library/src/simulation/AddressDecoder.cpp | 1 + DRAMSys/library/src/simulation/AddressDecoder.h | 1 + DRAMSys/library/src/simulation/Arbiter.cpp | 1 + DRAMSys/library/src/simulation/Arbiter.h | 1 + DRAMSys/library/src/simulation/DRAMSys.cpp | 1 + DRAMSys/library/src/simulation/DRAMSys.h | 1 + DRAMSys/library/src/simulation/DRAMSysRecordable.cpp | 1 + DRAMSys/library/src/simulation/DRAMSysRecordable.h | 1 + DRAMSys/library/src/simulation/TemperatureController.h | 1 + DRAMSys/simulator/main.cpp | 1 + DRAMSys/traceAnalyzer/simulationdialog.cpp | 2 +- DRAMSys/traceAnalyzer/simulationdialog.h | 2 +- 43 files changed, 43 insertions(+), 4 deletions(-) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index eb7334c8..6c69454c 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -31,6 +31,7 @@ # Authors: # Matthias Jung # Lukas Steiner +# Derek Christ cmake_minimum_required(VERSION 3.10) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index e64d7ebe..8f410f03 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -34,6 +34,7 @@ * Robert Gernhardt * Matthias Jung * Eder F. Zulian + * Derek Christ */ #include diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 239c11d2..11cef417 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -34,6 +34,7 @@ * Robert Gernhardt * Matthias Jung * Luiza Correa + * Derek Christ */ #include diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index 8cc7e25f..a0b90f26 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -34,6 +34,7 @@ * Matthias Jung * Eder F. Zulian * Luiza Correa + * Derek Christ */ #ifndef UTILS_H diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 4a003206..d7915697 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -36,6 +36,7 @@ * Felipe S. Prado * Lukas Steiner * Luiza Correa + * Derek Christ */ #include @@ -92,8 +93,6 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const void Configuration::loadSimConfig(Configuration &config, const DRAMSysConfiguration::SimConfig &simConfig) { - // TODO document all default values... - if (simConfig.addressOffset.isValid()) config.addressOffset = simConfig.addressOffset.getValue(); diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index 54c16727..697b293a 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -36,6 +36,7 @@ * Felipe S. Prado * Lukas Steiner * Luiza Correa + * Derek Christ */ #ifndef CONFIGURATION_H diff --git a/DRAMSys/library/src/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/configuration/TemperatureSimConfig.h index c7f94265..9f0e67bf 100644 --- a/DRAMSys/library/src/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/configuration/TemperatureSimConfig.h @@ -33,6 +33,7 @@ * Eder F. Zulian * Matthias Jung * Luiza Correa + * Derek Christ */ #ifndef TEMPERATURESIMCONFIG_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 09179655..99a12c4e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include "MemSpec.h" diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 0af08d5d..480b3419 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -33,6 +33,7 @@ * Janik Schlemminger * Matthias Jung * Lukas Steiner + * Derek Christ */ #ifndef MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index ff1a05ca..81b8b2df 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 5924afff..beb5629f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index c1176f80..f2c9a204 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 67f3fe24..e7db402b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index f42c4b14..61ad2cd5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index 39b05e8c..178cca5c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECDDR5_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 13318e7b..a0d7b5a8 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index bd8dc580..f5998776 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECGDDR5_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index ea04e6b8..9ff6768b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index 002d8221..432ea1e0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECGDDR5X_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 86a54674..0e065766 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index 7d75362b..e96c8513 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECGDDR6_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 852af18e..156e07e5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 565f7eeb..71dffc76 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECHBM2_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index a1b81479..7e1efd8f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 05fd8ad2..d93cf8cc 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECLPDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp index 586b2ac5..08c82005 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h index 72749afc..33a91056 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECSTTMRAM_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index e5ba6610..f9ed3b9c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index afce3e92..ef300a2c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 736548e1..31f5ef5f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 78ea7611..4746d792 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef MEMSPECWIDEIO2_H diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index 824f45ce..c272eb4a 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -33,6 +33,7 @@ * Johannes Feldmann * Lukas Steiner * Luiza Correa + * Derek Christ */ #include diff --git a/DRAMSys/library/src/simulation/AddressDecoder.h b/DRAMSys/library/src/simulation/AddressDecoder.h index a88bf290..12a77627 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.h +++ b/DRAMSys/library/src/simulation/AddressDecoder.h @@ -33,6 +33,7 @@ * Johannes Feldmann * Lukas Steiner * Luiza Correa + * Derek Christ */ #ifndef ADDRESSDECODER_H diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 7b51d18e..00646789 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -34,6 +34,7 @@ * Matthias Jung * Eder F. Zulian * Lukas Steiner + * Derek Christ */ #include "Arbiter.h" diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 09150b14..4ee8ceb3 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -34,6 +34,7 @@ * Matthias Jung * Eder F. Zulian * Lukas Steiner + * Derek Christ */ #ifndef ARBITER_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 3578b62b..a771bd2a 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -35,6 +35,7 @@ * Eder F. Zulian * Felipe S. Prado * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index ebc9a412..8c91baf5 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -35,6 +35,7 @@ * Eder F. Zulian * Felipe S. Prado * Lukas Steiner + * Derek Christ */ #ifndef DRAMSYS_H diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 0eeac935..fa62d270 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #include "DRAMSysRecordable.h" diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.h b/DRAMSys/library/src/simulation/DRAMSysRecordable.h index 570fa50d..aeb0b387 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.h +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.h @@ -31,6 +31,7 @@ * * Authors: * Lukas Steiner + * Derek Christ */ #ifndef DRAMSYSRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index 8ad01896..c2d49e03 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -32,6 +32,7 @@ * Authors: * Eder F. Zulian * Matthias Jung + * Derek Christ */ #ifndef TEMPERATURECONTROLLER_H diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index b5e0c900..9ce554a6 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -34,6 +34,7 @@ * Matthias Jung * Luiza Correa * Lukas Steiner + * Derek Christ */ #include diff --git a/DRAMSys/traceAnalyzer/simulationdialog.cpp b/DRAMSys/traceAnalyzer/simulationdialog.cpp index 32ae659a..e4c1dc18 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.cpp +++ b/DRAMSys/traceAnalyzer/simulationdialog.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021s, Technische Universität Kaiserslautern + * Copyright (c) 2021, Technische Universität Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/DRAMSys/traceAnalyzer/simulationdialog.h b/DRAMSys/traceAnalyzer/simulationdialog.h index b7355480..311714d3 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.h +++ b/DRAMSys/traceAnalyzer/simulationdialog.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021s, Technische Universität Kaiserslautern + * Copyright (c) 2021, Technische Universität Kaiserslautern * All rights reserved. * * Redistribution and use in source and binary forms, with or without From de4cb1be663184bcb55abecfa946fcc40c9213f4 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 2 Dec 2021 11:03:52 +0100 Subject: [PATCH 11/23] Fix bug regarding addressIncrement --- .../src/common/configuration/TraceSetup.cpp | 40 ++++++++++--------- DRAMSys/simulator/TraceSetup.cpp | 8 +++- DRAMSys/traceAnalyzer/simulationdialog.cpp | 3 ++ 3 files changed, 32 insertions(+), 19 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 33cf0f8b..9d39a78f 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -49,36 +49,37 @@ void to_json(json &j, const TraceSetup &c) for (const auto &initiator : c.initiators) { - json inititator_j; + json initiator_j; - inititator_j["name"] = initiator->name; - inititator_j["clkMhz"] = initiator->clkMhz; - inititator_j["maxPendingReadRequests"] = initiator->maxPendingReadRequests; - inititator_j["maxPendingWriteRequests"] = initiator->maxPendingWriteRequests; + initiator_j["name"] = initiator->name; + initiator_j["clkMhz"] = initiator->clkMhz; + initiator_j["maxPendingReadRequests"] = initiator->maxPendingReadRequests; + initiator_j["maxPendingWriteRequests"] = initiator->maxPendingWriteRequests; if (const auto generator = dynamic_cast(initiator.get())) { - inititator_j["type"] = "generator"; - inititator_j["numRequests"] = generator->numRequests; - inititator_j["rwRatio"] = generator->rwRatio; - inititator_j["addressDistribution"] = generator->addressDistribution; - inititator_j["seed"] = generator->seed; - inititator_j["minAddress"] = generator->minAddress; - inititator_j["maxAddress"] = generator->maxAddress; + initiator_j["type"] = "generator"; + initiator_j["numRequests"] = generator->numRequests; + initiator_j["rwRatio"] = generator->rwRatio; + initiator_j["addressDistribution"] = generator->addressDistribution; + initiator_j["addressIncrement"] = generator->addressIncrement; + initiator_j["seed"] = generator->seed; + initiator_j["minAddress"] = generator->minAddress; + initiator_j["maxAddress"] = generator->maxAddress; } else if (const auto hammer = dynamic_cast(initiator.get())) { - inititator_j["type"] = "hammer"; - inititator_j["numRequests"] = hammer->numRequests; - inititator_j["rowIncrement"] = hammer->rowIncrement; + initiator_j["type"] = "hammer"; + initiator_j["numRequests"] = hammer->numRequests; + initiator_j["rowIncrement"] = hammer->rowIncrement; } else if (const auto player = dynamic_cast(initiator.get())) { - inititator_j["type"] = "player"; + initiator_j["type"] = "player"; } - remove_null_values(inititator_j); - j.insert(j.end(), inititator_j); + remove_null_values(initiator_j); + j.insert(j.end(), initiator_j); } } @@ -102,6 +103,9 @@ void from_json(const json &j, TraceSetup &c) initiator_j.at("rwRatio").get_to(generator->rwRatio); initiator_j.at("addressDistribution").get_to(generator->addressDistribution); + if (initiator_j.contains("addressIncrement")) + initiator_j.at("addressIncrement").get_to(generator->addressIncrement); + if (initiator_j.contains("seed")) initiator_j.at("seed").get_to(generator->seed); diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 40d80cb4..2f4bb012 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -117,13 +117,19 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, return 0; }(); + if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) + SC_REPORT_FATAL("TraceSetup", "minAddress is out of range."); + uint64_t maxAddress = [=]() -> uint64_t { if (generator->maxAddress.isValid()) return generator->maxAddress.getValue(); else - return 0; + return Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; }(); + if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) + SC_REPORT_FATAL("TraceSetup", "minAddress is out of range."); + if (maxAddress < minAddress) SC_REPORT_FATAL("TraceSetup", "maxAddress is smaller than minAddress."); diff --git a/DRAMSys/traceAnalyzer/simulationdialog.cpp b/DRAMSys/traceAnalyzer/simulationdialog.cpp index e4c1dc18..218909ce 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.cpp +++ b/DRAMSys/traceAnalyzer/simulationdialog.cpp @@ -210,6 +210,9 @@ void SimulationDialog::saveConfiguration(QFile &file) return; } + // Clear the file + file.resize(0); + QTextStream out(&file); loadConfigurationFromTextFields(); From 7127a753af2c998fa36cc8866e919a48987566db Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 13 Dec 2021 10:45:20 +0100 Subject: [PATCH 12/23] Implement Json serializing/deserializing for new state machines --- .../common/configuration/ThermalConfig.cpp | 1 + .../src/common/configuration/TraceSetup.cpp | 104 +++++++++++++++--- .../src/common/configuration/TraceSetup.h | 17 ++- .../common/configuration/tests/simpletest.cpp | 63 ++++++++--- 4 files changed, 148 insertions(+), 37 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp index fdcbd0e2..f3bed414 100644 --- a/DRAMSys/library/src/common/configuration/ThermalConfig.cpp +++ b/DRAMSys/library/src/common/configuration/ThermalConfig.cpp @@ -100,6 +100,7 @@ void from_json(const json &j, PowerInfo &c) { DramDieChannel channel; j_powerinfo.at(entry.key()).get_to(channel); + channel.identifier = entry.key(); c.channels.push_back(channel); } diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 9d39a78f..9ead2a50 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -59,13 +59,51 @@ void to_json(json &j, const TraceSetup &c) if (const auto generator = dynamic_cast(initiator.get())) { initiator_j["type"] = "generator"; - initiator_j["numRequests"] = generator->numRequests; - initiator_j["rwRatio"] = generator->rwRatio; - initiator_j["addressDistribution"] = generator->addressDistribution; - initiator_j["addressIncrement"] = generator->addressIncrement; initiator_j["seed"] = generator->seed; - initiator_j["minAddress"] = generator->minAddress; - initiator_j["maxAddress"] = generator->maxAddress; + + // When there are less than 2 states, flatten out the json. + if (generator->states.size() == 1) + { + const auto &state = generator->states[0]; + initiator_j["numRequests"] = state.numRequests; + initiator_j["rwRatio"] = state.rwRatio; + initiator_j["addressDistribution"] = state.addressDistribution; + initiator_j["addressIncrement"] = state.addressIncrement; + initiator_j["minAddress"] = state.minAddress; + initiator_j["maxAddress"] = state.maxAddress; + } + else + { + json states_j = json::array(); + + for (const auto &state : generator->states) + { + json state_j; + state_j["id"] = state.first; + state_j["numRequests"] = state.second.numRequests; + state_j["rwRatio"] = state.second.rwRatio; + state_j["addressDistribution"] = state.second.addressDistribution; + state_j["addressIncrement"] = state.second.addressIncrement; + state_j["minAddress"] = state.second.minAddress; + state_j["maxAddress"] = state.second.maxAddress; + remove_null_values(state_j); + states_j.insert(states_j.end(), state_j); + } + initiator_j["states"] = states_j; + + json transitions_j = json::array(); + + for (const auto &transition : generator->transitions) + { + json transition_j; + transition_j["from"] = transition.from; + transition_j["to"] = transition.to; + transition_j["propability"] = transition.propability; + remove_null_values(transition_j); + transitions_j.insert(transitions_j.end(), transition_j); + } + initiator_j["transitions"] = transitions_j; + } } else if (const auto hammer = dynamic_cast(initiator.get())) { @@ -99,21 +137,53 @@ void from_json(const json &j, TraceSetup &c) { TraceGenerator *generator = new TraceGenerator; - initiator_j.at("numRequests").get_to(generator->numRequests); - initiator_j.at("rwRatio").get_to(generator->rwRatio); - initiator_j.at("addressDistribution").get_to(generator->addressDistribution); + auto process_state = [](const json &state_j) -> std::pair { + TraceGeneratorState state {}; - if (initiator_j.contains("addressIncrement")) - initiator_j.at("addressIncrement").get_to(generator->addressIncrement); + state_j.at("numRequests").get_to(state.numRequests); + state_j.at("rwRatio").get_to(state.rwRatio); + state_j.at("addressDistribution").get_to(state.addressDistribution); - if (initiator_j.contains("seed")) - initiator_j.at("seed").get_to(generator->seed); + if (state_j.contains("addressIncrement")) + state_j.at("addressIncrement").get_to(state.addressIncrement); - if (initiator_j.contains("minAddress")) - initiator_j.at("minAddress").get_to(generator->minAddress); + if (state_j.contains("minAddress")) + state_j.at("minAddress").get_to(state.minAddress); - if (initiator_j.contains("maxAddress")) - initiator_j.at("maxAddress").get_to(generator->maxAddress); + if (state_j.contains("maxAddress")) + state_j.at("maxAddress").get_to(state.maxAddress); + + // Default to 0 + unsigned int id = 0; + + if (state_j.contains("id")) + id = state_j.at("id"); + + return {id, state}; + }; + + if (initiator_j.contains("states")) + { + for (const auto &state_j : initiator_j.at("states")) + { + auto state = process_state(state_j); + generator->states[state.first] = state.second; + } + + for (const auto &transition_j : initiator_j.at("transitions")) + { + TraceGeneratorStateTransition transition; + transition.from = transition_j.at("from"); + transition.to = transition_j.at("to"); + transition.propability = transition_j.at("propability"); + generator->transitions.push_back(transition); + } + } + else // Only one state will be created + { + auto state = process_state(initiator_j); + generator->states[state.first] = state.second; + } initiator = std::unique_ptr(generator); } diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index edc61d8c..4d094286 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -83,17 +83,30 @@ struct TracePlayer : public TrafficInitiator { }; -struct TraceGenerator : public TrafficInitiator +struct TraceGeneratorState { uint64_t numRequests; double rwRatio; AddressDistribution addressDistribution; Optional addressIncrement; - Optional seed; Optional minAddress; Optional maxAddress; }; +struct TraceGeneratorStateTransition +{ + unsigned int from; + unsigned int to; + float propability; +}; + +struct TraceGenerator : public TrafficInitiator +{ + Optional seed; + std::map states; + std::vector transitions; +}; + struct TraceHammer : public TrafficInitiator { uint64_t numRequests; diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index de8ff9a4..e1823bbe 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -104,36 +104,63 @@ std::unique_ptr getTracePlayer() return std::unique_ptr(player); } -std::unique_ptr getTraceGeneratorRandom() +std::unique_ptr getTraceGeneratorOneState() { DRAMSysConfiguration::TraceGenerator *gen = new DRAMSysConfiguration::TraceGenerator; gen->clkMhz = 100; gen->name = "MyTestGen"; - gen->addressDistribution = DRAMSysConfiguration::AddressDistribution::Random; - gen->maxAddress = 1000; - gen->maxPendingReadRequests = 8; - gen->rwRatio = 0.5; - gen->seed = 1337; - gen->numRequests = 1000; + DRAMSysConfiguration::TraceGeneratorState state0 { + 1000, + 0.5, + DRAMSysConfiguration::AddressDistribution::Random, + {}, + {}, + {} + }; + + gen->states[0] = state0; return std::unique_ptr(gen); } -std::unique_ptr getTraceGeneratorSequential() +std::unique_ptr getTraceGeneratorMultipleStates() { DRAMSysConfiguration::TraceGenerator *gen = new DRAMSysConfiguration::TraceGenerator; gen->clkMhz = 100; gen->name = "MyTestGen"; - - gen->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; - gen->addressIncrement = 64; - gen->maxAddress = 1000; gen->maxPendingReadRequests = 8; - gen->rwRatio = 0.5; - gen->numRequests = 1000; + + DRAMSysConfiguration::TraceGeneratorState state0 { + 1000, + 0.5, + DRAMSysConfiguration::AddressDistribution::Sequential, + {256}, + {}, + {1024} + }; + + DRAMSysConfiguration::TraceGeneratorState state1 { + 100, + 0.75, + DRAMSysConfiguration::AddressDistribution::Sequential, + {512}, + {1024}, + {2048} + }; + + gen->states[0] = state0; + gen->states[1] = state1; + + DRAMSysConfiguration::TraceGeneratorStateTransition transistion0 { + 0, + 1, + 1.0 + }; + + gen->transitions.push_back(transistion0); return std::unique_ptr(gen); } @@ -155,8 +182,8 @@ DRAMSysConfiguration::TraceSetup getTraceSetup() { std::vector> initiators; initiators.emplace_back(getTracePlayer()); - initiators.emplace_back(getTraceGeneratorRandom()); - initiators.emplace_back(getTraceGeneratorSequential()); + initiators.emplace_back(getTraceGeneratorOneState()); + initiators.emplace_back(getTraceGeneratorMultipleStates()); initiators.emplace_back(getTraceHammer()); return DRAMSysConfiguration::TraceSetup{initiators}; @@ -193,11 +220,11 @@ int main() j_myhbm2["simulation"] = hbm2conf; filehbm2 << j_myhbm2.dump(4); - std::ifstream file3("old_conf.json"); + std::ifstream file3("myjson.json"); json ddr5_old = json::parse(file3, nullptr, false); json ddr5_old_conf = ddr5_old.at("simulation"); DRAMSysConfiguration::Configuration ddr5_old_config = ddr5_old_conf.get(); - std::ofstream fileoldout("old_conf_converted.json"); + std::ofstream fileoldout("myjson2.json"); json j_oldconfconv; j_oldconfconv["simulation"] = ddr5_old_config; fileoldout << j_oldconfconv.dump(4); From 696e9c17d7f19821160370b7044ff9cd0a0815fd Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 13 Dec 2021 16:08:01 +0100 Subject: [PATCH 13/23] Introduce a state machine design for TrafficGenerators Its now possible to design TrafficGenerators in a state machine style. Each state can have different configurations and the transitions are defined as propabilities, which makes the design very flexible. --- .../src/common/configuration/TraceSetup.cpp | 18 +- .../src/common/configuration/TraceSetup.h | 3 +- .../common/configuration/tests/simpletest.cpp | 38 +-- DRAMSys/simulator/TraceSetup.cpp | 64 +--- DRAMSys/simulator/TrafficGenerator.cpp | 292 +++++++++++++----- DRAMSys/simulator/TrafficGenerator.h | 119 ++++--- DRAMSys/simulator/TrafficInitiator.cpp | 23 ++ DRAMSys/simulator/TrafficInitiator.h | 8 +- 8 files changed, 328 insertions(+), 237 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 9ead2a50..bba018c5 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -96,9 +96,9 @@ void to_json(json &j, const TraceSetup &c) for (const auto &transition : generator->transitions) { json transition_j; - transition_j["from"] = transition.from; - transition_j["to"] = transition.to; - transition_j["propability"] = transition.propability; + transition_j["from"] = transition.first; + transition_j["to"] = transition.second.to; + transition_j["propability"] = transition.second.propability; remove_null_values(transition_j); transitions_j.insert(transitions_j.end(), transition_j); } @@ -137,8 +137,9 @@ void from_json(const json &j, TraceSetup &c) { TraceGenerator *generator = new TraceGenerator; - auto process_state = [](const json &state_j) -> std::pair { - TraceGeneratorState state {}; + auto process_state = [](const json &state_j) -> std::pair + { + TraceGeneratorState state{}; state_j.at("numRequests").get_to(state.numRequests); state_j.at("rwRatio").get_to(state.rwRatio); @@ -173,10 +174,10 @@ void from_json(const json &j, TraceSetup &c) for (const auto &transition_j : initiator_j.at("transitions")) { TraceGeneratorStateTransition transition; - transition.from = transition_j.at("from"); + unsigned int from = transition_j.at("from"); transition.to = transition_j.at("to"); transition.propability = transition_j.at("propability"); - generator->transitions.push_back(transition); + generator->transitions.emplace(from, transition); } } else // Only one state will be created @@ -185,6 +186,9 @@ void from_json(const json &j, TraceSetup &c) generator->states[state.first] = state.second; } + if (initiator_j.contains("seed")) + initiator_j.at("seed").get_to(generator->seed); + initiator = std::unique_ptr(generator); } else if (type == TrafficInitiatorType::Hammer) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 4d094286..4fc804d8 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -95,7 +95,6 @@ struct TraceGeneratorState struct TraceGeneratorStateTransition { - unsigned int from; unsigned int to; float propability; }; @@ -104,7 +103,7 @@ struct TraceGenerator : public TrafficInitiator { Optional seed; std::map states; - std::vector transitions; + std::multimap transitions; }; struct TraceHammer : public TrafficInitiator diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index e1823bbe..50716769 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -111,14 +111,8 @@ std::unique_ptr getTraceGeneratorOneState( gen->clkMhz = 100; gen->name = "MyTestGen"; - DRAMSysConfiguration::TraceGeneratorState state0 { - 1000, - 0.5, - DRAMSysConfiguration::AddressDistribution::Random, - {}, - {}, - {} - }; + DRAMSysConfiguration::TraceGeneratorState state0{1000, 0.5, DRAMSysConfiguration::AddressDistribution::Random, + {}, {}, {}}; gen->states[0] = state0; @@ -133,34 +127,18 @@ std::unique_ptr getTraceGeneratorMultipleS gen->name = "MyTestGen"; gen->maxPendingReadRequests = 8; - DRAMSysConfiguration::TraceGeneratorState state0 { - 1000, - 0.5, - DRAMSysConfiguration::AddressDistribution::Sequential, - {256}, - {}, - {1024} - }; + DRAMSysConfiguration::TraceGeneratorState state0{1000, 0.5, DRAMSysConfiguration::AddressDistribution::Sequential, + {256}, {}, {1024}}; - DRAMSysConfiguration::TraceGeneratorState state1 { - 100, - 0.75, - DRAMSysConfiguration::AddressDistribution::Sequential, - {512}, - {1024}, - {2048} - }; + DRAMSysConfiguration::TraceGeneratorState state1{ + 100, 0.75, DRAMSysConfiguration::AddressDistribution::Sequential, {512}, {1024}, {2048}}; gen->states[0] = state0; gen->states[1] = state1; - DRAMSysConfiguration::TraceGeneratorStateTransition transistion0 { - 0, - 1, - 1.0 - }; + DRAMSysConfiguration::TraceGeneratorStateTransition transistion0{1, 1.0}; - gen->transitions.push_back(transistion0); + gen->transitions.emplace(0, transistion0); return std::unique_ptr(gen); } diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 2f4bb012..966fff87 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -104,72 +104,18 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, } else if (auto generator = std::dynamic_pointer_cast(inititator)) { - uint64_t numRequests = generator->numRequests; - double rwRatio = generator->rwRatio; + TrafficGenerator *trafficGenerator = new TrafficGenerator(name.c_str(), *generator, this); + players.push_back(trafficGenerator); - if (rwRatio < 0 || rwRatio > 1) - SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); - - uint64_t minAddress = [=]() -> uint64_t { - if (generator->minAddress.isValid()) - return generator->minAddress.getValue(); - else - return 0; - }(); - - if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) - SC_REPORT_FATAL("TraceSetup", "minAddress is out of range."); - - uint64_t maxAddress = [=]() -> uint64_t { - if (generator->maxAddress.isValid()) - return generator->maxAddress.getValue(); - else - return Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; - }(); - - if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) - SC_REPORT_FATAL("TraceSetup", "minAddress is out of range."); - - if (maxAddress < minAddress) - SC_REPORT_FATAL("TraceSetup", "maxAddress is smaller than minAddress."); - - unsigned int seed = [=]() -> unsigned int { - if (generator->seed.isValid()) - return generator->seed.getValue(); - else - return 0; - }(); - - if (generator->addressDistribution == DRAMSysConfiguration::AddressDistribution::Sequential) - { - uint64_t addressIncrement = [=]() -> uint64_t { - if (generator->addressIncrement.isValid()) - return generator->addressIncrement.getValue(); - else - return 0x0; - }(); - - players.push_back(new TrafficGeneratorSequential(name.c_str(), playerClk, numRequests, - maxPendingReadRequests, maxPendingWriteRequests, - minAddress, maxAddress, rwRatio, addressIncrement, seed, - this)); - } - else if (generator->addressDistribution == DRAMSysConfiguration::AddressDistribution::Random) - { - players.push_back(new TrafficGeneratorRandom(name.c_str(), playerClk, numRequests, - maxPendingReadRequests, maxPendingWriteRequests, - minAddress, maxAddress, rwRatio, seed, this)); - } - - totalTransactions += numRequests; + totalTransactions += trafficGenerator->getTotalTransactions(); } else if (auto hammer = std::dynamic_pointer_cast(inititator)) { uint64_t numRequests = hammer->numRequests; uint64_t rowIncrement = hammer->rowIncrement; - players.push_back(new TrafficGeneratorHammer(name.c_str(), playerClk, numRequests, - rowIncrement, this)); + players.push_back(new TrafficGeneratorHammer(name.c_str(), *hammer, this)); + totalTransactions += numRequests; } } diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 27fa923e..0dba0717 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -41,50 +41,34 @@ using namespace sc_core; using namespace tlm; -TrafficGenerator::TrafficGenerator(const sc_module_name &name, - const sc_time &generatorClk, - uint64_t numRequests, - unsigned int maxPendingReadRequests, - unsigned int maxPendingWriteRequests, - float rwRatio, - unsigned int seed, - TraceSetup *setup) : - TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests), - generatorClk(generatorClk), numRequests(numRequests), rwRatio(rwRatio) +TrafficGeneratorIf::TrafficGeneratorIf(const sc_core::sc_module_name &name, TraceSetup *setup, + unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests) + : TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests) { burstLength = Configuration::getInstance().memSpec->burstLength; dataLength = Configuration::getInstance().memSpec->bytesPerBurst; - - randomGenerator = std::default_random_engine(seed); } -void TrafficGenerator::sendNextPayload() +void TrafficGeneratorIf::sendNextPayload() { - if (transactionsSent >= numRequests) - { - finished = true; - return; - } + prepareNextPayload(); - tlm_generic_payload *payload = setup->allocatePayload(); - payload->acquire(); + if (finished) + return; // TODO: column / burst breite uint64_t address = getNextAddress(); - tlm_command command; - if (randomRwDistribution(randomGenerator) < rwRatio) - { - command = tlm::TLM_READ_COMMAND; - pendingReadRequests++; - } - else - { - command = tlm::TLM_WRITE_COMMAND; - pendingWriteRequests++; - } + tlm_command command = getNextCommand(); + if (command == tlm::TLM_READ_COMMAND) + pendingReadRequests++; + else if (command == tlm::TLM_WRITE_COMMAND) + pendingWriteRequests++; + + tlm_generic_payload *payload = setup->allocatePayload(); + payload->acquire(); payload->set_address(address); payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); payload->set_dmi_allowed(false); @@ -93,6 +77,7 @@ void TrafficGenerator::sendNextPayload() payload->set_data_length(dataLength); payload->set_command(command); + sc_time generatorClk = getGeneratorClk(); sc_time sendingOffset; if (transactionsSent == 0) sendingOffset = SC_ZERO_TIME; @@ -104,65 +89,226 @@ void TrafficGenerator::sendNextPayload() transactionsSent++; PRINTDEBUGMESSAGE(name(), "Performing request #" + std::to_string(transactionsSent)); + payloadSent(); } -TrafficGeneratorRandom::TrafficGeneratorRandom(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - unsigned int maxPendingReadRequests, - unsigned int maxPendingWriteRequests, - uint64_t minAddress, - uint64_t maxAddress, - float rwRatio, - unsigned int seed, - TraceSetup *setup) : - TrafficGenerator(name, generatorClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, rwRatio, seed, - setup) +TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConfiguration::TraceGenerator &conf, + TraceSetup *setup) + : TrafficGeneratorIf(name, setup, evaluateMaxPendingReadRequests(conf), evaluateMaxPendingWriteRequests(conf)), + generatorClk(TrafficInitiator::evaluateGeneratorClk(conf)), conf(conf), + randomGenerator(std::default_random_engine(evaluateSeed(conf))) { + // Perform checks for all states + for (const auto &state : conf.states) + { + uint64_t minAddress = evaluateMinAddress(state.second); + uint64_t maxAddress = evaluateMaxAddress(state.second); + double rwRatio = state.second.rwRatio; + + if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) + SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); + + if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) + SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); + + if (maxAddress < minAddress) + SC_REPORT_FATAL("TrafficGenerator", "maxAddress is smaller than minAddress."); + + if (rwRatio < 0 || rwRatio > 1) + SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); + } + + uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); + uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); + randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); + + calculateTransitions(); +} + +void TrafficGenerator::calculateTransitions() +{ + unsigned int state = 0; + stateSequence.push_back(state); + + while (true) + { + auto transitionsIt = conf.transitions.equal_range(state); + float propabilityAccumulated = 0.0f; + std::map> transitionsDistribution; + + for (auto it = transitionsIt.first; it != transitionsIt.second; ++it) + { + float lowerLimit = propabilityAccumulated; + propabilityAccumulated += it->second.propability; + float upperLimit = propabilityAccumulated; + transitionsDistribution[it->second.to] = {lowerLimit, upperLimit}; + } + + if (propabilityAccumulated > 1.001f) + SC_REPORT_WARNING("TrafficGenerator", "Sum of transition propabilities greater than 1."); + + float random = randomDistribution(randomGenerator); + bool transitionFound = false; + + for (const auto &transition : transitionsDistribution) + { + auto to = transition.first; + auto limits = transition.second; + + if (limits.first < random && limits.second > random) + { + state = to; + stateSequence.push_back(state); + transitionFound = true; + break; + } + } + + if (transitionFound) + continue; + + break; + } + + stateIt = stateSequence.cbegin(); +} + +uint64_t TrafficGenerator::getTotalTransactions() const +{ + uint64_t totalTransactions = 0; + + for (auto state : stateSequence) + { + totalTransactions += conf.states.at(state).numRequests; + } + + return totalTransactions; +} + +void TrafficGenerator::transitionToNextState() +{ + ++stateIt; + + if (stateIt == stateSequence.cend()) + { + // No transition performed. + finished = true; + return; + } + + currentState = *stateIt; + + uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); + uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); randomAddressDistribution = std::uniform_int_distribution (minAddress, maxAddress); + + currentAddress = 0x00; + transactionsSentInCurrentState = 0; } -uint64_t TrafficGeneratorRandom::getNextAddress() +void TrafficGenerator::prepareNextPayload() { - return randomAddressDistribution(randomGenerator); + if (transactionsSentInCurrentState >= conf.states.at(currentState).numRequests) + transitionToNextState(); } -TrafficGeneratorSequential::TrafficGeneratorSequential(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - unsigned int maxPendingReadRequests, - unsigned int maxPendingWriteRequests, - uint64_t minAddress, - uint64_t maxAddress, - float rwRatio, - uint64_t addressIncrement, - unsigned int seed, - TraceSetup *setup) : - TrafficGenerator(name, generatorClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests, rwRatio, seed, - setup), minAddress(minAddress), maxAddress(maxAddress), addressIncrement(addressIncrement), - currentAddress(minAddress) +void TrafficGenerator::payloadSent() { + transactionsSentInCurrentState++; } -uint64_t TrafficGeneratorSequential::getNextAddress() +tlm::tlm_command TrafficGenerator::getNextCommand() { - uint64_t address = currentAddress; - currentAddress += addressIncrement; - if (currentAddress > maxAddress) - currentAddress = minAddress; - return address; + tlm_command command; + if (randomDistribution(randomGenerator) < conf.states.at(currentState).rwRatio) + command = tlm::TLM_READ_COMMAND; + else + command = tlm::TLM_WRITE_COMMAND; + + return command; } +sc_core::sc_time TrafficGenerator::getGeneratorClk() +{ + return generatorClk; +} + +uint64_t TrafficGenerator::getNextAddress() +{ + using DRAMSysConfiguration::AddressDistribution; + + uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); + uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); + + if (conf.states.at(currentState).addressDistribution == AddressDistribution::Sequential) + { + uint64_t addressIncrement = evaluateAddressIncrement(conf.states.at(currentState)); + + uint64_t address = currentAddress; + currentAddress += addressIncrement; + if (currentAddress > maxAddress) + currentAddress = minAddress; + return address; + } + else if (conf.states.at(currentState).addressDistribution == AddressDistribution::Random) + { + return randomAddressDistribution(randomGenerator); + } + else + { + return 0x00; + } +} + +unsigned int TrafficGenerator::evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf) +{ + if (conf.seed.isValid()) + return conf.seed.getValue(); + else + return 0; +} + +unsigned int TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state) +{ + if (state.minAddress.isValid()) + return state.minAddress.getValue(); + else + return 0x00; +} + +unsigned int TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state) +{ + if (state.maxAddress.isValid()) + return state.maxAddress.getValue(); + else + return Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; +} + +unsigned int TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state) +{ + if (state.addressIncrement.isValid()) + return state.addressIncrement.getValue(); + else + return 0x00; +} TrafficGeneratorHammer::TrafficGeneratorHammer(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - uint64_t rowIncrement, - TraceSetup *setup) : - TrafficGenerator(name, generatorClk, numRequests, 1, 1, 1.0f, 1, setup), rowIncrement(rowIncrement) + const DRAMSysConfiguration::TraceHammer &conf, TraceSetup *setup) + : TrafficGeneratorIf(name, setup, 1, 1), generatorClk(evaluateGeneratorClk(conf)), rowIncrement(conf.rowIncrement), + numRequests(conf.numRequests) { } +tlm::tlm_command TrafficGeneratorHammer::getNextCommand() +{ + return tlm::TLM_READ_COMMAND; +} + +sc_core::sc_time TrafficGeneratorHammer::getGeneratorClk() +{ + return generatorClk; +} + uint64_t TrafficGeneratorHammer::getNextAddress() { if (currentAddress == 0x0) @@ -172,3 +318,9 @@ uint64_t TrafficGeneratorHammer::getNextAddress() return currentAddress; } + +void TrafficGeneratorHammer::prepareNextPayload() +{ + if (transactionsSent >= numRequests) + finished = true; +} diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index 394e1d81..b4337ad9 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -44,90 +44,75 @@ #include "TrafficInitiator.h" #include "TraceSetup.h" -class TrafficGenerator : public TrafficInitiator -{ -protected: - TrafficGenerator(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - unsigned int maxPendingReadRequests, - unsigned int maxPendingWriteRequests, - float rwRatio, - unsigned int seed, - TraceSetup *setup); - - void sendNextPayload() override; - virtual uint64_t getNextAddress() = 0; - - std::default_random_engine randomGenerator; - -private: - sc_core::sc_time generatorClk; - uint64_t numRequests; - float rwRatio; - - std::uniform_real_distribution randomRwDistribution - = std::uniform_real_distribution(0.0f, 1.0f); -}; - -class TrafficGeneratorRandom final : public TrafficGenerator +class TrafficGeneratorIf : public TrafficInitiator { public: - TrafficGeneratorRandom(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - unsigned int maxPendingReadRequests, - unsigned int maxPendingWriteRequests, - uint64_t minAddress, - uint64_t maxAddress, - float rwRatio, - unsigned int seed, - TraceSetup *setup); + TrafficGeneratorIf(const sc_core::sc_module_name &name, TraceSetup *setup, unsigned int maxPendingReadRequests, + unsigned int maxPendingWriteRequests); private: - uint64_t getNextAddress() override; + void sendNextPayload() override; + virtual void prepareNextPayload(){}; + virtual uint64_t getNextAddress() = 0; + virtual tlm::tlm_command getNextCommand() = 0; + virtual sc_core::sc_time getGeneratorClk() = 0; + virtual void payloadSent(){}; +}; +class TrafficGenerator : public TrafficGeneratorIf +{ +public: + TrafficGenerator(const sc_core::sc_module_name &name, const DRAMSysConfiguration::TraceGenerator &conf, + TraceSetup *setup); + + uint64_t getTotalTransactions() const; + +private: + static unsigned int evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf); + static unsigned int evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state); + static unsigned int evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state); + static unsigned int evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state); + + void prepareNextPayload() override; + uint64_t getNextAddress() override; + tlm::tlm_command getNextCommand() override; + sc_core::sc_time getGeneratorClk() override; + void payloadSent() override; + + void calculateTransitions(); + void transitionToNextState(); + + sc_core::sc_time generatorClk; + + const DRAMSysConfiguration::TraceGenerator &conf; + unsigned int currentState = 0; + uint64_t currentAddress = 0x00; + uint64_t transactionsSentInCurrentState = 0; + + std::vector stateSequence; + std::vector::const_iterator stateIt; + + std::default_random_engine randomGenerator; + std::uniform_real_distribution randomDistribution = std::uniform_real_distribution(0.0f, 1.0f); std::uniform_int_distribution randomAddressDistribution; }; -class TrafficGeneratorSequential final : public TrafficGenerator +class TrafficGeneratorHammer final : public TrafficGeneratorIf { public: - TrafficGeneratorSequential(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - unsigned int maxPendingReadRequests, - unsigned int maxPendingWriteRequests, - uint64_t minAddress, - uint64_t maxAddress, - float rwRatio, - uint64_t addressIncrement, - unsigned int seed, - TraceSetup *setup); - -private: - uint64_t getNextAddress() override; - - uint64_t currentAddress; - uint64_t addressIncrement; - uint64_t minAddress; - uint64_t maxAddress; -}; - -class TrafficGeneratorHammer final : public TrafficGenerator -{ -public: - TrafficGeneratorHammer(const sc_core::sc_module_name &name, - const sc_core::sc_time &generatorClk, - uint64_t numRequests, - uint64_t rowIncrement, + TrafficGeneratorHammer(const sc_core::sc_module_name &name, const DRAMSysConfiguration::TraceHammer &conf, TraceSetup *setup); private: + void prepareNextPayload() override; uint64_t getNextAddress() override; + tlm::tlm_command getNextCommand() override; + sc_core::sc_time getGeneratorClk() override; + sc_core::sc_time generatorClk; uint64_t rowIncrement; uint64_t currentAddress = 0x0; + uint64_t numRequests; }; #endif // TRAFFICGENERATOR_H diff --git a/DRAMSys/simulator/TrafficInitiator.cpp b/DRAMSys/simulator/TrafficInitiator.cpp index 2a7c783e..644f1235 100644 --- a/DRAMSys/simulator/TrafficInitiator.cpp +++ b/DRAMSys/simulator/TrafficInitiator.cpp @@ -129,3 +129,26 @@ bool TrafficInitiator::nextPayloadSendable() const else return true; } + +sc_core::sc_time TrafficInitiator::evaluateGeneratorClk(const DRAMSysConfiguration::TrafficInitiator &conf) +{ + double frequencyMHz = conf.clkMhz; + sc_time playerClk = sc_time(1.0 / frequencyMHz, SC_US); + return playerClk; +} + +unsigned int TrafficInitiator::evaluateMaxPendingReadRequests(const DRAMSysConfiguration::TrafficInitiator &conf) +{ + if (conf.maxPendingReadRequests.isValid()) + return conf.maxPendingReadRequests.getValue(); + else + return 0; +} + +unsigned int TrafficInitiator::evaluateMaxPendingWriteRequests(const DRAMSysConfiguration::TrafficInitiator &conf) +{ + if (conf.maxPendingWriteRequests.isValid()) + return conf.maxPendingWriteRequests.getValue(); + else + return 0; +} diff --git a/DRAMSys/simulator/TrafficInitiator.h b/DRAMSys/simulator/TrafficInitiator.h index a53f91f0..78c19e25 100644 --- a/DRAMSys/simulator/TrafficInitiator.h +++ b/DRAMSys/simulator/TrafficInitiator.h @@ -62,6 +62,10 @@ public: virtual void sendNextPayload() = 0; protected: + static sc_core::sc_time evaluateGeneratorClk(const DRAMSysConfiguration::TrafficInitiator &conf); + static unsigned int evaluateMaxPendingReadRequests(const DRAMSysConfiguration::TrafficInitiator &conf); + static unsigned int evaluateMaxPendingWriteRequests(const DRAMSysConfiguration::TrafficInitiator &conf); + tlm_utils::peq_with_cb_and_phase payloadEventQueue; void terminate(); bool storageEnabled = false; @@ -73,8 +77,8 @@ protected: uint64_t transactionsSent = 0; unsigned int pendingReadRequests = 0; unsigned int pendingWriteRequests = 0; - unsigned int maxPendingReadRequests = 0; - unsigned int maxPendingWriteRequests = 0; + const unsigned int maxPendingReadRequests; + const unsigned int maxPendingWriteRequests; bool payloadPostponed = false; bool finished = false; From 2540c9d194f8728cf54f0fa4e6dc8554d5f8b6ef Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 3 Jan 2022 11:05:20 +0100 Subject: [PATCH 14/23] Implement maxTransactions for TrafficGenerator SM --- .../src/common/configuration/TraceSetup.cpp | 4 +++ .../src/common/configuration/TraceSetup.h | 1 + DRAMSys/simulator/TrafficGenerator.cpp | 33 +++++++++++++++---- DRAMSys/simulator/TrafficGenerator.h | 11 ++++--- 4 files changed, 38 insertions(+), 11 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index bba018c5..0963db41 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -60,6 +60,7 @@ void to_json(json &j, const TraceSetup &c) { initiator_j["type"] = "generator"; initiator_j["seed"] = generator->seed; + initiator_j["maxTransactions"] = generator->maxTransactions; // When there are less than 2 states, flatten out the json. if (generator->states.size() == 1) @@ -189,6 +190,9 @@ void from_json(const json &j, TraceSetup &c) if (initiator_j.contains("seed")) initiator_j.at("seed").get_to(generator->seed); + if (initiator_j.contains("maxTransactions")) + initiator_j.at("maxTransactions").get_to(generator->maxTransactions); + initiator = std::unique_ptr(generator); } else if (type == TrafficInitiatorType::Hammer) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 4fc804d8..bb861571 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -102,6 +102,7 @@ struct TraceGeneratorStateTransition struct TraceGenerator : public TrafficInitiator { Optional seed; + Optional maxTransactions; std::map states; std::multimap transitions; }; diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 0dba0717..e6ea1cf8 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -38,6 +38,8 @@ #include "TrafficGenerator.h" +#include + using namespace sc_core; using namespace tlm; @@ -95,7 +97,7 @@ void TrafficGeneratorIf::sendNextPayload() TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConfiguration::TraceGenerator &conf, TraceSetup *setup) : TrafficGeneratorIf(name, setup, evaluateMaxPendingReadRequests(conf), evaluateMaxPendingWriteRequests(conf)), - generatorClk(TrafficInitiator::evaluateGeneratorClk(conf)), conf(conf), + generatorClk(TrafficInitiator::evaluateGeneratorClk(conf)), conf(conf), maxTransactions(evaluateMaxTransactions(conf)), randomGenerator(std::default_random_engine(evaluateSeed(conf))) { // Perform checks for all states @@ -128,6 +130,7 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf void TrafficGenerator::calculateTransitions() { unsigned int state = 0; + uint64_t totalTransactions = 0; stateSequence.push_back(state); while (true) @@ -165,7 +168,12 @@ void TrafficGenerator::calculateTransitions() } if (transitionFound) - continue; + { + totalTransactions += conf.states.at(state).numRequests; + + if (totalTransactions < maxTransactions) + continue; + } break; } @@ -182,6 +190,9 @@ uint64_t TrafficGenerator::getTotalTransactions() const totalTransactions += conf.states.at(state).numRequests; } + if (totalTransactions > maxTransactions) + totalTransactions = maxTransactions; + return totalTransactions; } @@ -189,7 +200,7 @@ void TrafficGenerator::transitionToNextState() { ++stateIt; - if (stateIt == stateSequence.cend()) + if (stateIt == stateSequence.cend() || transactionsSent >= maxTransactions) { // No transition performed. finished = true; @@ -260,7 +271,7 @@ uint64_t TrafficGenerator::getNextAddress() } } -unsigned int TrafficGenerator::evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf) +uint64_t TrafficGenerator::evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf) { if (conf.seed.isValid()) return conf.seed.getValue(); @@ -268,7 +279,15 @@ unsigned int TrafficGenerator::evaluateSeed(const DRAMSysConfiguration::TraceGen return 0; } -unsigned int TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateMaxTransactions(const DRAMSysConfiguration::TraceGenerator &conf) +{ + if (conf.maxTransactions.isValid()) + return conf.maxTransactions.getValue(); + else + return std::numeric_limits::max(); +} + +uint64_t TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state) { if (state.minAddress.isValid()) return state.minAddress.getValue(); @@ -276,7 +295,7 @@ unsigned int TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::Tr return 0x00; } -unsigned int TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state) { if (state.maxAddress.isValid()) return state.maxAddress.getValue(); @@ -284,7 +303,7 @@ unsigned int TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::Tr return Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; } -unsigned int TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state) { if (state.addressIncrement.isValid()) return state.addressIncrement.getValue(); diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index b4337ad9..d2a25c90 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -68,10 +68,11 @@ public: uint64_t getTotalTransactions() const; private: - static unsigned int evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf); - static unsigned int evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state); - static unsigned int evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state); - static unsigned int evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state); + static uint64_t evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf); + static uint64_t evaluateMaxTransactions(const DRAMSysConfiguration::TraceGenerator &conf); + static uint64_t evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state); + static uint64_t evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state); + static uint64_t evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state); void prepareNextPayload() override; uint64_t getNextAddress() override; @@ -89,6 +90,8 @@ private: uint64_t currentAddress = 0x00; uint64_t transactionsSentInCurrentState = 0; + const uint64_t maxTransactions; + std::vector stateSequence; std::vector::const_iterator stateIt; From e1e2e9c0f9ebc08430fc49cef8d91a70802b9723 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 3 Jan 2022 15:20:03 +0100 Subject: [PATCH 15/23] Add clksPerRequest field to state definition --- .../library/src/common/configuration/TraceSetup.cpp | 5 +++++ .../library/src/common/configuration/TraceSetup.h | 1 + DRAMSys/simulator/TrafficGenerator.cpp | 12 +++++++++++- DRAMSys/simulator/TrafficGenerator.h | 4 ++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 0963db41..e6bc15d4 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -72,6 +72,7 @@ void to_json(json &j, const TraceSetup &c) initiator_j["addressIncrement"] = state.addressIncrement; initiator_j["minAddress"] = state.minAddress; initiator_j["maxAddress"] = state.maxAddress; + initiator_j["clksPerRequest"] = state.clksPerRequest; } else { @@ -87,6 +88,7 @@ void to_json(json &j, const TraceSetup &c) state_j["addressIncrement"] = state.second.addressIncrement; state_j["minAddress"] = state.second.minAddress; state_j["maxAddress"] = state.second.maxAddress; + state_j["clksPerRequest"] = state.second.clksPerRequest; remove_null_values(state_j); states_j.insert(states_j.end(), state_j); } @@ -155,6 +157,9 @@ void from_json(const json &j, TraceSetup &c) if (state_j.contains("maxAddress")) state_j.at("maxAddress").get_to(state.maxAddress); + if (state_j.contains("clksPerRequest")) + state_j.at("clksPerRequest").get_to(state.clksPerRequest); + // Default to 0 unsigned int id = 0; diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index bb861571..4340805d 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -91,6 +91,7 @@ struct TraceGeneratorState Optional addressIncrement; Optional minAddress; Optional maxAddress; + Optional clksPerRequest; }; struct TraceGeneratorStateTransition diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index e6ea1cf8..cf609702 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -84,7 +84,7 @@ void TrafficGeneratorIf::sendNextPayload() if (transactionsSent == 0) sendingOffset = SC_ZERO_TIME; else - sendingOffset = generatorClk - (sc_time_stamp() % generatorClk); + sendingOffset = (generatorClk * clksPerRequest()) - (sc_time_stamp() % generatorClk); // TODO: do not send two requests in the same cycle sendToTarget(*payload, tlm::BEGIN_REQ, sendingOffset); @@ -123,6 +123,7 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); + currentClksPerRequest = evaluateClksPerRequest(conf.states.at(currentState)); calculateTransitions(); } @@ -212,6 +213,7 @@ void TrafficGenerator::transitionToNextState() uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); randomAddressDistribution = std::uniform_int_distribution (minAddress, maxAddress); + currentClksPerRequest = evaluateClksPerRequest(conf.states.at(currentState)); currentAddress = 0x00; transactionsSentInCurrentState = 0; @@ -311,6 +313,14 @@ uint64_t TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration:: return 0x00; } +uint64_t TrafficGenerator::evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorState &state) +{ + if (state.clksPerRequest.isValid()) + return state.clksPerRequest.getValue(); + else + return 1; +} + TrafficGeneratorHammer::TrafficGeneratorHammer(const sc_core::sc_module_name &name, const DRAMSysConfiguration::TraceHammer &conf, TraceSetup *setup) : TrafficGeneratorIf(name, setup, 1, 1), generatorClk(evaluateGeneratorClk(conf)), rowIncrement(conf.rowIncrement), diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index d2a25c90..a258b6e2 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -57,6 +57,7 @@ private: virtual tlm::tlm_command getNextCommand() = 0; virtual sc_core::sc_time getGeneratorClk() = 0; virtual void payloadSent(){}; + virtual uint64_t clksPerRequest() { return 1; } }; class TrafficGenerator : public TrafficGeneratorIf @@ -73,12 +74,14 @@ private: static uint64_t evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state); static uint64_t evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state); static uint64_t evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state); + static uint64_t evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorState &state); void prepareNextPayload() override; uint64_t getNextAddress() override; tlm::tlm_command getNextCommand() override; sc_core::sc_time getGeneratorClk() override; void payloadSent() override; + uint64_t clksPerRequest() override { return currentClksPerRequest; }; void calculateTransitions(); void transitionToNextState(); @@ -88,6 +91,7 @@ private: const DRAMSysConfiguration::TraceGenerator &conf; unsigned int currentState = 0; uint64_t currentAddress = 0x00; + uint64_t currentClksPerRequest = 1; uint64_t transactionsSentInCurrentState = 0; const uint64_t maxTransactions; From 3dbb089dcb0d38629baa9ce56747786c0cc60e7d Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 5 Jan 2022 13:48:19 +0100 Subject: [PATCH 16/23] Add an idle state to the state machine A state with the field "idleClks" is a state that forces the TrafficGenerator to idle the specified amount of clocks. --- .../src/common/configuration/TraceSetup.cpp | 96 +++++++++++----- .../src/common/configuration/TraceSetup.h | 12 +- .../common/configuration/tests/simpletest.cpp | 36 ++++-- DRAMSys/simulator/TrafficGenerator.cpp | 103 +++++++++++------- DRAMSys/simulator/TrafficGenerator.h | 22 ++-- 5 files changed, 183 insertions(+), 86 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index e6bc15d4..fd509ee2 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -42,6 +42,10 @@ TrafficInitiator::~TrafficInitiator() { } +TraceGeneratorState::~TraceGeneratorState() +{ +} + void to_json(json &j, const TraceSetup &c) { // Create an empty array @@ -66,13 +70,21 @@ void to_json(json &j, const TraceSetup &c) if (generator->states.size() == 1) { const auto &state = generator->states[0]; - initiator_j["numRequests"] = state.numRequests; - initiator_j["rwRatio"] = state.rwRatio; - initiator_j["addressDistribution"] = state.addressDistribution; - initiator_j["addressIncrement"] = state.addressIncrement; - initiator_j["minAddress"] = state.minAddress; - initiator_j["maxAddress"] = state.maxAddress; - initiator_j["clksPerRequest"] = state.clksPerRequest; + + if (const auto trafficState = dynamic_cast(state.get())) + { + initiator_j["numRequests"] = trafficState->numRequests; + initiator_j["rwRatio"] = trafficState->rwRatio; + initiator_j["addressDistribution"] = trafficState->addressDistribution; + initiator_j["addressIncrement"] = trafficState->addressIncrement; + initiator_j["minAddress"] = trafficState->minAddress; + initiator_j["maxAddress"] = trafficState->maxAddress; + initiator_j["clksPerRequest"] = trafficState->clksPerRequest; + } + else if (const auto idleState = dynamic_cast(state.get())) + { + initiator_j["idleClks"] = idleState->idleClks; + } } else { @@ -82,13 +94,22 @@ void to_json(json &j, const TraceSetup &c) { json state_j; state_j["id"] = state.first; - state_j["numRequests"] = state.second.numRequests; - state_j["rwRatio"] = state.second.rwRatio; - state_j["addressDistribution"] = state.second.addressDistribution; - state_j["addressIncrement"] = state.second.addressIncrement; - state_j["minAddress"] = state.second.minAddress; - state_j["maxAddress"] = state.second.maxAddress; - state_j["clksPerRequest"] = state.second.clksPerRequest; + + if (const auto trafficState = dynamic_cast(state.second.get())) + { + state_j["numRequests"] = trafficState->numRequests; + state_j["rwRatio"] = trafficState->rwRatio; + state_j["addressDistribution"] = trafficState->addressDistribution; + state_j["addressIncrement"] = trafficState->addressIncrement; + state_j["minAddress"] = trafficState->minAddress; + state_j["maxAddress"] = trafficState->maxAddress; + state_j["clksPerRequest"] = trafficState->clksPerRequest; + } + else if (const auto idleState = dynamic_cast(state.second.get())) + { + state_j["idleClks"] = idleState->idleClks; + } + remove_null_values(state_j); states_j.insert(states_j.end(), state_j); } @@ -140,25 +161,40 @@ void from_json(const json &j, TraceSetup &c) { TraceGenerator *generator = new TraceGenerator; - auto process_state = [](const json &state_j) -> std::pair + auto process_state = [](const json &state_j) -> std::pair> { - TraceGeneratorState state{}; + std::unique_ptr state; - state_j.at("numRequests").get_to(state.numRequests); - state_j.at("rwRatio").get_to(state.rwRatio); - state_j.at("addressDistribution").get_to(state.addressDistribution); + if (state_j.contains("idleClks")) + { + // Idle state + auto idleState = new TraceGeneratorIdleState; + state_j.at("idleClks").get_to(idleState->idleClks); - if (state_j.contains("addressIncrement")) - state_j.at("addressIncrement").get_to(state.addressIncrement); + state = std::unique_ptr(idleState); + } + else + { + // Traffic state + auto trafficState = new TraceGeneratorTrafficState; + state_j.at("numRequests").get_to(trafficState->numRequests); + state_j.at("rwRatio").get_to(trafficState->rwRatio); + state_j.at("addressDistribution").get_to(trafficState->addressDistribution); - if (state_j.contains("minAddress")) - state_j.at("minAddress").get_to(state.minAddress); + if (state_j.contains("addressIncrement")) + state_j.at("addressIncrement").get_to(trafficState->addressIncrement); - if (state_j.contains("maxAddress")) - state_j.at("maxAddress").get_to(state.maxAddress); + if (state_j.contains("minAddress")) + state_j.at("minAddress").get_to(trafficState->minAddress); - if (state_j.contains("clksPerRequest")) - state_j.at("clksPerRequest").get_to(state.clksPerRequest); + if (state_j.contains("maxAddress")) + state_j.at("maxAddress").get_to(trafficState->maxAddress); + + if (state_j.contains("clksPerRequest")) + state_j.at("clksPerRequest").get_to(trafficState->clksPerRequest); + + state = std::unique_ptr(trafficState); + } // Default to 0 unsigned int id = 0; @@ -166,7 +202,7 @@ void from_json(const json &j, TraceSetup &c) if (state_j.contains("id")) id = state_j.at("id"); - return {id, state}; + return {id, std::move(state)}; }; if (initiator_j.contains("states")) @@ -174,7 +210,7 @@ void from_json(const json &j, TraceSetup &c) for (const auto &state_j : initiator_j.at("states")) { auto state = process_state(state_j); - generator->states[state.first] = state.second; + generator->states[state.first] = std::move(state.second); } for (const auto &transition_j : initiator_j.at("transitions")) @@ -189,7 +225,7 @@ void from_json(const json &j, TraceSetup &c) else // Only one state will be created { auto state = process_state(initiator_j); - generator->states[state.first] = state.second; + generator->states[state.first] = std::move(state.second); } if (initiator_j.contains("seed")) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 4340805d..d128dc36 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -84,6 +84,11 @@ struct TracePlayer : public TrafficInitiator }; struct TraceGeneratorState +{ + virtual ~TraceGeneratorState() = 0; +}; + +struct TraceGeneratorTrafficState : public TraceGeneratorState { uint64_t numRequests; double rwRatio; @@ -94,6 +99,11 @@ struct TraceGeneratorState Optional clksPerRequest; }; +struct TraceGeneratorIdleState : public TraceGeneratorState +{ + uint64_t idleClks; +}; + struct TraceGeneratorStateTransition { unsigned int to; @@ -104,7 +114,7 @@ struct TraceGenerator : public TrafficInitiator { Optional seed; Optional maxTransactions; - std::map states; + std::map> states; std::multimap transitions; }; diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 50716769..bd272ae4 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -111,10 +111,16 @@ std::unique_ptr getTraceGeneratorOneState( gen->clkMhz = 100; gen->name = "MyTestGen"; - DRAMSysConfiguration::TraceGeneratorState state0{1000, 0.5, DRAMSysConfiguration::AddressDistribution::Random, - {}, {}, {}}; + auto state0 = new DRAMSysConfiguration::TraceGeneratorTrafficState; + state0->numRequests = 1000; + state0->rwRatio = 0.5; + state0->addressDistribution = DRAMSysConfiguration::AddressDistribution::Random; + state0->addressIncrement = {}; + state0->minAddress = {}; + state0->maxAddress = {}; + state0->clksPerRequest = {}; - gen->states[0] = state0; + gen->states[0] = std::unique_ptr(state0); return std::unique_ptr(gen); } @@ -127,14 +133,26 @@ std::unique_ptr getTraceGeneratorMultipleS gen->name = "MyTestGen"; gen->maxPendingReadRequests = 8; - DRAMSysConfiguration::TraceGeneratorState state0{1000, 0.5, DRAMSysConfiguration::AddressDistribution::Sequential, - {256}, {}, {1024}}; + auto state0 = new DRAMSysConfiguration::TraceGeneratorTrafficState; + state0->numRequests = 1000; + state0->rwRatio = 0.5; + state0->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; + state0->addressIncrement = 256; + state0->minAddress = {}; + state0->maxAddress = 1024; + state0->clksPerRequest = {}; - DRAMSysConfiguration::TraceGeneratorState state1{ - 100, 0.75, DRAMSysConfiguration::AddressDistribution::Sequential, {512}, {1024}, {2048}}; + auto state1 = new DRAMSysConfiguration::TraceGeneratorTrafficState; + state1->numRequests = 100; + state1->rwRatio = 0.75; + state1->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; + state1->addressIncrement = 512; + state1->minAddress = 1024; + state1->maxAddress = 2048; + state1->clksPerRequest = {}; - gen->states[0] = state0; - gen->states[1] = state1; + gen->states[0] = std::unique_ptr(state0); + gen->states[1] = std::unique_ptr(state1); DRAMSysConfiguration::TraceGeneratorStateTransition transistion0{1, 1.0}; diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index cf609702..ad56dc47 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -82,9 +82,9 @@ void TrafficGeneratorIf::sendNextPayload() sc_time generatorClk = getGeneratorClk(); sc_time sendingOffset; if (transactionsSent == 0) - sendingOffset = SC_ZERO_TIME; + sendingOffset = SC_ZERO_TIME + generatorClk * clksToIdle(); else - sendingOffset = (generatorClk * clksPerRequest()) - (sc_time_stamp() % generatorClk); + sendingOffset = (generatorClk * clksPerRequest()) - (sc_time_stamp() % generatorClk) + generatorClk * clksToIdle(); // TODO: do not send two requests in the same cycle sendToTarget(*payload, tlm::BEGIN_REQ, sendingOffset); @@ -103,27 +103,33 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf // Perform checks for all states for (const auto &state : conf.states) { - uint64_t minAddress = evaluateMinAddress(state.second); - uint64_t maxAddress = evaluateMaxAddress(state.second); - double rwRatio = state.second.rwRatio; + if (auto trafficState = dynamic_cast(state.second.get())) + { + uint64_t minAddress = evaluateMinAddress(*trafficState); + uint64_t maxAddress = evaluateMaxAddress(*trafficState); + double rwRatio = (*trafficState).rwRatio; - if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) - SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); + if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) + SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); - if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) - SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); + if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1) + SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); - if (maxAddress < minAddress) - SC_REPORT_FATAL("TrafficGenerator", "maxAddress is smaller than minAddress."); + if (maxAddress < minAddress) + SC_REPORT_FATAL("TrafficGenerator", "maxAddress is smaller than minAddress."); - if (rwRatio < 0 || rwRatio > 1) - SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); + if (rwRatio < 0 || rwRatio > 1) + SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); + } } - uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); - uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); - randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); - currentClksPerRequest = evaluateClksPerRequest(conf.states.at(currentState)); + if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) + { + uint64_t minAddress = evaluateMinAddress(*trafficState); + uint64_t maxAddress = evaluateMaxAddress(*trafficState); + randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); + currentClksPerRequest = evaluateClksPerRequest(*trafficState); + } calculateTransitions(); } @@ -170,7 +176,8 @@ void TrafficGenerator::calculateTransitions() if (transitionFound) { - totalTransactions += conf.states.at(state).numRequests; + if (auto trafficState = dynamic_cast(conf.states.at(state).get())) + totalTransactions += trafficState->numRequests; if (totalTransactions < maxTransactions) continue; @@ -188,7 +195,8 @@ uint64_t TrafficGenerator::getTotalTransactions() const for (auto state : stateSequence) { - totalTransactions += conf.states.at(state).numRequests; + if (auto trafficState = dynamic_cast(conf.states.at(state).get())) + totalTransactions += trafficState->numRequests; } if (totalTransactions > maxTransactions) @@ -210,10 +218,19 @@ void TrafficGenerator::transitionToNextState() currentState = *stateIt; - uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); - uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); - randomAddressDistribution = std::uniform_int_distribution (minAddress, maxAddress); - currentClksPerRequest = evaluateClksPerRequest(conf.states.at(currentState)); + if (auto idleState = dynamic_cast(conf.states.at(currentState).get())) + { + currentClksToIdle += idleState->idleClks; + transitionToNextState(); + return; + } + else if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) + { + uint64_t minAddress = evaluateMinAddress(*trafficState); + uint64_t maxAddress = evaluateMaxAddress(*trafficState); + randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); + currentClksPerRequest = evaluateClksPerRequest(*trafficState); + } currentAddress = 0x00; transactionsSentInCurrentState = 0; @@ -221,19 +238,28 @@ void TrafficGenerator::transitionToNextState() void TrafficGenerator::prepareNextPayload() { - if (transactionsSentInCurrentState >= conf.states.at(currentState).numRequests) - transitionToNextState(); + if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) + { + if (transactionsSentInCurrentState >= trafficState->numRequests) + transitionToNextState(); + } } void TrafficGenerator::payloadSent() { + // Reset clks to idle. + currentClksToIdle = 0; + transactionsSentInCurrentState++; } tlm::tlm_command TrafficGenerator::getNextCommand() { + // An idle state should never reach this method. + auto state = static_cast(conf.states.at(currentState).get()); + tlm_command command; - if (randomDistribution(randomGenerator) < conf.states.at(currentState).rwRatio) + if (randomDistribution(randomGenerator) < state->rwRatio) command = tlm::TLM_READ_COMMAND; else command = tlm::TLM_WRITE_COMMAND; @@ -241,7 +267,7 @@ tlm::tlm_command TrafficGenerator::getNextCommand() return command; } -sc_core::sc_time TrafficGenerator::getGeneratorClk() +sc_core::sc_time TrafficGenerator::getGeneratorClk() const { return generatorClk; } @@ -250,12 +276,15 @@ uint64_t TrafficGenerator::getNextAddress() { using DRAMSysConfiguration::AddressDistribution; - uint64_t minAddress = evaluateMinAddress(conf.states.at(currentState)); - uint64_t maxAddress = evaluateMaxAddress(conf.states.at(currentState)); + // An idle state should never reach this method. + auto state = static_cast(conf.states.at(currentState).get()); - if (conf.states.at(currentState).addressDistribution == AddressDistribution::Sequential) + uint64_t minAddress = evaluateMinAddress(*state); + uint64_t maxAddress = evaluateMaxAddress(*state); + + if (state->addressDistribution == AddressDistribution::Sequential) { - uint64_t addressIncrement = evaluateAddressIncrement(conf.states.at(currentState)); + uint64_t addressIncrement = evaluateAddressIncrement(*state); uint64_t address = currentAddress; currentAddress += addressIncrement; @@ -263,7 +292,7 @@ uint64_t TrafficGenerator::getNextAddress() currentAddress = minAddress; return address; } - else if (conf.states.at(currentState).addressDistribution == AddressDistribution::Random) + else if (state->addressDistribution == AddressDistribution::Random) { return randomAddressDistribution(randomGenerator); } @@ -289,7 +318,7 @@ uint64_t TrafficGenerator::evaluateMaxTransactions(const DRAMSysConfiguration::T return std::numeric_limits::max(); } -uint64_t TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) { if (state.minAddress.isValid()) return state.minAddress.getValue(); @@ -297,7 +326,7 @@ uint64_t TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceG return 0x00; } -uint64_t TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) { if (state.maxAddress.isValid()) return state.maxAddress.getValue(); @@ -305,7 +334,7 @@ uint64_t TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceG return Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; } -uint64_t TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) { if (state.addressIncrement.isValid()) return state.addressIncrement.getValue(); @@ -313,7 +342,7 @@ uint64_t TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration:: return 0x00; } -uint64_t TrafficGenerator::evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorState &state) +uint64_t TrafficGenerator::evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) { if (state.clksPerRequest.isValid()) return state.clksPerRequest.getValue(); @@ -333,7 +362,7 @@ tlm::tlm_command TrafficGeneratorHammer::getNextCommand() return tlm::TLM_READ_COMMAND; } -sc_core::sc_time TrafficGeneratorHammer::getGeneratorClk() +sc_core::sc_time TrafficGeneratorHammer::getGeneratorClk() const { return generatorClk; } diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index a258b6e2..f27c7bba 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -55,9 +55,10 @@ private: virtual void prepareNextPayload(){}; virtual uint64_t getNextAddress() = 0; virtual tlm::tlm_command getNextCommand() = 0; - virtual sc_core::sc_time getGeneratorClk() = 0; + virtual sc_core::sc_time getGeneratorClk() const = 0; virtual void payloadSent(){}; - virtual uint64_t clksPerRequest() { return 1; } + virtual uint64_t clksPerRequest() const { return 1; } + virtual uint64_t clksToIdle() const { return 0; } }; class TrafficGenerator : public TrafficGeneratorIf @@ -71,17 +72,18 @@ public: private: static uint64_t evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf); static uint64_t evaluateMaxTransactions(const DRAMSysConfiguration::TraceGenerator &conf); - static uint64_t evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorState &state); - static uint64_t evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorState &state); - static uint64_t evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorState &state); - static uint64_t evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorState &state); + static uint64_t evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); + static uint64_t evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); + static uint64_t evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); + static uint64_t evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); void prepareNextPayload() override; uint64_t getNextAddress() override; tlm::tlm_command getNextCommand() override; - sc_core::sc_time getGeneratorClk() override; + sc_core::sc_time getGeneratorClk() const override; void payloadSent() override; - uint64_t clksPerRequest() override { return currentClksPerRequest; }; + uint64_t clksPerRequest() const override { return currentClksPerRequest; }; + uint64_t clksToIdle() const override { return currentClksToIdle; } void calculateTransitions(); void transitionToNextState(); @@ -96,6 +98,8 @@ private: const uint64_t maxTransactions; + uint64_t currentClksToIdle = 0; + std::vector stateSequence; std::vector::const_iterator stateIt; @@ -114,7 +118,7 @@ private: void prepareNextPayload() override; uint64_t getNextAddress() override; tlm::tlm_command getNextCommand() override; - sc_core::sc_time getGeneratorClk() override; + sc_core::sc_time getGeneratorClk() const override; sc_core::sc_time generatorClk; uint64_t rowIncrement; From 5c0b08246e93f4ebd6b739ee2a819f0790504e3d Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 12 Jan 2022 15:51:07 +0100 Subject: [PATCH 17/23] Introduce a event-based system to start statemachines State machines can now optionally be started by other state machines when they transition into a certain state. The field "notify" was added to send a event with the specified name when the transition happens. The other state machine can listen to those events by adding the "idleUntil" field to the definition. --- .../src/common/configuration/TraceSetup.cpp | 9 ++++ .../src/common/configuration/TraceSetup.h | 2 + DRAMSys/simulator/TraceSetup.cpp | 42 ++++++++++++++++++- DRAMSys/simulator/TrafficGenerator.cpp | 42 +++++++++++++++++++ DRAMSys/simulator/TrafficGenerator.h | 21 +++++++++- DRAMSys/simulator/TrafficInitiator.cpp | 2 +- 6 files changed, 114 insertions(+), 4 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index fd509ee2..c5bb2492 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -65,6 +65,7 @@ void to_json(json &j, const TraceSetup &c) initiator_j["type"] = "generator"; initiator_j["seed"] = generator->seed; initiator_j["maxTransactions"] = generator->maxTransactions; + initiator_j["idleUntil"] = generator->idleUntil; // When there are less than 2 states, flatten out the json. if (generator->states.size() == 1) @@ -80,6 +81,7 @@ void to_json(json &j, const TraceSetup &c) initiator_j["minAddress"] = trafficState->minAddress; initiator_j["maxAddress"] = trafficState->maxAddress; initiator_j["clksPerRequest"] = trafficState->clksPerRequest; + initiator_j["notify"] = trafficState->notify; } else if (const auto idleState = dynamic_cast(state.get())) { @@ -104,6 +106,7 @@ void to_json(json &j, const TraceSetup &c) state_j["minAddress"] = trafficState->minAddress; state_j["maxAddress"] = trafficState->maxAddress; state_j["clksPerRequest"] = trafficState->clksPerRequest; + state_j["notify"] = trafficState->notify; } else if (const auto idleState = dynamic_cast(state.second.get())) { @@ -193,6 +196,9 @@ void from_json(const json &j, TraceSetup &c) if (state_j.contains("clksPerRequest")) state_j.at("clksPerRequest").get_to(trafficState->clksPerRequest); + if (state_j.contains("notify")) + state_j.at("notify").get_to(trafficState->notify); + state = std::unique_ptr(trafficState); } @@ -234,6 +240,9 @@ void from_json(const json &j, TraceSetup &c) if (initiator_j.contains("maxTransactions")) initiator_j.at("maxTransactions").get_to(generator->maxTransactions); + if (initiator_j.contains("idleUntil")) + initiator_j.at("idleUntil").get_to(generator->idleUntil); + initiator = std::unique_ptr(generator); } else if (type == TrafficInitiatorType::Hammer) diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index d128dc36..5b61fef0 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -97,6 +97,7 @@ struct TraceGeneratorTrafficState : public TraceGeneratorState Optional minAddress; Optional maxAddress; Optional clksPerRequest; + Optional notify; }; struct TraceGeneratorIdleState : public TraceGeneratorState @@ -116,6 +117,7 @@ struct TraceGenerator : public TrafficInitiator Optional maxTransactions; std::map> states; std::multimap transitions; + Optional idleUntil; }; struct TraceHammer : public TrafficInitiator diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 966fff87..08373c62 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -35,10 +35,12 @@ * Derek Christ */ -#include #include "TraceSetup.h" #include "StlPlayer.h" #include "TrafficGenerator.h" +#include +#include +#include using namespace sc_core; using namespace tlm; @@ -119,6 +121,44 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, } } + for (const auto &inititatorConf : traceSetup.initiators) + { + if (auto generatorConf = std::dynamic_pointer_cast(inititatorConf)) + { + if (generatorConf->idleUntil.isValid()) + { + auto idleUntil = generatorConf->idleUntil.getValue(); + + const std::string name = generatorConf->name; + auto listenerIt = + std::find_if(players.begin(), players.end(), + [&name](const TrafficInitiator *initiator) { return initiator->name() == name; }); + + // Should be found + auto listener = dynamic_cast(*listenerIt); + + auto notifierIt = + std::find_if(players.begin(), players.end(), + [&idleUntil](const TrafficInitiator *initiator) + { + if (auto generator = dynamic_cast(initiator)) + { + if (generator->hasStateTransitionEvent(idleUntil)) + return true; + } + + return false; + }); + + if (notifierIt == players.end()) + SC_REPORT_FATAL("TraceSetup", "Event to listen on not found."); + + auto notifier = dynamic_cast(*notifierIt); + listener->waitUntil(¬ifier->getStateTransitionEvent(idleUntil)); + } + } + } + remainingTransactions = totalTransactions; numberOfTrafficInitiators = players.size(); } diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index ad56dc47..539b0f6f 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -120,6 +120,13 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf if (rwRatio < 0 || rwRatio > 1) SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); + + if (trafficState->notify.isValid()) + { + auto eventName = trafficState->notify.getValue(); + stateTranstitionEvents.emplace(std::piecewise_construct, std::forward_as_tuple(eventName), + std::forward_as_tuple(eventName.c_str(), state.first)); + } } } @@ -189,6 +196,26 @@ void TrafficGenerator::calculateTransitions() stateIt = stateSequence.cbegin(); } +bool TrafficGenerator::hasStateTransitionEvent(const std::string &eventName) const +{ + auto it = stateTranstitionEvents.find(eventName); + + if (it == stateTranstitionEvents.end()) + return false; + + return true; +} + +const sc_core::sc_event &TrafficGenerator::getStateTransitionEvent(const std::string &eventName) const +{ + auto it = stateTranstitionEvents.find(eventName); + + if (it == stateTranstitionEvents.end()) + SC_REPORT_FATAL("TraceSetup", "StateTransitionEvent not found."); + + return it->second.event; +} + uint64_t TrafficGenerator::getTotalTransactions() const { uint64_t totalTransactions = 0; @@ -205,6 +232,11 @@ uint64_t TrafficGenerator::getTotalTransactions() const return totalTransactions; } +void TrafficGenerator::waitUntil(const sc_core::sc_event *ev) +{ + startEvent = ev; +} + void TrafficGenerator::transitionToNextState() { ++stateIt; @@ -218,6 +250,13 @@ void TrafficGenerator::transitionToNextState() currentState = *stateIt; + // Notify + for (auto &it : stateTranstitionEvents) + { + if (it.second.stateId == currentState) + it.second.event.notify(); + } + if (auto idleState = dynamic_cast(conf.states.at(currentState).get())) { currentClksToIdle += idleState->idleClks; @@ -238,6 +277,9 @@ void TrafficGenerator::transitionToNextState() void TrafficGenerator::prepareNextPayload() { + if (startEvent && transactionsSent == 0) + wait(*startEvent); + if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) { if (transactionsSentInCurrentState >= trafficState->numRequests) diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index f27c7bba..16e957ea 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -39,11 +39,12 @@ #ifndef TRAFFICGENERATOR_H #define TRAFFICGENERATOR_H -#include - #include "TrafficInitiator.h" #include "TraceSetup.h" +#include +#include + class TrafficGeneratorIf : public TrafficInitiator { public: @@ -68,6 +69,9 @@ public: TraceSetup *setup); uint64_t getTotalTransactions() const; + void waitUntil(const sc_core::sc_event *ev); + bool hasStateTransitionEvent(const std::string &eventName) const; + const sc_core::sc_event &getStateTransitionEvent(const std::string &eventName) const; private: static uint64_t evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf); @@ -103,6 +107,19 @@ private: std::vector stateSequence; std::vector::const_iterator stateIt; + struct EventPair + { + EventPair(const std::string &name, unsigned int id) : event(name.c_str()), stateId(id) + { + } + sc_core::sc_event event; + unsigned int stateId; + }; + std::map stateTranstitionEvents; + + bool idleAtStart = false; + const sc_core::sc_event *startEvent = nullptr; + std::default_random_engine randomGenerator; std::uniform_real_distribution randomDistribution = std::uniform_real_distribution(0.0f, 1.0f); std::uniform_int_distribution randomAddressDistribution; diff --git a/DRAMSys/simulator/TrafficInitiator.cpp b/DRAMSys/simulator/TrafficInitiator.cpp index 644f1235..8783fcc9 100644 --- a/DRAMSys/simulator/TrafficInitiator.cpp +++ b/DRAMSys/simulator/TrafficInitiator.cpp @@ -49,7 +49,7 @@ TrafficInitiator::TrafficInitiator(const sc_module_name &name, TraceSetup *setup setup(setup), maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests) { - SC_METHOD(sendNextPayload); + SC_THREAD(sendNextPayload); iSocket.register_nb_transport_bw(this, &TrafficInitiator::nb_transport_bw); if (Configuration::getInstance().storeMode == Configuration::StoreMode::NoStorage) From 55ad6639f2b209d590454e2d595ea8bdffca9fc5 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 25 Jan 2022 15:31:17 +0100 Subject: [PATCH 18/23] Fix a bug where more transactions were simulated than specified --- DRAMSys/simulator/TrafficGenerator.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 539b0f6f..5d15235d 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -277,6 +277,12 @@ void TrafficGenerator::transitionToNextState() void TrafficGenerator::prepareNextPayload() { + if (transactionsSent >= maxTransactions) + { + finished = true; + return; + } + if (startEvent && transactionsSent == 0) wait(*startEvent); From 1b5b40d987076b2b386a43049a0406f0ec671d20 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 16 Feb 2022 16:10:06 +0100 Subject: [PATCH 19/23] Update authors --- DRAMSys/library/src/simulation/TemperatureController.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/DRAMSys/library/src/simulation/TemperatureController.cpp b/DRAMSys/library/src/simulation/TemperatureController.cpp index 3634663f..f66469c9 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.cpp +++ b/DRAMSys/library/src/simulation/TemperatureController.cpp @@ -32,6 +32,7 @@ * Authors: * Eder F. Zulian * Matthias Jung + * Derek Christ */ #include From ce94141a3f8a7a65ed314c1d056b1dff1ab00473 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 22 Feb 2022 10:24:35 +0100 Subject: [PATCH 20/23] Fix some bugs in configuration library --- .../common/configuration/AddressMapping.cpp | 17 ++++++---- .../src/common/configuration/AddressMapping.h | 6 ++-- .../src/common/configuration/McConfig.cpp | 34 ++++++++++++++++++- .../src/common/configuration/McConfig.h | 15 ++------ .../src/common/configuration/SimConfig.h | 2 +- .../common/configuration/tests/simpletest.cpp | 8 ++--- .../src/configuration/Configuration.cpp | 8 ++--- .../src/configuration/memspec/MemSpecDDR5.cpp | 4 +-- .../library/src/simulation/AddressDecoder.cpp | 20 +++++++++-- 9 files changed, 77 insertions(+), 37 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.cpp b/DRAMSys/library/src/common/configuration/AddressMapping.cpp index c3a57881..1d39e875 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.cpp +++ b/DRAMSys/library/src/common/configuration/AddressMapping.cpp @@ -45,13 +45,11 @@ void to_json(json &j, const AddressMapping &m) json congen = json{}; congen = json{{"BYTE_BIT", m.byteBits}, - {"COLUMN_BIT", m.coloumnBits}, - {"BANKGROUP_BIT", m.bankGroupBits}, + {"COLUMN_BIT", m.columnBits}, {"BANK_BIT", m.bankBits}, + {"BANKGROUP_BIT", m.bankGroupBits}, {"ROW_BIT", m.rowBits}, {"CHANNEL_BIT", m.channelBits}, - {"BYTE_BIT", m.byteBits}, - {"BANKGROUP_BIT", m.bankGroupBits}, {"RANK_BIT", m.rankBits}, {"XOR", m.xorBits}}; @@ -70,9 +68,14 @@ void from_json(const json &j, AddressMapping &m) else congen = j_addressmapping["CONGEN"]; - congen.at("COLUMN_BIT").get_to(m.coloumnBits); - congen.at("BANK_BIT").get_to(m.bankBits); - congen.at("ROW_BIT").get_to(m.rowBits); + if (congen.contains("COLUMN_BIT")) + congen.at("COLUMN_BIT").get_to(m.columnBits); + + if (congen.contains("BANK_BIT")) + congen.at("BANK_BIT").get_to(m.bankBits); + + if (congen.contains("ROW_BIT")) + congen.at("ROW_BIT").get_to(m.rowBits); if (congen.contains("RANK_BIT")) congen.at("RANK_BIT").get_to(m.rankBits); diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index 72884f1f..d0ee8082 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -58,10 +58,10 @@ void from_json(const json &j, XorPair &x); struct AddressMapping { Optional> byteBits; - std::vector coloumnBits; - std::vector bankBits; + Optional> columnBits; + Optional> bankBits; Optional> bankGroupBits; - std::vector rowBits; + Optional> rowBits; Optional> channelBits; Optional> rankBits; Optional> xorBits; diff --git a/DRAMSys/library/src/common/configuration/McConfig.cpp b/DRAMSys/library/src/common/configuration/McConfig.cpp index 945388d0..1abce2f0 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.cpp +++ b/DRAMSys/library/src/common/configuration/McConfig.cpp @@ -70,7 +70,7 @@ void from_json(const json &j, McConfig &c) if (j_mcconfig.contains("PagePolicy")) j_mcconfig.at("PagePolicy").get_to(c.pagePolicy); - if (j_mcconfig.contains("PagePolicy")) + if (j_mcconfig.contains("Scheduler")) j_mcconfig.at("Scheduler").get_to(c.scheduler); if (j_mcconfig.contains("SchedulerBuffer")) @@ -135,6 +135,38 @@ void from_json(const json &j, McConfig &c) invalidateEnum(c.arbiter); } +void to_json(json &j, const RefreshPolicy &r) +{ + if (r == RefreshPolicy::NoRefresh) + j = "NoRefresh"; + else if (r == RefreshPolicy::AllBank) + j = "AllBank"; + else if (r == RefreshPolicy::PerBank) + j = "PerBank"; + else if (r == RefreshPolicy::Per2Bank) + j = "Per2Bank"; + else if (r == RefreshPolicy::SameBank) + j = "SameBank"; + else + j = nullptr; +} + +void from_json(const json &j, RefreshPolicy &r) +{ + if (j == "NoRefresh") + r = RefreshPolicy::NoRefresh; + else if (j == "AllBank" || j == "Rankwise") + r = RefreshPolicy::AllBank; + else if (j == "PerBank" || j == "Bankwise") + r = RefreshPolicy::PerBank; + else if (j == "SameBank" || j == "Groupwise") + r = RefreshPolicy::SameBank; + else if (j == "Per2Bank") + r = RefreshPolicy::Per2Bank; + else + r = RefreshPolicy::Invalid; +} + void from_dump(const std::string &dump, McConfig &c) { json json_mcconfig = json::parse(dump).at("mcconfig"); diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index abc7bcd0..7ad3329c 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -119,21 +119,9 @@ enum class RefreshPolicy PerBank, Per2Bank, SameBank, - Rankwise, - Bankwise, - Groupwise, Invalid = -1 }; -NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicy, {{RefreshPolicy::Invalid, nullptr}, - {RefreshPolicy::NoRefresh, "NoRefresh"}, - {RefreshPolicy::AllBank, "AllBank"}, - {RefreshPolicy::PerBank, "PerBank"}, - {RefreshPolicy::Per2Bank, "Per2Bank"}, - {RefreshPolicy::Rankwise, "Rankwise"}, - {RefreshPolicy::Bankwise, "Bankwise"}, - {RefreshPolicy::Groupwise, "Groupwise"}}) - enum class PowerDownPolicy { NoPowerDown, @@ -184,6 +172,9 @@ struct McConfig void to_json(json &j, const McConfig &c); void from_json(const json &j, McConfig &c); +void to_json(json &j, const RefreshPolicy &r); +void from_json(const json &j, RefreshPolicy &r); + void from_dump(const std::string &dump, McConfig &c); std::string dump(const McConfig &c, unsigned int indentation = -1); diff --git a/DRAMSys/library/src/common/configuration/SimConfig.h b/DRAMSys/library/src/common/configuration/SimConfig.h index fb5688a3..7c189909 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.h +++ b/DRAMSys/library/src/common/configuration/SimConfig.h @@ -61,7 +61,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(StoreMode, {{StoreMode::Invalid, nullptr}, struct SimConfig { - Optional addressOffset; + Optional addressOffset; Optional checkTLM2Protocol; Optional databaseRecording; Optional debug; diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index bd272ae4..520791f0 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -42,10 +42,10 @@ using json = nlohmann::json; DRAMSysConfiguration::AddressMapping getAddressMapping() { return DRAMSysConfiguration::AddressMapping{{{0, 1}}, - {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, - {16}, + {{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}}, + {{16}}, {{13, 14, 15}}, - {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}, + {{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}}, {{33}}, {{}}, {{}}}; @@ -71,7 +71,7 @@ DRAMSysConfiguration::McConfig getMcConfig() DRAMSysConfiguration::SimConfig getSimConfig() { return DRAMSysConfiguration::SimConfig{ - 0, false, true, false, DRAMSysConfiguration::ECCControllerMode::Disabled, false, {"error.csv"}, + 0, false, true, false, false, {"error.csv"}, 42, false, {"ddr5"}, true, DRAMSysConfiguration::StoreMode::NoStorage, false, false, 1000}; } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index cd80dd27..9c559a26 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -81,7 +81,7 @@ void Configuration::loadSimConfig(Configuration &config, const DRAMSysConfigurat if (simConfig.addressOffset.isValid()) config.addressOffset = simConfig.addressOffset.getValue(); - if (simConfig.addressOffset.isValid()) + if (simConfig.checkTLM2Protocol.isValid()) config.checkTLM2Protocol = simConfig.checkTLM2Protocol.getValue(); if (simConfig.databaseRecording.isValid()) @@ -250,13 +250,13 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati if (policy == DRAMSysConfiguration::RefreshPolicy::NoRefresh) return RefreshPolicy::NoRefresh; - else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank || policy == DRAMSysConfiguration::RefreshPolicy::Rankwise) + else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank) return RefreshPolicy::AllBank; - else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank || policy == DRAMSysConfiguration::RefreshPolicy::Bankwise) + else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank) return RefreshPolicy::PerBank; else if (policy == DRAMSysConfiguration::RefreshPolicy::Per2Bank) return RefreshPolicy::Per2Bank; - else // if (policy == DRAMSysConfiguration::RefreshPolicy::SameBank || policy == DRAMSysConfiguration::RefreshPolicy::Groupwise) + else // if (policy == DRAMSysConfiguration::RefreshPolicy::SameBank) return RefreshPolicy::SameBank; }(); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 61ad2cd5..9b6f5bbe 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -100,8 +100,8 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec) : tCK * memSpec.memTimingSpec.entries.at("RFC2_dlr")), tRFC_dpr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dpr") : tCK * memSpec.memTimingSpec.entries.at("RFC2_dpr")), - tRFCsb_slr (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), - tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("WTR_S")), + tRFCsb_slr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_slr")), + tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_dlr ")), tREFI ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("REFI1") : tCK * memSpec.memTimingSpec.entries.at("REFI2")), tREFIsb (tCK * memSpec.memTimingSpec.entries.at("REFISB")), diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index c272eb4a..84fb7f9a 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -79,9 +79,23 @@ AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addre } } - std::copy(addressMapping.bankBits.begin(), addressMapping.bankBits.end(), std::back_inserter(vBankBits)); - std::copy(addressMapping.rowBits.begin(), addressMapping.rowBits.end(), std::back_inserter(vRowBits)); - std::copy(addressMapping.coloumnBits.begin(), addressMapping.coloumnBits.end(), std::back_inserter(vColumnBits)); + if (addressMapping.bankBits.isValid()) + { + auto bankBits = addressMapping.bankBits.getValue(); + std::copy(bankBits.begin(), bankBits.end(), std::back_inserter(vBankBits)); + } + + if (addressMapping.rowBits.isValid()) + { + auto rowBits = addressMapping.rowBits.getValue(); + std::copy(rowBits.begin(), rowBits.end(), std::back_inserter(vRowBits)); + } + + if (addressMapping.columnBits.isValid()) + { + auto columnBits = addressMapping.columnBits.getValue(); + std::copy(columnBits.begin(), columnBits.end(), std::back_inserter(vColumnBits)); + } unsigned channels = std::lround(std::pow(2.0, vChannelBits.size())); unsigned ranks = std::lround(std::pow(2.0, vRankBits.size())); From aed3d37699e8739090686104ca987275bc1d188f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 23 Feb 2022 12:26:27 +0100 Subject: [PATCH 21/23] Switch to C++17 and to std::optional --- DRAMSys/CMakeLists.txt | 2 +- .../src/common/configuration/AddressMapping.h | 17 +- .../src/common/configuration/Configuration.h | 5 +- .../src/common/configuration/McConfig.h | 39 ++--- .../src/common/configuration/SimConfig.h | 29 ++-- .../src/common/configuration/TraceSetup.h | 23 +-- .../common/configuration/memspec/MemSpec.h | 3 +- .../library/src/common/configuration/util.h | 93 +++++------ .../src/configuration/Configuration.cpp | 152 ++++++++---------- .../src/configuration/memspec/MemSpecDDR3.cpp | 26 +-- .../src/configuration/memspec/MemSpecDDR4.cpp | 32 ++-- .../src/configuration/memspec/MemSpecDDR5.cpp | 2 +- .../configuration/memspec/MemSpecWideIO.cpp | 50 +++--- .../library/src/simulation/AddressDecoder.cpp | 39 ++--- DRAMSys/library/src/simulation/DRAMSys.cpp | 4 +- .../src/simulation/TemperatureController.cpp | 2 +- DRAMSys/simulator/CMakeLists.txt | 2 +- DRAMSys/simulator/TraceSetup.cpp | 29 ++-- DRAMSys/simulator/TrafficGenerator.cpp | 72 ++------- DRAMSys/simulator/TrafficGenerator.h | 10 +- DRAMSys/simulator/TrafficInitiator.cpp | 15 -- DRAMSys/simulator/TrafficInitiator.h | 6 +- DRAMSys/simulator/main.cpp | 6 +- DRAMSys/traceAnalyzer/.directory | 8 + DRAMSys/traceAnalyzer/CMakeLists.txt | 2 +- DRAMSys/traceAnalyzer/simulationdialog.cpp | 33 ++-- 26 files changed, 320 insertions(+), 381 deletions(-) create mode 100644 DRAMSys/traceAnalyzer/.directory diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 2904122d..e3d7f388 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -41,7 +41,7 @@ option(DRAMSYS_COVERAGE_CHECK "Coverage check of DRAMSys") option(DRAMSYS_WITH_GEM5 "Build DRAMSys with gem5 coupling") # Configuration: -set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") +set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") if(DRAMSYS_COVERAGE_CHECK) diff --git a/DRAMSys/library/src/common/configuration/AddressMapping.h b/DRAMSys/library/src/common/configuration/AddressMapping.h index d0ee8082..45920cf8 100644 --- a/DRAMSys/library/src/common/configuration/AddressMapping.h +++ b/DRAMSys/library/src/common/configuration/AddressMapping.h @@ -39,6 +39,7 @@ #include "util.h" #include +#include namespace DRAMSysConfiguration { @@ -57,14 +58,14 @@ void from_json(const json &j, XorPair &x); struct AddressMapping { - Optional> byteBits; - Optional> columnBits; - Optional> bankBits; - Optional> bankGroupBits; - Optional> rowBits; - Optional> channelBits; - Optional> rankBits; - Optional> xorBits; + std::optional> byteBits; + std::optional> columnBits; + std::optional> bankBits; + std::optional> bankGroupBits; + std::optional> rowBits; + std::optional> channelBits; + std::optional> rankBits; + std::optional> xorBits; }; void to_json(json &j, const AddressMapping &m); diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h index 7bbca42d..61091aa1 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.h +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -46,6 +46,7 @@ #include #include +#include #include /** @@ -69,8 +70,8 @@ struct Configuration MemSpec memSpec; SimConfig simConfig; std::string simulationId; - Optional thermalConfig; - Optional traceSetup; + std::optional thermalConfig; + std::optional traceSetup; static std::string resourceDirectory; }; diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index 7ad3329c..ee1b51d8 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -40,6 +40,7 @@ #include #include +#include #include namespace DRAMSysConfiguration @@ -148,25 +149,25 @@ NLOHMANN_JSON_SERIALIZE_ENUM(Arbiter, {{Arbiter::Invalid, nullptr}, struct McConfig { - Optional pagePolicy; - Optional scheduler; - Optional schedulerBuffer; - Optional requestBufferSize; - Optional cmdMux; - Optional respQueue; - Optional refreshPolicy; - Optional refreshMaxPostponed; - Optional refreshMaxPulledin; - Optional powerDownPolicy; - Optional arbiter; - Optional maxActiveTransactions; - Optional refreshManagement; - Optional arbitrationDelayFw; - Optional arbitrationDelayBw; - Optional thinkDelayFw; - Optional thinkDelayBw; - Optional phyDelayFw; - Optional phyDelayBw; + std::optional pagePolicy; + std::optional scheduler; + std::optional schedulerBuffer; + std::optional requestBufferSize; + std::optional cmdMux; + std::optional respQueue; + std::optional refreshPolicy; + std::optional refreshMaxPostponed; + std::optional refreshMaxPulledin; + std::optional powerDownPolicy; + std::optional arbiter; + std::optional maxActiveTransactions; + std::optional refreshManagement; + std::optional arbitrationDelayFw; + std::optional arbitrationDelayBw; + std::optional thinkDelayFw; + std::optional thinkDelayBw; + std::optional phyDelayFw; + std::optional phyDelayBw; }; void to_json(json &j, const McConfig &c); diff --git a/DRAMSys/library/src/common/configuration/SimConfig.h b/DRAMSys/library/src/common/configuration/SimConfig.h index 7c189909..339495c8 100644 --- a/DRAMSys/library/src/common/configuration/SimConfig.h +++ b/DRAMSys/library/src/common/configuration/SimConfig.h @@ -39,6 +39,7 @@ #include "util.h" #include +#include namespace DRAMSysConfiguration { @@ -61,20 +62,20 @@ NLOHMANN_JSON_SERIALIZE_ENUM(StoreMode, {{StoreMode::Invalid, nullptr}, struct SimConfig { - Optional addressOffset; - Optional checkTLM2Protocol; - Optional databaseRecording; - Optional debug; - Optional enableWindowing; - Optional errorCsvFile; - Optional errorChipSeed; - Optional powerAnalysis; - Optional simulationName; - Optional simulationProgressBar; - Optional storeMode; - Optional thermalSimulation; - Optional useMalloc; - Optional windowSize; + std::optional addressOffset; + std::optional checkTLM2Protocol; + std::optional databaseRecording; + std::optional debug; + std::optional enableWindowing; + std::optional errorCsvFile; + std::optional errorChipSeed; + std::optional powerAnalysis; + std::optional simulationName; + std::optional simulationProgressBar; + std::optional storeMode; + std::optional thermalSimulation; + std::optional useMalloc; + std::optional windowSize; }; void to_json(json &j, const SimConfig &c); diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 20cbbd7b..54298cf7 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -40,6 +40,7 @@ #include #include +#include namespace DRAMSysConfiguration { @@ -75,9 +76,9 @@ struct TrafficInitiator uint64_t clkMhz; std::string name; - Optional maxPendingReadRequests; - Optional maxPendingWriteRequests; - Optional addLengthConverter; + std::optional maxPendingReadRequests; + std::optional maxPendingWriteRequests; + std::optional addLengthConverter; }; struct TracePlayer : public TrafficInitiator @@ -94,11 +95,11 @@ struct TraceGeneratorTrafficState : public TraceGeneratorState uint64_t numRequests; double rwRatio; AddressDistribution addressDistribution; - Optional addressIncrement; - Optional minAddress; - Optional maxAddress; - Optional clksPerRequest; - Optional notify; + std::optional addressIncrement; + std::optional minAddress; + std::optional maxAddress; + std::optional clksPerRequest; + std::optional notify; }; struct TraceGeneratorIdleState : public TraceGeneratorState @@ -114,11 +115,11 @@ struct TraceGeneratorStateTransition struct TraceGenerator : public TrafficInitiator { - Optional seed; - Optional maxTransactions; + std::optional seed; + std::optional maxTransactions; std::map> states; std::multimap transitions; - Optional idleUntil; + std::optional idleUntil; }; struct TraceHammer : public TrafficInitiator diff --git a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h index 66c0a317..0aa2cb7f 100644 --- a/DRAMSys/library/src/common/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/common/configuration/memspec/MemSpec.h @@ -42,6 +42,7 @@ #include "util.h" #include +#include namespace DRAMSysConfiguration { @@ -55,7 +56,7 @@ struct MemSpec std::string memoryId; std::string memoryType; MemTimingSpec memTimingSpec; - Optional memPowerSpec; + std::optional memPowerSpec; }; void to_json(json &j, const MemSpec &c); diff --git a/DRAMSys/library/src/common/configuration/util.h b/DRAMSys/library/src/common/configuration/util.h index 5d61f9a7..07c12741 100644 --- a/DRAMSys/library/src/common/configuration/util.h +++ b/DRAMSys/library/src/common/configuration/util.h @@ -37,61 +37,62 @@ #define DRAMSYSCONFIGURATION_UTIL_H #include +#include #include namespace DRAMSysConfiguration { using json = nlohmann::json; -template -class Optional : public std::pair -{ -public: - Optional() : std::pair{{}, false} - { - } - Optional(const T &v) : std::pair{v, true} - { - } +// template +// class Optional : public std::pair +// { +// public: +// Optional() : std::pair{{}, false} +// { +// } +// Optional(const T &v) : std::pair{v, true} +// { +// } - bool isValid() const - { - return this->second; - } +// bool isValid() const +// { +// return this->second; +// } - const T &getValue() const - { - assert(this->second == true); - return this->first; - } +// const T &getValue() const +// { +// assert(this->second == true); +// return this->first; +// } - void setValue(const T &v) - { - this->first = v; - this->second = true; - } +// void setValue(const T &v) +// { +// this->first = v; +// this->second = true; +// } - void invalidate() - { - this->second = false; - } +// void invalidate() +// { +// this->second = false; +// } - /** - * This methods only purpose is to make a optional type - * valid so that it can be written to by reference. - */ - T &setByReference() - { - this->second = true; - return this->first; - } -}; +// /** +// * This methods only purpose is to make a optional type +// * valid so that it can be written to by reference. +// */ +// T &setByReference() +// { +// this->second = true; +// return this->first; +// } +// }; template void invalidateEnum(T &value) { - if (value.isValid() && value.getValue() == T::first_type::Invalid) - value.invalidate(); + if (value.has_value() && value.value() == T::value_type::Invalid) + value.reset(); } json get_config_json(const json &j, const std::string &configPath, const std::string &objectName); @@ -119,22 +120,22 @@ namespace nlohmann { template -void to_json(nlohmann::json &j, const DRAMSysConfiguration::Optional &v) +void to_json(nlohmann::json &j, const std::optional &v) { - if (v.isValid()) - j = v.getValue(); + if (v.has_value()) + j = v.value(); else j = nullptr; } template -void from_json(const nlohmann::json &j, DRAMSysConfiguration::Optional &v) +void from_json(const nlohmann::json &j, std::optional &v) { if (j.is_null()) - v = {}; + v = std::nullopt; else { - v = {j.get()}; + v = j.get(); } } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 9c559a26..76636cd4 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -78,55 +78,53 @@ enum sc_time_unit string2TimeUnit(const std::string &s) void Configuration::loadSimConfig(Configuration &config, const DRAMSysConfiguration::SimConfig &simConfig) { - if (simConfig.addressOffset.isValid()) - config.addressOffset = simConfig.addressOffset.getValue(); + if (const auto &addressOffset = simConfig.addressOffset) + config.addressOffset = *addressOffset; - if (simConfig.checkTLM2Protocol.isValid()) - config.checkTLM2Protocol = simConfig.checkTLM2Protocol.getValue(); + if (const auto &checkTLM2Protocol = simConfig.checkTLM2Protocol) + config.checkTLM2Protocol = *checkTLM2Protocol; - if (simConfig.databaseRecording.isValid()) - config.databaseRecording = simConfig.databaseRecording.getValue(); + if (const auto &databaseRecording = simConfig.databaseRecording) + config.databaseRecording = *databaseRecording; - if (simConfig.debug.isValid()) - config.debug = simConfig.debug.getValue(); + if (const auto &debug = simConfig.debug) + config.debug = *debug; - if (simConfig.enableWindowing.isValid()) - config.enableWindowing = simConfig.enableWindowing.getValue(); + if (const auto &enableWindowing = simConfig.enableWindowing) + config.enableWindowing = *enableWindowing; - if (simConfig.powerAnalysis.isValid()) - config.powerAnalysis = simConfig.powerAnalysis.getValue(); + if (const auto &powerAnalysis = simConfig.powerAnalysis) + config.powerAnalysis = *powerAnalysis; - if (simConfig.simulationName.isValid()) - config.simulationName = simConfig.simulationName.getValue(); + if (const auto &simulationName = simConfig.simulationName) + config.simulationName = *simulationName; - if (simConfig.simulationProgressBar.isValid()) - config.simulationProgressBar = simConfig.simulationProgressBar.getValue(); + if (const auto &simulationProgressBar = simConfig.simulationProgressBar) + config.simulationProgressBar = *simulationProgressBar; - if (simConfig.thermalSimulation.isValid()) - config.thermalSimulation = simConfig.thermalSimulation.getValue(); + if (const auto &thermalSimulation = simConfig.thermalSimulation) + config.thermalSimulation = *thermalSimulation; - if (simConfig.useMalloc.isValid()) - config.useMalloc = simConfig.useMalloc.getValue(); + if (const auto &useMalloc = simConfig.useMalloc) + config.useMalloc = *useMalloc; - if (simConfig.windowSize.isValid()) - config.windowSize = simConfig.windowSize.getValue(); + if (const auto &windowSize = simConfig.windowSize) + config.windowSize = *windowSize; if (config.windowSize == 0) SC_REPORT_FATAL("Configuration", "Minimum window size is 1"); - if (simConfig.errorCsvFile.isValid()) - config.errorCSVFile = simConfig.errorCsvFile.getValue(); + if (const auto &errorCsvFile = simConfig.errorCsvFile) + config.errorCSVFile = *errorCsvFile; - if (simConfig.errorChipSeed.isValid()) - config.errorChipSeed = simConfig.errorChipSeed.getValue(); + if (const auto &errorChipSeed = simConfig.errorChipSeed) + config.errorChipSeed = *errorChipSeed; - if (simConfig.storeMode.isValid()) + if (const auto &storeMode = simConfig.storeMode) config.storeMode = [=] { - auto mode = simConfig.storeMode.getValue(); - - if (mode == DRAMSysConfiguration::StoreMode::NoStorage) + if (storeMode == DRAMSysConfiguration::StoreMode::NoStorage) return StoreMode::NoStorage; - else if (mode == DRAMSysConfiguration::StoreMode::Store) + else if (storeMode == DRAMSysConfiguration::StoreMode::Store) return StoreMode::Store; else return StoreMode::ErrorModel; @@ -180,24 +178,20 @@ void Configuration::loadTemperatureSimConfig(Configuration &config, const DRAMSy void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfiguration::McConfig &mcConfig) { - if (mcConfig.pagePolicy.isValid()) + if (const auto &pagePolicy = mcConfig.pagePolicy) config.pagePolicy = [=] { - auto policy = mcConfig.pagePolicy.getValue(); - - if (policy == DRAMSysConfiguration::PagePolicy::Open) + if (pagePolicy == DRAMSysConfiguration::PagePolicy::Open) return PagePolicy::Open; - else if (policy == DRAMSysConfiguration::PagePolicy::OpenAdaptive) + else if (pagePolicy == DRAMSysConfiguration::PagePolicy::OpenAdaptive) return PagePolicy::OpenAdaptive; - else if (policy == DRAMSysConfiguration::PagePolicy::Closed) + else if (pagePolicy == DRAMSysConfiguration::PagePolicy::Closed) return PagePolicy::Closed; else return PagePolicy::ClosedAdaptive; }(); - if (mcConfig.scheduler.isValid()) + if (const auto &scheduler = mcConfig.scheduler) config.scheduler = [=] { - auto scheduler = mcConfig.scheduler.getValue(); - if (scheduler == DRAMSysConfiguration::Scheduler::Fifo) return Scheduler::Fifo; else if (scheduler == DRAMSysConfiguration::Scheduler::FrFcfs) @@ -206,10 +200,8 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati return Scheduler::FrFcfsGrp; }(); - if (mcConfig.schedulerBuffer.isValid()) + if (const auto &schedulerBuffer = mcConfig.schedulerBuffer) config.schedulerBuffer = [=] { - auto schedulerBuffer = mcConfig.schedulerBuffer.getValue(); - if (schedulerBuffer == DRAMSysConfiguration::SchedulerBuffer::Bankwise) return SchedulerBuffer::Bankwise; else if (schedulerBuffer == DRAMSysConfiguration::SchedulerBuffer::ReadWrite) @@ -218,68 +210,58 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati return SchedulerBuffer::Shared; }(); - if (mcConfig.requestBufferSize.isValid()) - config.requestBufferSize = mcConfig.requestBufferSize.getValue(); + if (const auto &requestBufferSize = mcConfig.requestBufferSize) + config.requestBufferSize = *mcConfig.requestBufferSize; if (config.requestBufferSize == 0) SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); - if (mcConfig.cmdMux.isValid()) + if (const auto &cmdMux = mcConfig.cmdMux) config.cmdMux = [=] { - auto cmdMux = mcConfig.cmdMux.getValue(); - if (cmdMux == DRAMSysConfiguration::CmdMux::Oldest) return CmdMux::Oldest; else return CmdMux::Strict; }(); - if (mcConfig.respQueue.isValid()) + if (const auto &respQueue = mcConfig.respQueue) config.respQueue = [=] { - auto respQueue = mcConfig.respQueue.getValue(); - if (respQueue == DRAMSysConfiguration::RespQueue::Fifo) return RespQueue::Fifo; else return RespQueue::Reorder; }(); - if (mcConfig.refreshPolicy.isValid()) + if (const auto &refreshPolicy = mcConfig.refreshPolicy) config.refreshPolicy = [=] { - auto policy = mcConfig.refreshPolicy.getValue(); - - if (policy == DRAMSysConfiguration::RefreshPolicy::NoRefresh) + if (refreshPolicy == DRAMSysConfiguration::RefreshPolicy::NoRefresh) return RefreshPolicy::NoRefresh; - else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank) + else if (refreshPolicy == DRAMSysConfiguration::RefreshPolicy::AllBank) return RefreshPolicy::AllBank; - else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank) + else if (refreshPolicy == DRAMSysConfiguration::RefreshPolicy::PerBank) return RefreshPolicy::PerBank; - else if (policy == DRAMSysConfiguration::RefreshPolicy::Per2Bank) + else if (refreshPolicy == DRAMSysConfiguration::RefreshPolicy::Per2Bank) return RefreshPolicy::Per2Bank; else // if (policy == DRAMSysConfiguration::RefreshPolicy::SameBank) return RefreshPolicy::SameBank; }(); - if (mcConfig.refreshMaxPostponed.isValid()) - config.refreshMaxPostponed = mcConfig.refreshMaxPostponed.getValue(); + if (const auto &refreshMaxPostponed = mcConfig.refreshMaxPostponed) + config.refreshMaxPostponed = *refreshMaxPostponed; - if (mcConfig.refreshMaxPulledin.isValid()) - config.refreshMaxPulledin = mcConfig.refreshMaxPulledin.getValue(); + if (const auto &refreshMaxPulledin = mcConfig.refreshMaxPulledin) + config.refreshMaxPulledin = *refreshMaxPulledin; - if (mcConfig.powerDownPolicy.isValid()) + if (const auto &powerDownPolicy = mcConfig.powerDownPolicy) config.powerDownPolicy = [=] { - auto policy = mcConfig.powerDownPolicy.getValue(); - - if (policy == DRAMSysConfiguration::PowerDownPolicy::NoPowerDown) + if (powerDownPolicy == DRAMSysConfiguration::PowerDownPolicy::NoPowerDown) return PowerDownPolicy::NoPowerDown; else return PowerDownPolicy::Staggered; }(); - if (mcConfig.arbiter.isValid()) + if (const auto &arbiter = mcConfig.arbiter) config.arbiter = [=] { - auto arbiter = mcConfig.arbiter.getValue(); - if (arbiter == DRAMSysConfiguration::Arbiter::Simple) return Arbiter::Simple; else if (arbiter == DRAMSysConfiguration::Arbiter::Fifo) @@ -288,40 +270,40 @@ void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfigurati return Arbiter::Reorder; }(); - if (mcConfig.maxActiveTransactions.isValid()) - config.maxActiveTransactions = mcConfig.maxActiveTransactions.getValue(); + if (const auto &maxActiveTransactions = mcConfig.maxActiveTransactions) + config.maxActiveTransactions = *maxActiveTransactions; - if (mcConfig.refreshManagement.isValid()) - config.refreshManagement = mcConfig.refreshManagement.getValue(); + if (const auto &refreshManagement = mcConfig.refreshManagement) + config.refreshManagement = *refreshManagement; - if (mcConfig.arbitrationDelayFw.isValid()) + if (const auto &arbitrationDelayFw = mcConfig.arbitrationDelayFw) { - config.arbitrationDelayFw = std::round(sc_time(mcConfig.arbitrationDelayFw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + config.arbitrationDelayFw = std::round(sc_time(*arbitrationDelayFw, SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; } - if (mcConfig.arbitrationDelayBw.isValid()) + if (const auto &arbitrationDelayBw = mcConfig.arbitrationDelayBw) { - config.arbitrationDelayBw = std::round(sc_time(mcConfig.arbitrationDelayBw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + config.arbitrationDelayBw = std::round(sc_time(*arbitrationDelayBw, SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; } - if (mcConfig.thinkDelayFw.isValid()) + if (const auto &thinkDelayFw = mcConfig.thinkDelayFw) { - config.thinkDelayFw = std::round(sc_time(mcConfig.thinkDelayFw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + config.thinkDelayFw = std::round(sc_time(*thinkDelayFw, SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; } - if (mcConfig.thinkDelayBw.isValid()) + if (const auto &thinkDelayBw = mcConfig.thinkDelayBw) { - config.thinkDelayBw = std::round(sc_time(mcConfig.thinkDelayBw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + config.thinkDelayBw = std::round(sc_time(*thinkDelayBw, SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; } - if (mcConfig.phyDelayFw.isValid()) + if (const auto &phyDelayFw = mcConfig.phyDelayFw) { - config.phyDelayFw = std::round(sc_time(mcConfig.phyDelayFw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + config.phyDelayFw = std::round(sc_time(*phyDelayFw, SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; } - if (mcConfig.phyDelayBw.isValid()) + if (const auto &phyDelayBw = mcConfig.phyDelayBw) { - config.phyDelayBw = std::round(sc_time(mcConfig.phyDelayBw.getValue(), SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; + config.phyDelayBw = std::round(sc_time(*phyDelayBw, SC_NS) / config.memSpec->tCK) * config.memSpec->tCK; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 81b8b2df..b17601f1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -80,24 +80,24 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec) tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")), tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")), tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), - iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")), - iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")), - iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")), - iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")), - iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")), - iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")), - iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")), - vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")), - iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")), - iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")), - iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")), - iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")) + iDD0 (memSpec.memPowerSpec.value().entries.at("idd0")), + iDD2N (memSpec.memPowerSpec.value().entries.at("idd2n")), + iDD3N (memSpec.memPowerSpec.value().entries.at("idd3n")), + iDD4R (memSpec.memPowerSpec.value().entries.at("idd4r")), + iDD4W (memSpec.memPowerSpec.value().entries.at("idd4w")), + iDD5 (memSpec.memPowerSpec.value().entries.at("idd5")), + iDD6 (memSpec.memPowerSpec.value().entries.at("idd6")), + vDD (memSpec.memPowerSpec.value().entries.at("vdd")), + iDD2P0 (memSpec.memPowerSpec.value().entries.at("idd2p0")), + iDD2P1 (memSpec.memPowerSpec.value().entries.at("idd2p1")), + iDD3P0 (memSpec.memPowerSpec.value().entries.at("idd3p0")), + iDD3P1 (memSpec.memPowerSpec.value().entries.at("idd3p1")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels; - if (!memSpec.memPowerSpec.isValid()) + if (!memSpec.memPowerSpec.has_value()) SC_REPORT_FATAL("MemSpec", "No power spec defined!"); std::cout << headline << std::endl; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index f2c9a204..428584ab 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -95,27 +95,27 @@ MemSpecDDR4::MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec) tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")), tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")), tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), - iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")), - iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")), - iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")), - iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")), - iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")), - iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")), - iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")), - vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")), - iDD02 (memSpec.memPowerSpec.getValue().entries.at("idd02")), - iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")), - iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")), - iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")), - iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")), - iDD62 (memSpec.memPowerSpec.getValue().entries.at("idd62")), - vDD2 (memSpec.memPowerSpec.getValue().entries.at("vdd2")) + iDD0 (memSpec.memPowerSpec.value().entries.at("idd0")), + iDD2N (memSpec.memPowerSpec.value().entries.at("idd2n")), + iDD3N (memSpec.memPowerSpec.value().entries.at("idd3n")), + iDD4R (memSpec.memPowerSpec.value().entries.at("idd4r")), + iDD4W (memSpec.memPowerSpec.value().entries.at("idd4w")), + iDD5 (memSpec.memPowerSpec.value().entries.at("idd5")), + iDD6 (memSpec.memPowerSpec.value().entries.at("idd6")), + vDD (memSpec.memPowerSpec.value().entries.at("vdd")), + iDD02 (memSpec.memPowerSpec.value().entries.at("idd02")), + iDD2P0 (memSpec.memPowerSpec.value().entries.at("idd2p0")), + iDD2P1 (memSpec.memPowerSpec.value().entries.at("idd2p1")), + iDD3P0 (memSpec.memPowerSpec.value().entries.at("idd3p0")), + iDD3P1 (memSpec.memPowerSpec.value().entries.at("idd3p1")), + iDD62 (memSpec.memPowerSpec.value().entries.at("idd62")), + vDD2 (memSpec.memPowerSpec.value().entries.at("vdd2")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels; - if (!memSpec.memPowerSpec.isValid()) + if (!memSpec.memPowerSpec.has_value()) SC_REPORT_FATAL("MemSpec", "No power spec defined!"); std::cout << headline << std::endl; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 9b6f5bbe..23b6db52 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -101,7 +101,7 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec) tRFC_dpr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dpr") : tCK * memSpec.memTimingSpec.entries.at("RFC2_dpr")), tRFCsb_slr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_slr")), - tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_dlr ")), + tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("RFCsb_dlr")), tREFI ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("REFI1") : tCK * memSpec.memTimingSpec.entries.at("REFI2")), tREFIsb (tCK * memSpec.memTimingSpec.entries.at("REFISB")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index f9ed3b9c..9b84c30f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -74,36 +74,36 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec) tTAW (tCK * memSpec.memTimingSpec.entries.at("TAW")), tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")), tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")), - iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")), - iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")), - iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")), - iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")), - iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")), - iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")), - iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")), - vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")), - iDD02 (memSpec.memPowerSpec.getValue().entries.at("idd02")), - iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")), - iDD2P02 (memSpec.memPowerSpec.getValue().entries.at("idd2p02")), - iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")), - iDD2P12 (memSpec.memPowerSpec.getValue().entries.at("idd2p12")), - iDD2N2 (memSpec.memPowerSpec.getValue().entries.at("idd2n2")), - iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")), - iDD3P02 (memSpec.memPowerSpec.getValue().entries.at("idd3p02")), - iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")), - iDD3P12 (memSpec.memPowerSpec.getValue().entries.at("idd3p12")), - iDD3N2 (memSpec.memPowerSpec.getValue().entries.at("idd3n2")), - iDD4R2 (memSpec.memPowerSpec.getValue().entries.at("idd4r2")), - iDD4W2 (memSpec.memPowerSpec.getValue().entries.at("idd4w2")), - iDD52 (memSpec.memPowerSpec.getValue().entries.at("idd52")), - iDD62 (memSpec.memPowerSpec.getValue().entries.at("idd62")), - vDD2 (memSpec.memPowerSpec.getValue().entries.at("vdd2")) + iDD0 (memSpec.memPowerSpec.value().entries.at("idd0")), + iDD2N (memSpec.memPowerSpec.value().entries.at("idd2n")), + iDD3N (memSpec.memPowerSpec.value().entries.at("idd3n")), + iDD4R (memSpec.memPowerSpec.value().entries.at("idd4r")), + iDD4W (memSpec.memPowerSpec.value().entries.at("idd4w")), + iDD5 (memSpec.memPowerSpec.value().entries.at("idd5")), + iDD6 (memSpec.memPowerSpec.value().entries.at("idd6")), + vDD (memSpec.memPowerSpec.value().entries.at("vdd")), + iDD02 (memSpec.memPowerSpec.value().entries.at("idd02")), + iDD2P0 (memSpec.memPowerSpec.value().entries.at("idd2p0")), + iDD2P02 (memSpec.memPowerSpec.value().entries.at("idd2p02")), + iDD2P1 (memSpec.memPowerSpec.value().entries.at("idd2p1")), + iDD2P12 (memSpec.memPowerSpec.value().entries.at("idd2p12")), + iDD2N2 (memSpec.memPowerSpec.value().entries.at("idd2n2")), + iDD3P0 (memSpec.memPowerSpec.value().entries.at("idd3p0")), + iDD3P02 (memSpec.memPowerSpec.value().entries.at("idd3p02")), + iDD3P1 (memSpec.memPowerSpec.value().entries.at("idd3p1")), + iDD3P12 (memSpec.memPowerSpec.value().entries.at("idd3p12")), + iDD3N2 (memSpec.memPowerSpec.value().entries.at("idd3n2")), + iDD4R2 (memSpec.memPowerSpec.value().entries.at("idd4r2")), + iDD4W2 (memSpec.memPowerSpec.value().entries.at("idd4w2")), + iDD52 (memSpec.memPowerSpec.value().entries.at("idd52")), + iDD62 (memSpec.memPowerSpec.value().entries.at("idd62")), + vDD2 (memSpec.memPowerSpec.value().entries.at("vdd2")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * numberOfRows * numberOfColumns * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels; - if (!memSpec.memPowerSpec.isValid()) + if (!memSpec.memPowerSpec.has_value()) SC_REPORT_FATAL("MemSpec", "No power spec defined!"); std::cout << headline << std::endl; diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index 84fb7f9a..178fa6db 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -47,54 +47,47 @@ AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addressMapping) { - if (addressMapping.channelBits.isValid()) + if (const auto &channelBits = addressMapping.channelBits) { - auto channelBits = addressMapping.channelBits.getValue(); - std::copy(channelBits.begin(), channelBits.end(), std::back_inserter(vChannelBits)); + std::copy(channelBits->begin(), channelBits->end(), std::back_inserter(vChannelBits)); } - if (addressMapping.rankBits.isValid()) + if (const auto &rankBits = addressMapping.rankBits) { - auto rankBits = addressMapping.rankBits.getValue(); - std::copy(rankBits.begin(), rankBits.end(), std::back_inserter(vRankBits)); + std::copy(rankBits->begin(), rankBits->end(), std::back_inserter(vRankBits)); } - if (addressMapping.bankGroupBits.isValid()) + if (const auto &bankGroupBits = addressMapping.bankGroupBits) { - auto bankBroupBits = addressMapping.bankGroupBits.getValue(); - std::copy(bankBroupBits.begin(), bankBroupBits.end(), std::back_inserter(vBankGroupBits)); + std::copy(bankGroupBits->begin(), bankGroupBits->end(), std::back_inserter(vBankGroupBits)); } - if (addressMapping.byteBits.isValid()) + if (const auto &byteBits = addressMapping.byteBits) { - auto byteBits = addressMapping.byteBits.getValue(); - std::copy(byteBits.begin(), byteBits.end(), std::back_inserter(vByteBits)); + std::copy(byteBits->begin(), byteBits->end(), std::back_inserter(vByteBits)); } - if (addressMapping.xorBits.isValid()) + if (const auto &xorBits = addressMapping.xorBits) { - for (const auto &xorBit : addressMapping.xorBits.getValue()) + for (const auto &xorBit : *xorBits) { vXor.emplace_back(xorBit.first, xorBit.second); } } - if (addressMapping.bankBits.isValid()) + if (const auto &bankBits = addressMapping.bankBits) { - auto bankBits = addressMapping.bankBits.getValue(); - std::copy(bankBits.begin(), bankBits.end(), std::back_inserter(vBankBits)); + std::copy(bankBits->begin(), bankBits->end(), std::back_inserter(vBankBits)); } - if (addressMapping.rowBits.isValid()) + if (const auto &rowBits = addressMapping.rowBits) { - auto rowBits = addressMapping.rowBits.getValue(); - std::copy(rowBits.begin(), rowBits.end(), std::back_inserter(vRowBits)); + std::copy(rowBits->begin(), rowBits->end(), std::back_inserter(vRowBits)); } - if (addressMapping.columnBits.isValid()) + if (const auto &columnBits = addressMapping.columnBits) { - auto columnBits = addressMapping.columnBits.getValue(); - std::copy(columnBits.begin(), columnBits.end(), std::back_inserter(vColumnBits)); + std::copy(columnBits->begin(), columnBits->end(), std::back_inserter(vColumnBits)); } unsigned channels = std::lround(std::pow(2.0, vChannelBits.size())); diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 21f7a222..c1fb3065 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -80,8 +80,8 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name, Configuration::loadMCConfig(Configuration::getInstance(), config.mcConfig); Configuration::loadSimConfig(Configuration::getInstance(), config.simConfig); - if (config.thermalConfig.isValid()) - Configuration::loadTemperatureSimConfig(Configuration::getInstance(), config.thermalConfig.getValue()); + if (const auto &thermalConfig = config.thermalConfig) + Configuration::loadTemperatureSimConfig(Configuration::getInstance(), *thermalConfig); // Setup the debug manager: setupDebugManager(Configuration::getInstance().simulationName); diff --git a/DRAMSys/library/src/simulation/TemperatureController.cpp b/DRAMSys/library/src/simulation/TemperatureController.cpp index f66469c9..77ef5d1e 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.cpp +++ b/DRAMSys/library/src/simulation/TemperatureController.cpp @@ -149,7 +149,7 @@ double TemperatureController::adjustThermalSimPeriod() cyclesSinceLastPeriodAdjust++; if (cyclesSinceLastPeriodAdjust >= nPowStableCyclesToIncreasePeriod) { cyclesSinceLastPeriodAdjust = 0; - period = period * (periodAdjustFactor / 2); + period = period * ((double)periodAdjustFactor / 2); if (period > targetPeriod) period = targetPeriod; PRINTDEBUGMESSAGE(name(), "Thermal Simulation period increased to " diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index 43b59dd2..507d6a71 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -39,7 +39,7 @@ cmake_minimum_required(VERSION 3.10) project(DRAMSysSimulator) # Configuration: -set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") +set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") find_package(Threads REQUIRED) diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 7bd468f8..3672408d 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -59,23 +59,26 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, std::string name = inititator->name; - unsigned int maxPendingReadRequests = [=]() -> unsigned int { - if (inititator->maxPendingReadRequests.isValid()) - return inititator->maxPendingReadRequests.getValue(); + unsigned int maxPendingReadRequests = [=]() -> unsigned int + { + if (const auto &maxPendingReadRequests = inititator->maxPendingReadRequests) + return *maxPendingReadRequests; else return 0; }(); - unsigned int maxPendingWriteRequests = [=]() -> unsigned int { - if (inititator->maxPendingWriteRequests.isValid()) - return inititator->maxPendingWriteRequests.getValue(); + unsigned int maxPendingWriteRequests = [=]() -> unsigned int + { + if (const auto &maxPendingWriteRequests = inititator->maxPendingWriteRequests) + return *maxPendingWriteRequests; else return 0; }(); - bool addLengthConverter = [=]() -> bool { - if (inititator->addLengthConverter.isValid()) - return inititator->addLengthConverter.getValue(); + bool addLengthConverter = [=]() -> bool + { + if (const auto &addLengthConverter = inititator->addLengthConverter) + return *addLengthConverter; else return false; }(); @@ -132,10 +135,8 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, { if (auto generatorConf = std::dynamic_pointer_cast(inititatorConf)) { - if (generatorConf->idleUntil.isValid()) + if (const auto &idleUntil = generatorConf->idleUntil) { - auto idleUntil = generatorConf->idleUntil.getValue(); - const std::string name = generatorConf->name; auto listenerIt = std::find_if(players.begin(), players.end(), @@ -150,7 +151,7 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, { if (auto generator = dynamic_cast(initiator.get())) { - if (generator->hasStateTransitionEvent(idleUntil)) + if (generator->hasStateTransitionEvent(*idleUntil)) return true; } @@ -161,7 +162,7 @@ TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, SC_REPORT_FATAL("TraceSetup", "Event to listen on not found."); auto notifier = dynamic_cast(notifierIt->get()); - listener->waitUntil(¬ifier->getStateTransitionEvent(idleUntil)); + listener->waitUntil(¬ifier->getStateTransitionEvent(*idleUntil)); } } } diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index bfca8a46..1598a82b 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -93,9 +93,12 @@ void TrafficGeneratorIf::sendNextPayload() TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConfiguration::TraceGenerator &conf, TraceSetup *setup) - : TrafficGeneratorIf(name, setup, evaluateMaxPendingReadRequests(conf), evaluateMaxPendingWriteRequests(conf), evaluateAddLengthConverter(conf)), - generatorClk(TrafficInitiator::evaluateGeneratorClk(conf)), conf(conf), maxTransactions(evaluateMaxTransactions(conf)), - randomGenerator(std::default_random_engine(evaluateSeed(conf))) + : TrafficGeneratorIf(name, setup, conf.maxPendingReadRequests.value_or(defaultMaxPendingReadRequests), + conf.maxPendingWriteRequests.value_or(defaultMaxPendingWriteRequests), + conf.addLengthConverter.value_or(false)), + generatorClk(TrafficInitiator::evaluateGeneratorClk(conf)), conf(conf), + maxTransactions(conf.maxTransactions.value_or(std::numeric_limits::max())), + randomGenerator(std::default_random_engine(conf.seed.value_or(defaultSeed))) { // Perform checks for all states for (const auto &state : conf.states) @@ -118,11 +121,10 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf if (rwRatio < 0 || rwRatio > 1) SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1."); - if (trafficState->notify.isValid()) + if (const auto &eventName = trafficState->notify) { - auto eventName = trafficState->notify.getValue(); - stateTranstitionEvents.emplace(std::piecewise_construct, std::forward_as_tuple(eventName), - std::forward_as_tuple(eventName.c_str(), state.first)); + stateTranstitionEvents.emplace(std::piecewise_construct, std::forward_as_tuple(*eventName), + std::forward_as_tuple(eventName->c_str(), state.first)); } } } @@ -132,7 +134,7 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf uint64_t minAddress = evaluateMinAddress(*trafficState); uint64_t maxAddress = evaluateMaxAddress(*trafficState); randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); - currentClksPerRequest = evaluateClksPerRequest(*trafficState); + currentClksPerRequest = trafficState->clksPerRequest.value_or(defaultClksPerRequest); } calculateTransitions(); @@ -265,7 +267,7 @@ void TrafficGenerator::transitionToNextState() uint64_t minAddress = evaluateMinAddress(*trafficState); uint64_t maxAddress = evaluateMaxAddress(*trafficState); randomAddressDistribution = std::uniform_int_distribution(minAddress, maxAddress); - currentClksPerRequest = evaluateClksPerRequest(*trafficState); + currentClksPerRequest = trafficState->clksPerRequest.value_or(defaultClksPerRequest); } currentAddress = 0x00; @@ -329,7 +331,7 @@ uint64_t TrafficGenerator::getNextAddress() if (state->addressDistribution == AddressDistribution::Sequential) { - uint64_t addressIncrement = evaluateAddressIncrement(*state); + uint64_t addressIncrement = state->addressIncrement.value_or(defaultAddressIncrement); uint64_t address = currentAddress; currentAddress += addressIncrement; @@ -347,60 +349,14 @@ uint64_t TrafficGenerator::getNextAddress() } } -uint64_t TrafficGenerator::evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf) -{ - if (conf.seed.isValid()) - return conf.seed.getValue(); - else - return 0; -} - -uint64_t TrafficGenerator::evaluateMaxTransactions(const DRAMSysConfiguration::TraceGenerator &conf) -{ - if (conf.maxTransactions.isValid()) - return conf.maxTransactions.getValue(); - else - return std::numeric_limits::max(); -} - -bool TrafficGenerator::evaluateAddLengthConverter(const DRAMSysConfiguration::TraceGenerator &conf) -{ - if (conf.addLengthConverter.isValid()) - return conf.addLengthConverter.getValue(); - else - return false; -} - uint64_t TrafficGenerator::evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) { - if (state.minAddress.isValid()) - return state.minAddress.getValue(); - else - return 0x00; + return state.minAddress.value_or(0x00); } uint64_t TrafficGenerator::evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) { - if (state.maxAddress.isValid()) - return state.maxAddress.getValue(); - else - return Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1; -} - -uint64_t TrafficGenerator::evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) -{ - if (state.addressIncrement.isValid()) - return state.addressIncrement.getValue(); - else - return 0x00; -} - -uint64_t TrafficGenerator::evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorTrafficState &state) -{ - if (state.clksPerRequest.isValid()) - return state.clksPerRequest.getValue(); - else - return 1; + return state.maxAddress.value_or(Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1); } TrafficGeneratorHammer::TrafficGeneratorHammer(const sc_core::sc_module_name &name, diff --git a/DRAMSys/simulator/TrafficGenerator.h b/DRAMSys/simulator/TrafficGenerator.h index 10f6c66c..e623dd48 100644 --- a/DRAMSys/simulator/TrafficGenerator.h +++ b/DRAMSys/simulator/TrafficGenerator.h @@ -42,6 +42,7 @@ #include "TrafficInitiator.h" #include "TraceSetup.h" +#include #include #include @@ -74,13 +75,8 @@ public: const sc_core::sc_event &getStateTransitionEvent(const std::string &eventName) const; private: - static uint64_t evaluateSeed(const DRAMSysConfiguration::TraceGenerator &conf); - static uint64_t evaluateMaxTransactions(const DRAMSysConfiguration::TraceGenerator &conf); - static bool evaluateAddLengthConverter(const DRAMSysConfiguration::TraceGenerator &conf); static uint64_t evaluateMinAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); static uint64_t evaluateMaxAddress(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); - static uint64_t evaluateAddressIncrement(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); - static uint64_t evaluateClksPerRequest(const DRAMSysConfiguration::TraceGeneratorTrafficState &state); void prepareNextPayload() override; uint64_t getNextAddress() override; @@ -124,6 +120,10 @@ private: std::default_random_engine randomGenerator; std::uniform_real_distribution randomDistribution = std::uniform_real_distribution(0.0f, 1.0f); std::uniform_int_distribution randomAddressDistribution; + + static constexpr uint64_t defaultSeed = 0; + static constexpr uint64_t defaultClksPerRequest = 1; + static constexpr uint64_t defaultAddressIncrement = 0x00; }; class TrafficGeneratorHammer final : public TrafficGeneratorIf diff --git a/DRAMSys/simulator/TrafficInitiator.cpp b/DRAMSys/simulator/TrafficInitiator.cpp index 83449c46..4a2f74af 100644 --- a/DRAMSys/simulator/TrafficInitiator.cpp +++ b/DRAMSys/simulator/TrafficInitiator.cpp @@ -137,18 +137,3 @@ sc_core::sc_time TrafficInitiator::evaluateGeneratorClk(const DRAMSysConfigurati return playerClk; } -unsigned int TrafficInitiator::evaluateMaxPendingReadRequests(const DRAMSysConfiguration::TrafficInitiator &conf) -{ - if (conf.maxPendingReadRequests.isValid()) - return conf.maxPendingReadRequests.getValue(); - else - return 0; -} - -unsigned int TrafficInitiator::evaluateMaxPendingWriteRequests(const DRAMSysConfiguration::TrafficInitiator &conf) -{ - if (conf.maxPendingWriteRequests.isValid()) - return conf.maxPendingWriteRequests.getValue(); - else - return 0; -} diff --git a/DRAMSys/simulator/TrafficInitiator.h b/DRAMSys/simulator/TrafficInitiator.h index c727777d..3b456d29 100644 --- a/DRAMSys/simulator/TrafficInitiator.h +++ b/DRAMSys/simulator/TrafficInitiator.h @@ -64,8 +64,6 @@ public: protected: static sc_core::sc_time evaluateGeneratorClk(const DRAMSysConfiguration::TrafficInitiator &conf); - static unsigned int evaluateMaxPendingReadRequests(const DRAMSysConfiguration::TrafficInitiator &conf); - static unsigned int evaluateMaxPendingWriteRequests(const DRAMSysConfiguration::TrafficInitiator &conf); tlm_utils::peq_with_cb_and_phase payloadEventQueue; void terminate(); @@ -86,6 +84,10 @@ protected: const unsigned int defaultDataLength = 64; const bool storageEnabled = false; + // 0 disables the max value. + static constexpr unsigned int defaultMaxPendingWriteRequests = 0; + static constexpr unsigned int defaultMaxPendingReadRequests = 0; + private: tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 44962562..5fed42be 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -108,17 +108,17 @@ int sc_main(int argc, char **argv) std::unique_ptr dramSys; #ifdef RECORDING - if (conf.simConfig.databaseRecording.isValid() && conf.simConfig.databaseRecording.getValue()) + if (conf.simConfig.databaseRecording.value_or(false)) dramSys = std::unique_ptr(new DRAMSysRecordable("DRAMSys", conf)); else #endif dramSys = std::unique_ptr(new DRAMSys("DRAMSys", conf)); - if (!conf.traceSetup.isValid()) + if (!conf.traceSetup.has_value()) SC_REPORT_FATAL("sc_main", "No tracesetup section provided."); // Instantiate STL Players: - TraceSetup setup(conf.traceSetup.getValue(), resources, players); + TraceSetup setup(conf.traceSetup.value(), resources, players); // Bind STL Players with DRAMSys: for (auto& player : players) diff --git a/DRAMSys/traceAnalyzer/.directory b/DRAMSys/traceAnalyzer/.directory new file mode 100644 index 00000000..407ff9bc --- /dev/null +++ b/DRAMSys/traceAnalyzer/.directory @@ -0,0 +1,8 @@ +[Dolphin] +Timestamp=2022,2,16,16,1,1.259 +Version=4 +ViewMode=1 +VisibleRoles=Details_text,Details_type,Details_size,Details_modificationtime,CustomizedDetails + +[Settings] +HiddenFilesShown=true diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 5f4ea9bf..3ce4cceb 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -66,7 +66,7 @@ set(CMAKE_AUTORCC ON) set(CMAKE_INCLUDE_CURRENT_DIR ON) # Configure: -set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) set(DCMAKE_SH="CMAKE_SH-NOTFOUND") add_executable(TraceAnalyzer diff --git a/DRAMSys/traceAnalyzer/simulationdialog.cpp b/DRAMSys/traceAnalyzer/simulationdialog.cpp index 218909ce..cc0f6958 100644 --- a/DRAMSys/traceAnalyzer/simulationdialog.cpp +++ b/DRAMSys/traceAnalyzer/simulationdialog.cpp @@ -34,6 +34,7 @@ */ #include "simulationdialog.h" +#include "TraceSetup.h" #include #include @@ -41,6 +42,7 @@ #include #include #include +#include SimulationDialog::SimulationDialog(QWidget *parent) : QWidget(parent), ui(new Ui::SimulationDialog) { @@ -90,8 +92,7 @@ void SimulationDialog::on_browseConfigButton_clicked() void SimulationDialog::on_browseOutputButton_clicked() { - QString fileName = - QFileDialog::getExistingDirectory(this, ui->browseOutputButton->text(), {}); + QString fileName = QFileDialog::getExistingDirectory(this, ui->browseOutputButton->text(), {}); ui->outputDirLineEdit->setText(fileName); loadConfigurationFromPath(); @@ -99,8 +100,7 @@ void SimulationDialog::on_browseOutputButton_clicked() void SimulationDialog::on_browseResourceDirButton_clicked() { - QString fileName = - QFileDialog::getExistingDirectory(this, ui->browseResourceDirButton->text(), {}); + QString fileName = QFileDialog::getExistingDirectory(this, ui->browseResourceDirButton->text(), {}); ui->resourceDirLineEdit->setText(fileName); loadConfigurationFromPath(); @@ -246,8 +246,8 @@ void SimulationDialog::loadConfigurationFromTextFields() MemSpec memSpec; SimConfig simConfig; std::string simulationId; - Optional thermalConfig; - Optional traceSetup; + ThermalConfig thermalConfig; + TraceSetup traceSetup; simulationId = ui->simulationIdLineEdit->text().toStdString(); @@ -259,10 +259,10 @@ void SimulationDialog::loadConfigurationFromTextFields() from_dump(ui->simConfigTextEdit->toPlainText().toStdString(), simConfig); if (!ui->thermalConfigTextEdit->toPlainText().toStdString().empty()) - from_dump(ui->thermalConfigTextEdit->toPlainText().toStdString(), thermalConfig.setByReference()); + from_dump(ui->thermalConfigTextEdit->toPlainText().toStdString(), thermalConfig); if (!ui->traceSetupTextEdit->toPlainText().toStdString().empty()) - from_dump(ui->traceSetupTextEdit->toPlainText().toStdString(), traceSetup.setByReference()); + from_dump(ui->traceSetupTextEdit->toPlainText().toStdString(), traceSetup); } catch (const std::exception &e) { @@ -270,8 +270,13 @@ void SimulationDialog::loadConfigurationFromTextFields() return; } - configuration = DRAMSysConfiguration::Configuration{addressMapping, mcConfig, memSpec, simConfig, - simulationId, thermalConfig, traceSetup}; + configuration = DRAMSysConfiguration::Configuration{addressMapping, + mcConfig, + memSpec, + simConfig, + simulationId, + std::make_optional(std::move(thermalConfig)), + std::make_optional(std::move(traceSetup))}; loadConfiguration(); } @@ -349,9 +354,9 @@ void SimulationDialog::loadThermalConfig() { ui->thermalConfigTextEdit->clear(); - if (configuration.thermalConfig.isValid()) + if (const auto &thermalConfig = configuration.thermalConfig) { - std::string dump = DRAMSysConfiguration::dump(configuration.thermalConfig.getValue(), 4); + std::string dump = DRAMSysConfiguration::dump(*thermalConfig, 4); ui->thermalConfigTextEdit->setText(dump.c_str()); } } @@ -360,9 +365,9 @@ void SimulationDialog::loadTraceSetup() { ui->traceSetupTextEdit->clear(); - if (configuration.traceSetup.isValid()) + if (const auto &traceSetup = configuration.traceSetup) { - std::string dump = DRAMSysConfiguration::dump(configuration.traceSetup.getValue(), 4); + std::string dump = DRAMSysConfiguration::dump(*traceSetup, 4); ui->traceSetupTextEdit->setText(dump.c_str()); } } From 70f987f9e906c6453a99139ae462df20d52b84fc Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 23 Feb 2022 15:57:32 +0100 Subject: [PATCH 22/23] Switch to std::variant in configuration library. --- .../src/common/configuration/Configuration.h | 9 +- .../src/common/configuration/McConfig.h | 1 - .../src/common/configuration/TraceSetup.cpp | 255 ++++++++++-------- .../src/common/configuration/TraceSetup.h | 6 +- .../common/configuration/tests/simpletest.cpp | 109 ++++---- DRAMSys/simulator/TraceSetup.cpp | 149 +++++----- DRAMSys/simulator/TrafficGenerator.cpp | 35 +-- 7 files changed, 299 insertions(+), 265 deletions(-) diff --git a/DRAMSys/library/src/common/configuration/Configuration.h b/DRAMSys/library/src/common/configuration/Configuration.h index 61091aa1..657f11be 100644 --- a/DRAMSys/library/src/common/configuration/Configuration.h +++ b/DRAMSys/library/src/common/configuration/Configuration.h @@ -44,7 +44,6 @@ #include "memspec/MemSpec.h" #include "util.h" -#include #include #include #include @@ -53,10 +52,10 @@ * To support polymorphic configurations, a Json "type" tag is used * to determine the correct type before further parsing. * - * To support optional values, std::pair is used. The first parameter is the value, - * the second parameter specifies if the value is valid. - * Replace with std::optional when this project is updated to C++17. - * Consider also switching to std::variant to achieve static polymorphism. + * To support optional values, std::optional is used. The default + * values will be provided by DRAMSys itself. + * + * To achieve static polymorphism, std::variant is used. */ namespace DRAMSysConfiguration diff --git a/DRAMSys/library/src/common/configuration/McConfig.h b/DRAMSys/library/src/common/configuration/McConfig.h index ee1b51d8..051c05e4 100644 --- a/DRAMSys/library/src/common/configuration/McConfig.h +++ b/DRAMSys/library/src/common/configuration/McConfig.h @@ -38,7 +38,6 @@ #include "util.h" -#include #include #include #include diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.cpp b/DRAMSys/library/src/common/configuration/TraceSetup.cpp index 19241e33..1e25b4a4 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.cpp +++ b/DRAMSys/library/src/common/configuration/TraceSetup.cpp @@ -35,6 +35,8 @@ #include "TraceSetup.h" +#include + namespace DRAMSysConfiguration { @@ -55,94 +57,112 @@ void to_json(json &j, const TraceSetup &c) { json initiator_j; - initiator_j["name"] = initiator->name; - initiator_j["clkMhz"] = initiator->clkMhz; - initiator_j["maxPendingReadRequests"] = initiator->maxPendingReadRequests; - initiator_j["maxPendingWriteRequests"] = initiator->maxPendingWriteRequests; - initiator_j["addLengthConverter"] = initiator->addLengthConverter; - - if (const auto generator = dynamic_cast(initiator.get())) - { - initiator_j["type"] = "generator"; - initiator_j["seed"] = generator->seed; - initiator_j["maxTransactions"] = generator->maxTransactions; - initiator_j["idleUntil"] = generator->idleUntil; - - // When there are less than 2 states, flatten out the json. - if (generator->states.size() == 1) + std::visit( + [&initiator_j](auto &&initiator) { - const auto &state = generator->states[0]; + initiator_j["name"] = initiator.name; + initiator_j["clkMhz"] = initiator.clkMhz; + initiator_j["maxPendingReadRequests"] = initiator.maxPendingReadRequests; + initiator_j["maxPendingWriteRequests"] = initiator.maxPendingWriteRequests; + initiator_j["addLengthConverter"] = initiator.addLengthConverter; - if (const auto trafficState = dynamic_cast(state.get())) + using T = std::decay_t; + if constexpr (std::is_same_v) { - initiator_j["numRequests"] = trafficState->numRequests; - initiator_j["rwRatio"] = trafficState->rwRatio; - initiator_j["addressDistribution"] = trafficState->addressDistribution; - initiator_j["addressIncrement"] = trafficState->addressIncrement; - initiator_j["minAddress"] = trafficState->minAddress; - initiator_j["maxAddress"] = trafficState->maxAddress; - initiator_j["clksPerRequest"] = trafficState->clksPerRequest; - initiator_j["notify"] = trafficState->notify; - } - else if (const auto idleState = dynamic_cast(state.get())) - { - initiator_j["idleClks"] = idleState->idleClks; - } - } - else - { - json states_j = json::array(); + initiator_j["type"] = "generator"; + initiator_j["seed"] = initiator.seed; + initiator_j["maxTransactions"] = initiator.maxTransactions; + initiator_j["idleUntil"] = initiator.idleUntil; - for (const auto &state : generator->states) - { - json state_j; - state_j["id"] = state.first; - - if (const auto trafficState = dynamic_cast(state.second.get())) + // When there are less than 2 states, flatten out the json. + if (initiator.states.size() == 1) { - state_j["numRequests"] = trafficState->numRequests; - state_j["rwRatio"] = trafficState->rwRatio; - state_j["addressDistribution"] = trafficState->addressDistribution; - state_j["addressIncrement"] = trafficState->addressIncrement; - state_j["minAddress"] = trafficState->minAddress; - state_j["maxAddress"] = trafficState->maxAddress; - state_j["clksPerRequest"] = trafficState->clksPerRequest; - state_j["notify"] = trafficState->notify; + std::visit( + [&initiator_j](auto &&state) + { + using U = std::decay_t; + + if constexpr (std::is_same_v) + { + initiator_j["numRequests"] = state.numRequests; + initiator_j["rwRatio"] = state.rwRatio; + initiator_j["addressDistribution"] = state.addressDistribution; + initiator_j["addressIncrement"] = state.addressIncrement; + initiator_j["minAddress"] = state.minAddress; + initiator_j["maxAddress"] = state.maxAddress; + initiator_j["clksPerRequest"] = state.clksPerRequest; + initiator_j["notify"] = state.notify; + } + else // if constexpr (std::is_same_v) + { + initiator_j["idleClks"] = state.idleClks; + } + }, + initiator.states.at(0)); } - else if (const auto idleState = dynamic_cast(state.second.get())) + else { - state_j["idleClks"] = idleState->idleClks; + json states_j = json::array(); + + for (const auto &state : initiator.states) + { + json state_j; + state_j["id"] = state.first; + + std::visit( + [&state_j](auto &&state) + { + using U = std::decay_t; + + if constexpr (std::is_same_v) + { + state_j["numRequests"] = state.numRequests; + state_j["rwRatio"] = state.rwRatio; + state_j["addressDistribution"] = state.addressDistribution; + state_j["addressIncrement"] = state.addressIncrement; + state_j["minAddress"] = state.minAddress; + state_j["maxAddress"] = state.maxAddress; + state_j["clksPerRequest"] = state.clksPerRequest; + state_j["notify"] = state.notify; + } + else // if constexpr (std::is_same_v) + { + state_j["idleClks"] = state.idleClks; + } + }, + state.second); + + remove_null_values(state_j); + states_j.insert(states_j.end(), state_j); + } + initiator_j["states"] = states_j; + + json transitions_j = json::array(); + + for (const auto &transition : initiator.transitions) + { + json transition_j; + transition_j["from"] = transition.first; + transition_j["to"] = transition.second.to; + transition_j["propability"] = transition.second.propability; + remove_null_values(transition_j); + transitions_j.insert(transitions_j.end(), transition_j); + } + initiator_j["transitions"] = transitions_j; } - - remove_null_values(state_j); - states_j.insert(states_j.end(), state_j); } - initiator_j["states"] = states_j; - - json transitions_j = json::array(); - - for (const auto &transition : generator->transitions) + else if constexpr (std::is_same_v) { - json transition_j; - transition_j["from"] = transition.first; - transition_j["to"] = transition.second.to; - transition_j["propability"] = transition.second.propability; - remove_null_values(transition_j); - transitions_j.insert(transitions_j.end(), transition_j); + initiator_j["type"] = "hammer"; + initiator_j["numRequests"] = initiator.numRequests; + initiator_j["rowIncrement"] = initiator.rowIncrement; } - initiator_j["transitions"] = transitions_j; - } - } - else if (const auto hammer = dynamic_cast(initiator.get())) - { - initiator_j["type"] = "hammer"; - initiator_j["numRequests"] = hammer->numRequests; - initiator_j["rowIncrement"] = hammer->rowIncrement; - } - else if (const auto player = dynamic_cast(initiator.get())) - { - initiator_j["type"] = "player"; - } + else // if constexpr (std::is_same_v) + { + initiator_j["type"] = "player"; + } + }, + initiator); remove_null_values(initiator_j); j.insert(j.end(), initiator_j); @@ -156,51 +176,53 @@ void from_json(const json &j, TraceSetup &c) // Default to Player, when not specified TrafficInitiatorType type = initiator_j.value("type", TrafficInitiatorType::Player); - std::unique_ptr initiator; + std::variant initiator; + if (type == TrafficInitiatorType::Player) { - initiator = std::unique_ptr(new TracePlayer); + initiator = TracePlayer{}; } else if (type == TrafficInitiatorType::Generator) { - TraceGenerator *generator = new TraceGenerator; + TraceGenerator generator; - auto process_state = [](const json &state_j) -> std::pair> + auto process_state = [](const json &state_j) + -> std::pair> { - std::unique_ptr state; + std::variant state; if (state_j.contains("idleClks")) { // Idle state - auto idleState = new TraceGeneratorIdleState; - state_j.at("idleClks").get_to(idleState->idleClks); + TraceGeneratorIdleState idleState; + state_j.at("idleClks").get_to(idleState.idleClks); - state = std::unique_ptr(idleState); + state = std::move(idleState); } else { // Traffic state - auto trafficState = new TraceGeneratorTrafficState; - state_j.at("numRequests").get_to(trafficState->numRequests); - state_j.at("rwRatio").get_to(trafficState->rwRatio); - state_j.at("addressDistribution").get_to(trafficState->addressDistribution); + TraceGeneratorTrafficState trafficState; + state_j.at("numRequests").get_to(trafficState.numRequests); + state_j.at("rwRatio").get_to(trafficState.rwRatio); + state_j.at("addressDistribution").get_to(trafficState.addressDistribution); if (state_j.contains("addressIncrement")) - state_j.at("addressIncrement").get_to(trafficState->addressIncrement); + state_j.at("addressIncrement").get_to(trafficState.addressIncrement); if (state_j.contains("minAddress")) - state_j.at("minAddress").get_to(trafficState->minAddress); + state_j.at("minAddress").get_to(trafficState.minAddress); if (state_j.contains("maxAddress")) - state_j.at("maxAddress").get_to(trafficState->maxAddress); + state_j.at("maxAddress").get_to(trafficState.maxAddress); if (state_j.contains("clksPerRequest")) - state_j.at("clksPerRequest").get_to(trafficState->clksPerRequest); + state_j.at("clksPerRequest").get_to(trafficState.clksPerRequest); if (state_j.contains("notify")) - state_j.at("notify").get_to(trafficState->notify); + state_j.at("notify").get_to(trafficState.notify); - state = std::unique_ptr(trafficState); + state = std::move(trafficState); } // Default to 0 @@ -217,7 +239,7 @@ void from_json(const json &j, TraceSetup &c) for (const auto &state_j : initiator_j.at("states")) { auto state = process_state(state_j); - generator->states[state.first] = std::move(state.second); + generator.states[state.first] = std::move(state.second); } for (const auto &transition_j : initiator_j.at("transitions")) @@ -226,47 +248,52 @@ void from_json(const json &j, TraceSetup &c) unsigned int from = transition_j.at("from"); transition.to = transition_j.at("to"); transition.propability = transition_j.at("propability"); - generator->transitions.emplace(from, transition); + generator.transitions.emplace(from, transition); } } else // Only one state will be created { auto state = process_state(initiator_j); - generator->states[state.first] = std::move(state.second); + generator.states[state.first] = std::move(state.second); } if (initiator_j.contains("seed")) - initiator_j.at("seed").get_to(generator->seed); + initiator_j.at("seed").get_to(generator.seed); if (initiator_j.contains("maxTransactions")) - initiator_j.at("maxTransactions").get_to(generator->maxTransactions); + initiator_j.at("maxTransactions").get_to(generator.maxTransactions); if (initiator_j.contains("idleUntil")) - initiator_j.at("idleUntil").get_to(generator->idleUntil); + initiator_j.at("idleUntil").get_to(generator.idleUntil); - initiator = std::unique_ptr(generator); + initiator = generator; } else if (type == TrafficInitiatorType::Hammer) { - TraceHammer *hammer = new TraceHammer; + TraceHammer hammer; - initiator_j.at("numRequests").get_to(hammer->numRequests); - initiator_j.at("rowIncrement").get_to(hammer->rowIncrement); + initiator_j.at("numRequests").get_to(hammer.numRequests); + initiator_j.at("rowIncrement").get_to(hammer.rowIncrement); - initiator = std::unique_ptr(hammer); + initiator = hammer; } - initiator_j.at("name").get_to(initiator->name); - initiator_j.at("clkMhz").get_to(initiator->clkMhz); + std::visit( + [&initiator_j](auto &&initiator) + { + initiator_j.at("name").get_to(initiator.name); + initiator_j.at("clkMhz").get_to(initiator.clkMhz); - if (initiator_j.contains("maxPendingReadRequests")) - initiator_j.at("maxPendingReadRequests").get_to(initiator->maxPendingReadRequests); + if (initiator_j.contains("maxPendingReadRequests")) + initiator_j.at("maxPendingReadRequests").get_to(initiator.maxPendingReadRequests); - if (initiator_j.contains("maxPendingWriteRequests")) - initiator_j.at("maxPendingWriteRequests").get_to(initiator->maxPendingWriteRequests); + if (initiator_j.contains("maxPendingWriteRequests")) + initiator_j.at("maxPendingWriteRequests").get_to(initiator.maxPendingWriteRequests); - if (initiator_j.contains("addLengthConverter")) - initiator_j.at("addLengthConverter").get_to(initiator->addLengthConverter); + if (initiator_j.contains("addLengthConverter")) + initiator_j.at("addLengthConverter").get_to(initiator.addLengthConverter); + }, + initiator); c.initiators.emplace_back(std::move(initiator)); } diff --git a/DRAMSys/library/src/common/configuration/TraceSetup.h b/DRAMSys/library/src/common/configuration/TraceSetup.h index 54298cf7..d9f0ed9a 100644 --- a/DRAMSys/library/src/common/configuration/TraceSetup.h +++ b/DRAMSys/library/src/common/configuration/TraceSetup.h @@ -38,9 +38,9 @@ #include "util.h" -#include #include #include +#include namespace DRAMSysConfiguration { @@ -117,7 +117,7 @@ struct TraceGenerator : public TrafficInitiator { std::optional seed; std::optional maxTransactions; - std::map> states; + std::map> states; std::multimap transitions; std::optional idleUntil; }; @@ -130,7 +130,7 @@ struct TraceHammer : public TrafficInitiator struct TraceSetup { - std::vector> initiators; + std::vector> initiators; }; void to_json(json &j, const TraceSetup &c); diff --git a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp index 520791f0..c0a9ac95 100644 --- a/DRAMSys/library/src/common/configuration/tests/simpletest.cpp +++ b/DRAMSys/library/src/common/configuration/tests/simpletest.cpp @@ -94,89 +94,88 @@ DRAMSysConfiguration::ThermalConfig getThermalConfig() true}; } -std::unique_ptr getTracePlayer() +DRAMSysConfiguration::TracePlayer getTracePlayer() { - DRAMSysConfiguration::TracePlayer *player = new DRAMSysConfiguration::TracePlayer; + DRAMSysConfiguration::TracePlayer player; + player.clkMhz = 100; + player.name = "mytrace.stl"; - player->clkMhz = 100; - player->name = "mytrace.stl"; - - return std::unique_ptr(player); + return player; } -std::unique_ptr getTraceGeneratorOneState() +DRAMSysConfiguration::TraceGenerator getTraceGeneratorOneState() { - DRAMSysConfiguration::TraceGenerator *gen = new DRAMSysConfiguration::TraceGenerator; + DRAMSysConfiguration::TraceGenerator gen; + gen.clkMhz = 100; + gen.name = "MyTestGen"; - gen->clkMhz = 100; - gen->name = "MyTestGen"; + DRAMSysConfiguration::TraceGeneratorTrafficState state0; + state0.numRequests = 1000; + state0.rwRatio = 0.5; + state0.addressDistribution = DRAMSysConfiguration::AddressDistribution::Random; + state0.addressIncrement = {}; + state0.minAddress = {}; + state0.maxAddress = {}; + state0.clksPerRequest = {}; - auto state0 = new DRAMSysConfiguration::TraceGeneratorTrafficState; - state0->numRequests = 1000; - state0->rwRatio = 0.5; - state0->addressDistribution = DRAMSysConfiguration::AddressDistribution::Random; - state0->addressIncrement = {}; - state0->minAddress = {}; - state0->maxAddress = {}; - state0->clksPerRequest = {}; + gen.states.emplace(0, state0); - gen->states[0] = std::unique_ptr(state0); - - return std::unique_ptr(gen); + return gen; } -std::unique_ptr getTraceGeneratorMultipleStates() +DRAMSysConfiguration::TraceGenerator getTraceGeneratorMultipleStates() { - DRAMSysConfiguration::TraceGenerator *gen = new DRAMSysConfiguration::TraceGenerator; + DRAMSysConfiguration::TraceGenerator gen; - gen->clkMhz = 100; - gen->name = "MyTestGen"; - gen->maxPendingReadRequests = 8; + gen.clkMhz = 100; + gen.name = "MyTestGen"; + gen.maxPendingReadRequests = 8; - auto state0 = new DRAMSysConfiguration::TraceGeneratorTrafficState; - state0->numRequests = 1000; - state0->rwRatio = 0.5; - state0->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; - state0->addressIncrement = 256; - state0->minAddress = {}; - state0->maxAddress = 1024; - state0->clksPerRequest = {}; + DRAMSysConfiguration::TraceGeneratorTrafficState state0; + state0.numRequests = 1000; + state0.rwRatio = 0.5; + state0.addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; + state0.addressIncrement = 256; + state0.minAddress = {}; + state0.maxAddress = 1024; + state0.clksPerRequest = {}; - auto state1 = new DRAMSysConfiguration::TraceGeneratorTrafficState; - state1->numRequests = 100; - state1->rwRatio = 0.75; - state1->addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; - state1->addressIncrement = 512; - state1->minAddress = 1024; - state1->maxAddress = 2048; - state1->clksPerRequest = {}; + DRAMSysConfiguration::TraceGeneratorTrafficState state1; + state1.numRequests = 100; + state1.rwRatio = 0.75; + state1.addressDistribution = DRAMSysConfiguration::AddressDistribution::Sequential; + state1.addressIncrement = 512; + state1.minAddress = 1024; + state1.maxAddress = 2048; + state1.clksPerRequest = {}; - gen->states[0] = std::unique_ptr(state0); - gen->states[1] = std::unique_ptr(state1); + gen.states.emplace(0, state0); + gen.states.emplace(1, state1); DRAMSysConfiguration::TraceGeneratorStateTransition transistion0{1, 1.0}; - gen->transitions.emplace(0, transistion0); + gen.transitions.emplace(0, transistion0); - return std::unique_ptr(gen); + return gen; } -std::unique_ptr getTraceHammer() +DRAMSysConfiguration::TraceHammer getTraceHammer() { - DRAMSysConfiguration::TraceHammer *hammer = new DRAMSysConfiguration::TraceHammer; + DRAMSysConfiguration::TraceHammer hammer; - hammer->clkMhz = 100; - hammer->name = "MyTestHammer"; + hammer.clkMhz = 100; + hammer.name = "MyTestHammer"; + hammer.numRequests = 4000; + hammer.rowIncrement = 2097152; - hammer->numRequests = 4000; - hammer->rowIncrement = 2097152; - - return std::unique_ptr(hammer); + return hammer; } DRAMSysConfiguration::TraceSetup getTraceSetup() { - std::vector> initiators; + using namespace DRAMSysConfiguration; + + std::vector> initiators; initiators.emplace_back(getTracePlayer()); initiators.emplace_back(getTraceGeneratorOneState()); initiators.emplace_back(getTraceGeneratorMultipleStates()); diff --git a/DRAMSys/simulator/TraceSetup.cpp b/DRAMSys/simulator/TraceSetup.cpp index 3672408d..fd6d8e54 100644 --- a/DRAMSys/simulator/TraceSetup.cpp +++ b/DRAMSys/simulator/TraceSetup.cpp @@ -45,102 +45,107 @@ using namespace sc_core; using namespace tlm; -TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, - const std::string &pathToResources, +TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup, const std::string &pathToResources, std::vector> &players) { if (traceSetup.initiators.empty()) SC_REPORT_FATAL("TraceSetup", "No traffic initiators specified"); - for (const auto &inititator : traceSetup.initiators) + for (const auto &initiator : traceSetup.initiators) { - double frequencyMHz = inititator->clkMhz; - sc_time playerClk = sc_time(1.0 / frequencyMHz, SC_US); + std::visit( + [&](auto &&initiator) + { + std::string name = initiator.name; + double frequencyMHz = initiator.clkMhz; + sc_time playerClk = sc_time(1.0 / frequencyMHz, SC_US); - std::string name = inititator->name; + unsigned int maxPendingReadRequests = [=]() -> unsigned int + { + if (const auto &maxPendingReadRequests = initiator.maxPendingReadRequests) + return *maxPendingReadRequests; + else + return 0; + }(); - unsigned int maxPendingReadRequests = [=]() -> unsigned int - { - if (const auto &maxPendingReadRequests = inititator->maxPendingReadRequests) - return *maxPendingReadRequests; - else - return 0; - }(); + unsigned int maxPendingWriteRequests = [=]() -> unsigned int + { + if (const auto &maxPendingWriteRequests = initiator.maxPendingWriteRequests) + return *maxPendingWriteRequests; + else + return 0; + }(); - unsigned int maxPendingWriteRequests = [=]() -> unsigned int - { - if (const auto &maxPendingWriteRequests = inititator->maxPendingWriteRequests) - return *maxPendingWriteRequests; - else - return 0; - }(); + bool addLengthConverter = [=]() -> bool + { + if (const auto &addLengthConverter = initiator.addLengthConverter) + return *addLengthConverter; + else + return false; + }(); - bool addLengthConverter = [=]() -> bool - { - if (const auto &addLengthConverter = inititator->addLengthConverter) - return *addLengthConverter; - else - return false; - }(); + using T = std::decay_t; + if constexpr (std::is_same_v) + { + size_t pos = name.rfind('.'); + if (pos == std::string::npos) + throw std::runtime_error("Name of the trace file does not contain a valid extension."); - if (std::dynamic_pointer_cast(inititator)) - { - size_t pos = name.rfind('.'); - if (pos == std::string::npos) - throw std::runtime_error("Name of the trace file does not contain a valid extension."); + // Get the extension and make it lower case + std::string ext = name.substr(pos + 1); + std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); - // Get the extension and make it lower case - std::string ext = name.substr(pos + 1); - std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower); + std::stringstream stlFileStream; + stlFileStream << pathToResources << "/traces/" << name; + std::string stlFile = stlFileStream.str(); + std::string moduleName = name; - std::stringstream stlFileStream; - stlFileStream << pathToResources << "/traces/" << name; - std::string stlFile = stlFileStream.str(); - std::string moduleName = name; + // replace all '.' to '_' + std::replace(moduleName.begin(), moduleName.end(), '.', '_'); - // replace all '.' to '_' - std::replace(moduleName.begin(), moduleName.end(), '.', '_'); + StlPlayer *player; + if (ext == "stl") + player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, maxPendingReadRequests, + maxPendingWriteRequests, addLengthConverter, this, false); + else if (ext == "rstl") + player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, maxPendingReadRequests, + maxPendingWriteRequests, addLengthConverter, this, true); + else + throw std::runtime_error("Unsupported file extension in " + name); - StlPlayer *player; - if (ext == "stl") - player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, - maxPendingReadRequests, maxPendingWriteRequests, addLengthConverter, this, false); - else if (ext == "rstl") - player = new StlPlayer(moduleName.c_str(), stlFile, playerClk, - maxPendingReadRequests, maxPendingWriteRequests, addLengthConverter, this, true); - else - throw std::runtime_error("Unsupported file extension in " + name); + players.push_back(std::unique_ptr(player)); + totalTransactions += player->getNumberOfLines(); + } + else if constexpr (std::is_same_v) + { + TrafficGenerator *trafficGenerator = new TrafficGenerator(name.c_str(), initiator, this); + players.push_back(std::unique_ptr(trafficGenerator)); - players.push_back(std::unique_ptr(player)); - totalTransactions += player->getNumberOfLines(); - } - else if (auto generator = std::dynamic_pointer_cast(inititator)) - { - TrafficGenerator *trafficGenerator = new TrafficGenerator(name.c_str(), *generator, this); - players.push_back(std::unique_ptr(trafficGenerator)); + totalTransactions += trafficGenerator->getTotalTransactions(); + } + else // if constexpr (std::is_same_v) + { + uint64_t numRequests = initiator.numRequests; + uint64_t rowIncrement = initiator.rowIncrement; - totalTransactions += trafficGenerator->getTotalTransactions(); - } - else if (auto hammer = std::dynamic_pointer_cast(inititator)) - { - uint64_t numRequests = hammer->numRequests; - uint64_t rowIncrement = hammer->rowIncrement; - - players.push_back(std::unique_ptr(new TrafficGeneratorHammer(name.c_str(), *hammer, this))); - totalTransactions += numRequests; - } + players.push_back( + std::unique_ptr(new TrafficGeneratorHammer(name.c_str(), initiator, this))); + totalTransactions += numRequests; + } + }, + initiator); } for (const auto &inititatorConf : traceSetup.initiators) { - if (auto generatorConf = std::dynamic_pointer_cast(inititatorConf)) + if (auto generatorConf = std::get_if(&inititatorConf)) { if (const auto &idleUntil = generatorConf->idleUntil) { const std::string name = generatorConf->name; - auto listenerIt = - std::find_if(players.begin(), players.end(), - [&name](const std::unique_ptr &initiator) { return initiator->name() == name; }); + auto listenerIt = std::find_if(players.begin(), players.end(), + [&name](const std::unique_ptr &initiator) + { return initiator->name() == name; }); // Should be found auto listener = dynamic_cast(listenerIt->get()); @@ -205,7 +210,7 @@ void TraceSetup::loadBar(uint64_t x, uint64_t n, unsigned int w, unsigned int gr if ((n < 100) || ((x != n) && (x % (n / 100 * granularity) != 0))) return; - float ratio = x / (float) n; + float ratio = x / (float)n; unsigned int c = (ratio * w); float rest = (ratio * w) - c; std::cout << std::setw(3) << round(ratio * 100) << "% |"; diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 1598a82b..7706840c 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -37,6 +37,7 @@ */ #include "TrafficGenerator.h" +#include "TraceSetup.h" #include @@ -103,7 +104,7 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf // Perform checks for all states for (const auto &state : conf.states) { - if (auto trafficState = dynamic_cast(state.second.get())) + if (auto trafficState = std::get_if(&state.second)) { uint64_t minAddress = evaluateMinAddress(*trafficState); uint64_t maxAddress = evaluateMaxAddress(*trafficState); @@ -129,7 +130,8 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name, const DRAMSysConf } } - if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) + if (auto trafficState = + std::get_if(&conf.states.at(currentState))) { uint64_t minAddress = evaluateMinAddress(*trafficState); uint64_t maxAddress = evaluateMaxAddress(*trafficState); @@ -182,7 +184,8 @@ void TrafficGenerator::calculateTransitions() if (transitionFound) { - if (auto trafficState = dynamic_cast(conf.states.at(state).get())) + if (auto trafficState = + std::get_if(&conf.states.at(state))) totalTransactions += trafficState->numRequests; if (totalTransactions < maxTransactions) @@ -221,7 +224,7 @@ uint64_t TrafficGenerator::getTotalTransactions() const for (auto state : stateSequence) { - if (auto trafficState = dynamic_cast(conf.states.at(state).get())) + if (auto trafficState = std::get_if(&conf.states.at(state))) totalTransactions += trafficState->numRequests; } @@ -256,13 +259,14 @@ void TrafficGenerator::transitionToNextState() it.second.event.notify(); } - if (auto idleState = dynamic_cast(conf.states.at(currentState).get())) + if (auto idleState = std::get_if(&conf.states.at(currentState))) { currentClksToIdle += idleState->idleClks; transitionToNextState(); return; } - else if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) + else if (auto trafficState = + std::get_if(&conf.states.at(currentState))) { uint64_t minAddress = evaluateMinAddress(*trafficState); uint64_t maxAddress = evaluateMaxAddress(*trafficState); @@ -285,7 +289,8 @@ void TrafficGenerator::prepareNextPayload() if (startEvent && transactionsSent == 0) wait(*startEvent); - if (auto trafficState = dynamic_cast(conf.states.at(currentState).get())) + if (auto trafficState = + std::get_if(&conf.states.at(currentState))) { if (transactionsSentInCurrentState >= trafficState->numRequests) transitionToNextState(); @@ -303,10 +308,10 @@ void TrafficGenerator::payloadSent() tlm::tlm_command TrafficGenerator::getNextCommand() { // An idle state should never reach this method. - auto state = static_cast(conf.states.at(currentState).get()); + auto &state = std::get(conf.states.at(currentState)); tlm_command command; - if (randomDistribution(randomGenerator) < state->rwRatio) + if (randomDistribution(randomGenerator) < state.rwRatio) command = tlm::TLM_READ_COMMAND; else command = tlm::TLM_WRITE_COMMAND; @@ -324,14 +329,14 @@ uint64_t TrafficGenerator::getNextAddress() using DRAMSysConfiguration::AddressDistribution; // An idle state should never reach this method. - auto state = static_cast(conf.states.at(currentState).get()); + auto &state = std::get(conf.states.at(currentState)); - uint64_t minAddress = evaluateMinAddress(*state); - uint64_t maxAddress = evaluateMaxAddress(*state); + uint64_t minAddress = evaluateMinAddress(state); + uint64_t maxAddress = evaluateMaxAddress(state); - if (state->addressDistribution == AddressDistribution::Sequential) + if (state.addressDistribution == AddressDistribution::Sequential) { - uint64_t addressIncrement = state->addressIncrement.value_or(defaultAddressIncrement); + uint64_t addressIncrement = state.addressIncrement.value_or(defaultAddressIncrement); uint64_t address = currentAddress; currentAddress += addressIncrement; @@ -339,7 +344,7 @@ uint64_t TrafficGenerator::getNextAddress() currentAddress = minAddress; return address; } - else if (state->addressDistribution == AddressDistribution::Random) + else if (state.addressDistribution == AddressDistribution::Random) { return randomAddressDistribution(randomGenerator); } From 0c47ea1a34499577ac3819e4aeaa45ad976f56b1 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 28 Feb 2022 11:43:34 +0100 Subject: [PATCH 23/23] Fix a bug when the first state is an idle state. --- DRAMSys/simulator/TrafficGenerator.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/DRAMSys/simulator/TrafficGenerator.cpp b/DRAMSys/simulator/TrafficGenerator.cpp index 7706840c..33e90032 100644 --- a/DRAMSys/simulator/TrafficGenerator.cpp +++ b/DRAMSys/simulator/TrafficGenerator.cpp @@ -295,6 +295,15 @@ void TrafficGenerator::prepareNextPayload() if (transactionsSentInCurrentState >= trafficState->numRequests) transitionToNextState(); } + + // In case we are in an idle state right at the beginning of the simulation, + // set the clksToIdle and transition to the next state. + if (auto idleState = + std::get_if(&conf.states.at(currentState))) + { + currentClksToIdle = idleState->idleClks; + transitionToNextState(); + } } void TrafficGenerator::payloadSent()