diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index bbd5437d..75e982f1 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -147,7 +147,7 @@ public: struct CommandTuple { - using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_core::sc_time>; + using Type = std::tuple<::Command, tlm::tlm_generic_payload*, sc_core::sc_time>; enum Accessor { Command = 0, diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index f5c4d042..2c9689c6 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -303,11 +303,11 @@ void Controller::controllerMethod() { commandTuple = cmdMux->selectCommand(readyCommands); Command command = std::get(commandTuple); - tlm_generic_payload *payload = std::get(commandTuple); + tlm_generic_payload* trans = std::get(commandTuple); if (command != Command::NOP) // can happen with FIFO strict { - Rank rank = ControllerExtension::getRank(*payload); - Bank bank = ControllerExtension::getBank(*payload); + Rank rank = ControllerExtension::getRank(*trans); + Bank bank = ControllerExtension::getBank(*trans); if (command.isRankCommand()) { @@ -330,16 +330,16 @@ void Controller::controllerMethod() refreshManagers[rank.ID()]->updateState(command); powerDownManagers[rank.ID()]->updateState(command); - checker->insert(command, *payload); + checker->insert(command, *trans); if (command.isCasCommand()) { - scheduler->removeRequest(*payload); + scheduler->removeRequest(*trans); manageRequests(thinkDelayFw); - respQueue->insertPayload(payload, sc_time_stamp() - + thinkDelayFw + phyDelayFw - + memSpec.getIntervalOnDataStrobe(command, *payload).end - + phyDelayBw + thinkDelayBw); + respQueue->insertPayload(trans, sc_time_stamp() + + thinkDelayFw + phyDelayFw + + memSpec.getIntervalOnDataStrobe(command, *trans).end + + phyDelayBw + thinkDelayBw); sc_time triggerTime = respQueue->getTriggerTime(); if (triggerTime != sc_max_time()) @@ -352,7 +352,7 @@ void Controller::controllerMethod() sc_time fwDelay = thinkDelayFw + phyDelayFw; tlm_phase phase = command.toPhase(); - iSocket->nb_transport_fw(*payload, phase, fwDelay); + iSocket->nb_transport_fw(*trans, phase, fwDelay); } else readyCmdBlocked = true; @@ -384,18 +384,17 @@ void Controller::controllerMethod() controllerEvent.notify(timeForNextTrigger - sc_time_stamp()); } -tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay) +tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay) { if (phase == BEGIN_REQ) { transToAcquire.payload = &trans; - transToAcquire.time = sc_time_stamp() + delay; + transToAcquire.arrival = sc_time_stamp() + delay; beginReqEvent.notify(delay); } else if (phase == END_RESP) { - transToRelease.time = sc_time_stamp() + delay; + transToRelease.arrival = sc_time_stamp() + delay; endRespEvent.notify(delay); } else @@ -407,27 +406,26 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &, - tlm_phase &, sc_time &) +tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& ,tlm_phase& , sc_time&) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!"); return TLM_ACCEPTED; } -void Controller::b_transport(tlm_generic_payload &trans, sc_time &delay) +void Controller::b_transport(tlm_generic_payload& trans, sc_time& delay) { iSocket->b_transport(trans, delay); delay += trans.is_write() ? blockingWriteDelay : blockingReadDelay; } -unsigned int Controller::transport_dbg(tlm_generic_payload &trans) +unsigned int Controller::transport_dbg(tlm_generic_payload& trans) { return iSocket->transport_dbg(trans); } -void Controller::manageRequests(const sc_time &delay) +void Controller::manageRequests(const sc_time& delay) { - if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp()) + if (transToAcquire.payload != nullptr && transToAcquire.arrival <= sc_time_stamp()) { // TODO: here we assume that the scheduler always has space not only for a single burst transaction // but for a maximum size transaction @@ -499,8 +497,8 @@ void Controller::manageResponses() { if (transToRelease.payload != nullptr) { - assert(transToRelease.time >= sc_time_stamp()); - if (transToRelease.time == sc_time_stamp()) // END_RESP completed + assert(transToRelease.arrival >= sc_time_stamp()); + if (transToRelease.arrival == sc_time_stamp()) // END_RESP completed { transToRelease.payload->release(); transToRelease.payload = nullptr; @@ -515,25 +513,25 @@ void Controller::manageResponses() return; // END_RESP not completed } - tlm_generic_payload* nextPayloadInRespQueue = respQueue->nextPayload(); - if (nextPayloadInRespQueue != nullptr) + tlm_generic_payload* nextTransInRespQueue = respQueue->nextPayload(); + if (nextTransInRespQueue != nullptr) { - numberOfBeatsServed += ControllerExtension::getBurstLength(*nextPayloadInRespQueue); - if (ChildExtension::isChildTrans(*nextPayloadInRespQueue)) + numberOfBeatsServed += ControllerExtension::getBurstLength(*nextTransInRespQueue); + if (ChildExtension::isChildTrans(*nextTransInRespQueue)) { - tlm_generic_payload& parentTrans = ChildExtension::getParentTrans(*nextPayloadInRespQueue); + tlm_generic_payload& parentTrans = ChildExtension::getParentTrans(*nextTransInRespQueue); if (ParentExtension::notifyChildTransCompletion(parentTrans)) { transToRelease.payload = &parentTrans; tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay; - if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle + if (transToRelease.arrival == sc_time_stamp()) // last payload was released in this cycle bwDelay = memSpec.tCK; else bwDelay = SC_ZERO_TIME; sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); + transToRelease.arrival = sc_max_time(); } else { @@ -544,16 +542,16 @@ void Controller::manageResponses() } else { - transToRelease.payload = nextPayloadInRespQueue; + transToRelease.payload = nextTransInRespQueue; tlm_phase bwPhase = BEGIN_RESP; sc_time bwDelay; - if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle + if (transToRelease.arrival == sc_time_stamp()) // last payload was released in this cycle bwDelay = memSpec.tCK; else bwDelay = SC_ZERO_TIME; sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); - transToRelease.time = sc_max_time(); + transToRelease.arrival = sc_max_time(); } } else @@ -564,19 +562,19 @@ void Controller::manageResponses() } } -void Controller::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay) +void Controller::sendToFrontend(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay) { - tSocket->nb_transport_bw(payload, phase, delay); + tSocket->nb_transport_bw(trans, phase, delay); } Controller::MemoryManager::~MemoryManager() { while (!freePayloads.empty()) { - tlm_generic_payload* payload = freePayloads.top(); + tlm_generic_payload* trans = freePayloads.top(); freePayloads.pop(); - payload->reset(); - delete payload; + trans->reset(); + delete trans; } } @@ -595,9 +593,9 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate() } } -void Controller::MemoryManager::free(tlm::tlm_generic_payload* payload) +void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans) { - freePayloads.push(payload); + freePayloads.push(trans); } void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans) diff --git a/src/libdramsys/DRAMSys/controller/Controller.h b/src/libdramsys/DRAMSys/controller/Controller.h index 5630b763..b8e190d7 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.h +++ b/src/libdramsys/DRAMSys/controller/Controller.h @@ -93,10 +93,10 @@ private: const AddressDecoder& addressDecoder; uint64_t nextChannelPayloadIDToAppend = 1; - struct Transaction + struct PayloadAndArrival { tlm::tlm_generic_payload* payload = nullptr; - sc_core::sc_time time = sc_core::sc_max_time(); + sc_core::sc_time arrival = sc_core::sc_max_time(); } transToAcquire, transToRelease; void manageResponses(); @@ -116,7 +116,7 @@ private: public: ~MemoryManager() override; tlm::tlm_generic_payload& allocate(); - void free(tlm::tlm_generic_payload* payload) override; + void free(tlm::tlm_generic_payload* trans) override; private: std::stack freePayloads; diff --git a/src/libdramsys/DRAMSys/controller/ControllerIF.h b/src/libdramsys/DRAMSys/controller/ControllerIF.h index 3de43506..920c581d 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerIF.h +++ b/src/libdramsys/DRAMSys/controller/ControllerIF.h @@ -121,10 +121,10 @@ protected: // Virtual transport functions virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) = 0; - virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans) = 0; - virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) = 0; virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) = 0; + virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) = 0; + virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans) = 0; // Bandwidth related class IdleTimeCollector