From 04a59c8bd23461ba61f03d8b03b678c8f3ee15ed Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 15 Oct 2019 16:03:34 +0200 Subject: [PATCH] Changed MemSpec::getExecutionTime() for different tRCDs. --- .../src/configuration/memspec/MemSpec.h | 2 +- .../src/configuration/memspec/MemSpecDDR3.cpp | 28 ++++++++-------- .../src/configuration/memspec/MemSpecDDR3.h | 2 +- .../src/configuration/memspec/MemSpecDDR4.cpp | 28 ++++++++-------- .../src/configuration/memspec/MemSpecDDR4.h | 2 +- .../src/configuration/memspec/MemSpecHBM2.cpp | 11 +++++-- .../src/configuration/memspec/MemSpecHBM2.h | 2 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 2 +- .../src/configuration/memspec/MemSpecLPDDR4.h | 2 +- .../configuration/memspec/MemSpecWideIO.cpp | 32 +++++++++---------- .../src/configuration/memspec/MemSpecWideIO.h | 2 +- .../configuration/memspec/MemSpecWideIO2.cpp | 32 +++++++++---------- .../configuration/memspec/MemSpecWideIO2.h | 2 +- DRAMSys/library/src/simulation/dram/Dram.cpp | 18 +++++------ .../src/simulation/dram/DramRecordable.cpp | 6 ++-- .../src/simulation/dram/DramWideIO.cpp | 18 +++++------ 16 files changed, 97 insertions(+), 92 deletions(-) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index dbb28264..0e95ed05 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -59,7 +59,7 @@ struct MemSpec virtual sc_time getRefreshIntervalAB() const = 0; virtual sc_time getRefreshIntervalPB() const = 0; - virtual sc_time getExecutionTime(Command) const = 0; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; unsigned getCommandLength(Command) const; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 16a5a75d..30e04c29 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -46,21 +46,8 @@ sc_time MemSpecDDR3::getRefreshIntervalPB() const return SC_ZERO_TIME; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command) const +sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -86,3 +73,16 @@ sc_time MemSpecDDR3::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 0d05e964..c8c7beac 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -81,7 +81,7 @@ struct MemSpecDDR3 final : public MemSpec virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 7c413340..ca0deeee 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -46,21 +46,8 @@ sc_time MemSpecDDR4::getRefreshIntervalPB() const return SC_ZERO_TIME; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command) const +sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -86,3 +73,16 @@ sc_time MemSpecDDR4::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 3dd13a1e..ecadfc18 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -87,7 +87,7 @@ struct MemSpecDDR4 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 190aa56f..7fa61d1b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -50,12 +50,17 @@ sc_time MemSpecHBM2::getRefreshIntervalPB() const return tREFISB; } -sc_time MemSpecHBM2::getExecutionTime(Command command) const +sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload &payload) const { if (command == Command::PRE || command == Command::PREA) return tRP; - else if (command == Command::ACT) // TODO: read or write? - return tRCDRD + clk; + else if (command == Command::ACT) + { + if (payload.get_command() == TLM_READ_COMMAND) + return tRCDRD + clk; + else + return tRCDWR + clk; + } else if (command == Command::RD || command == Command::RDA) return tRL + tDQSCK + getReadAccessTime(); else if (command == Command::WR || command == Command::WRA) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 5c5d5a8f..d09c31c9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -85,7 +85,7 @@ struct MemSpecHBM2 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 2de71159..50afd825 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -60,7 +60,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE) return tRPpb + clk; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index af42c2ce..67738e4e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -78,7 +78,7 @@ struct MemSpecLPDDR4 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index b5e9a90f..5b4c5316 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -46,23 +46,8 @@ sc_time MemSpecWideIO::getRefreshIntervalPB() const return SC_ZERO_TIME; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tAC, - sc_time_stamp() + tRL + tAC + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, - sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command) const +sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -86,3 +71,18 @@ sc_time MemSpecWideIO::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tAC, + sc_time_stamp() + tRL + tAC + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, + sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 3d5715a3..e504c63b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -91,7 +91,7 @@ struct MemSpecWideIO final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index a163acf4..7d122e17 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -45,23 +45,8 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const return tREFIpb; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK, - sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tDQSS, - sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE) return tRPpb; @@ -84,3 +69,18 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tDQSCK, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tDQSS, + sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 129947d3..4caff1e4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -72,7 +72,7 @@ struct MemSpecWideIO2 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index f2244acd..9f5cb4ef 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -128,18 +128,18 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); } else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PREA, - delay + memSpec->getExecutionTime(Command::PREA)); + delay + memSpec->getExecutionTime(Command::PREA, payload)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT)); + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); } else if (phase == BEGIN_WR) { @@ -150,7 +150,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR)); + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); } else if (phase == BEGIN_RD) { @@ -161,7 +161,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD)); + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); } else if (phase == BEGIN_WRA) { @@ -172,7 +172,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA)); + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } else if (phase == BEGIN_RDA) { @@ -183,19 +183,19 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA)); + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } else if (phase == BEGIN_REFB) { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFB)); + delay + memSpec->getExecutionTime(Command::REFB, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 279ccf1d..f52ee002 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -86,11 +86,11 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += this->memSpec->getExecutionTime(Command::PDXA); + recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += this->memSpec->getExecutionTime(Command::PDXP); + recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); else if (phase == END_SREF || phase == END_SREFB) - recTime += this->memSpec->getExecutionTime(Command::SREFEX); + recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch __attribute__((unused)) = DramExtension::getExtension(payload).getChannel().ID(); diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 2a320879..232e3224 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -183,18 +183,18 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); } else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PREA, - delay + memSpec->getExecutionTime(Command::PREA)); + delay + memSpec->getExecutionTime(Command::PREA, payload)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT)); + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -213,7 +213,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR)); + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); } else if (phase == BEGIN_RD) { @@ -228,7 +228,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD)); + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); } else if (phase == BEGIN_WRA) { @@ -243,7 +243,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA)); + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } else if (phase == BEGIN_RDA) { @@ -258,13 +258,13 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA)); + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -274,7 +274,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA)