diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 8d69ad8a..100411cb 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -131,8 +131,14 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (currentTransactionsInSystem[&trans].cmd == 'X') { - if (phase == END_REFA || phase == END_RFMAB || phase == END_REFB || phase == END_REFSB - || phase == END_PDNA || phase == END_PDNP || phase == END_SREF) + if (phase == END_REFA + || phase == END_RFMAB + || phase == END_REFB + || phase == END_REFSB + || phase == END_RFMSB + || phase == END_PDNA + || phase == END_PDNP + || phase == END_SREF) removeTransactionFromSystem(trans); } else diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index cef7fb3b..a3aa091c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -238,7 +238,7 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload } else if (command == Command::REFA || command == Command::RFMAB) return tRFC_slr + shortCmdOffset; - else if (command == Command::REFSB) + else if (command == Command::REFSB || command == Command::RFMSB) return tRFCsb_slr + shortCmdOffset; else { diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 74d17ab6..153954eb 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -75,7 +75,7 @@ void BankMachine::updateState(Command command) case Command::PDEA: case Command::PDEP: case Command::SREFEN: sleeping = true; break; - case Command::REFA: case Command::REFB: case Command::REFSB: case Command::RFMAB: + case Command::REFA: case Command::REFB: case Command::REFSB: case Command::RFMAB: case Command::RFMSB: sleeping = false; blocked = false; diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 8ba7167c..37a1e505 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -183,7 +183,7 @@ bool Command::isBankCommand() const bool Command::isGroupCommand() const { assert(type >= Command::NOP && type <= Command::SREFEX); - return (type >= Command::PRESB && type <= Command::REFSB); + return (type >= Command::PRESB && type <= Command::RFMSB); } bool Command::isRankCommand() const diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index 8e21de31..f7758832 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -578,6 +578,18 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_dlr - cmdLengthDiff); + lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RFMSB][bankInGroup.ID()]; + if (lastCommandStart != sc_max_time()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_slr - cmdLengthDiff); + + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RFMSB][logicalRank.ID()]; + if (lastCommandStart != sc_max_time()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_slr - cmdLengthDiff); + + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RFMSB][physicalRank.ID()]; + if (lastCommandStart != sc_max_time()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tREFSBRD_dlr - cmdLengthDiff); + if (last4ActivatesLogical[logicalRank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalRank.ID()].front() + memSpec->tFAW_slr - memSpec->longCmdOffset); @@ -755,7 +767,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo // REFSB tRFCsb_slr/dlr // PRESB tRP } - else if (command == Command::REFSB) + else if (command == Command::REFSB || command == Command::RFMSB) { lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) @@ -824,6 +836,14 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo if (lastCommandStart != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_dlr); + lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RFMSB][logicalRank.ID()]; + if (lastCommandStart != sc_max_time()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_slr); + + lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RFMSB][physicalRank.ID()]; + if (lastCommandStart != sc_max_time()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_dlr); + if (last4ActivatesLogical[logicalRank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalRank.ID()].front() + memSpec->tFAW_slr - memSpec->shortCmdOffset); @@ -889,7 +909,7 @@ void CheckerDDR5::insert(Command command, tlm_generic_payload *payload) lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK; - if (command == Command::ACT || command == Command::REFSB) + if (command == Command::ACT || command == Command::REFSB || command == Command::RFMSB) { if (last4ActivatesLogical[logicalRank.ID()].size() == 4) last4ActivatesLogical[logicalRank.ID()].pop(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp index 54026072..824c80a3 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp @@ -65,11 +65,12 @@ sc_time RefreshManagerAllBank::start() timeToSchedule = sc_max_time(); nextCommand = Command::NOP; +// TODO nach unten ziehen, und in BM auslagern.... bool RFMRequired = false; if(Configuration::getInstance().RFM == true) { for(auto bm : bankMachinesOnRank) { - uint64_t threshold = Configuration::getInstance().memSpec->getRAAIMT() * Configuration::getInstance().memSpec->getRAAMMT(); + uint64_t threshold = memSpec->getRAAIMT() * memSpec->getRAAMMT(); if(bm->getRFMCounter() >= threshold) { RFMRequired = true; break; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp index 0def8fd8..0c333691 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp @@ -206,7 +206,48 @@ sc_time RefreshManagerSameBank::start() } } else - return timeForNextTrigger; + { + bool RFMRequired = false; + if (Configuration::getInstance().RFM == true) + { + for (auto bankIt = allBankMachines.begin(); bankIt != allBankMachines.end(); bankIt++) + { + for (auto bm : *bankIt) + { + uint64_t threshold = memSpec->getRAAIMT() * memSpec->getRAAMMT(); + if (bm->getRFMCounter() >= threshold) + { + RFMRequired = true; + currentIterator = bankIt; + break; + } + } + } + } + + if (RFMRequired) + { + nextCommand = Command::RFMSB; + for (auto it : *currentIterator) + { + if (it->getState() == BankMachine::State::Activated) + { + nextCommand = Command::PRESB; + break; + } + } + + for (auto it : *currentIterator) + it->block(); + + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]); + return timeToSchedule; + } + else + { + return timeForNextTrigger; + } + } } void RefreshManagerSameBank::updateState(Command command) diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h index 1b05211b..822fec5d 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.h @@ -413,6 +413,27 @@ protected: } }; +class RFMSB : public AUTO_REFRESH +{ +public: + using AUTO_REFRESH::AUTO_REFRESH; +protected: + virtual QString Name() const override + { + return "RFMSB"; + } + virtual Granularity getGranularity() const override + { + return Granularity::Groupwise; + } + virtual QColor getPhaseColor() const override + { + QColor phaseColor = QColor(Qt::darkRed); + phaseColor.setAlpha(130); + return phaseColor; + } +}; + class PDNAB : public Phase { public: diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 5496f5b5..9afa91e1 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -85,6 +85,9 @@ shared_ptr PhaseFactory::CreatePhase(ID id, const QString &dbPhaseName, else if (dbPhaseName == "REFSB") return shared_ptr(new REFSB(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.REFSB)}, std::shared_ptr())); + else if (dbPhaseName == "RFMSB") + return shared_ptr(new RFMSB(id, span, clk, trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.RFMSB)}, std::shared_ptr())); else if (dbPhaseName == "RD") return shared_ptr(new RD(id, span, clk, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)}, std::shared_ptr(new Timespan(trans->spanOnDataStrobe)))); diff --git a/DRAMSys/traceAnalyzer/scripts/vcdExport.py b/DRAMSys/traceAnalyzer/scripts/vcdExport.py index 976c94ff..2e449458 100755 --- a/DRAMSys/traceAnalyzer/scripts/vcdExport.py +++ b/DRAMSys/traceAnalyzer/scripts/vcdExport.py @@ -88,7 +88,7 @@ class Granularity(enum.Enum): Rankwise = 2 def getGranularity(phase): - if phase == "PRESB" or phase == "REFSB": + if phase == "PRESB" or phase == "REFSB" or phase == "RFMSB": return Granularity.Groupwise elif phase == "PREA" or phase == "REFA" or phase=="RFMAB" or phase == "PDNA" or phase == "PDNP" or phase == "SREF": return Granularity.Rankwise