From 025de139269fa60f48296c05ed5bffc9dac29e71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Wed, 6 Jul 2016 10:11:25 +0200 Subject: [PATCH] Simple initiator changed to write to the memory and read through transport_dgb XXX: this implementation is not fully functional. --- DRAMSys/simulator/src/simulation/Arbiter.h | 9 ++++ DRAMSys/simulator/src/simulation/Dram.h | 7 ++-- .../simulator/src/simulation/Simulation.cpp | 2 +- .../src/simulation/exampleinitiator.h | 41 ++++++++++++++++--- 4 files changed, 49 insertions(+), 10 deletions(-) diff --git a/DRAMSys/simulator/src/simulation/Arbiter.h b/DRAMSys/simulator/src/simulation/Arbiter.h index 5e190451..6d1bee1f 100644 --- a/DRAMSys/simulator/src/simulation/Arbiter.h +++ b/DRAMSys/simulator/src/simulation/Arbiter.h @@ -76,6 +76,8 @@ public: // As soon the arbiter receives a request in any of its target sockets it should treat and forward it to the proper memory channel. tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw); + tSocket.register_transport_dbg(this, &Arbiter::transport_dbg); + for (size_t i = 0; i < Configuration::getInstance().NumberOfTracePlayers; ++i) { receivedResponses.push_back(queue()); } @@ -134,6 +136,13 @@ private: return TLM_ACCEPTED; } + virtual unsigned int transport_dbg(int id, tlm::tlm_generic_payload &trans) + { + //appendDramExtension(id, trans); + //trans.acquire(); + return iSocket[id]->transport_dbg(trans); + } + void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase) { unsigned int initiatorSocket = DramExtension::getExtension(payload).getThread().ID()-1; diff --git a/DRAMSys/simulator/src/simulation/Dram.h b/DRAMSys/simulator/src/simulation/Dram.h index 0d7f95a6..89e08283 100644 --- a/DRAMSys/simulator/src/simulation/Dram.h +++ b/DRAMSys/simulator/src/simulation/Dram.h @@ -536,17 +536,18 @@ struct Dram : sc_module sc_dt::uint64 adr = trans.get_address(); // TODO: - offset; unsigned char* ptr = trans.get_data_ptr(); unsigned int len = trans.get_data_length(); - unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); + //unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); if ( cmd == tlm::TLM_READ_COMMAND ) { if (ErrorStoreMode == ErrorStorageMode::Store) // Use Storage { memcpy(ptr,&memory[adr], len); + //memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8); } else { - ememory[bank]->load(trans); + //ememory[bank]->load(trans); } } else if ( cmd == tlm::TLM_WRITE_COMMAND ) @@ -557,7 +558,7 @@ struct Dram : sc_module } else { - ememory[bank]->store(trans); + //ememory[bank]->store(trans); } } return len; diff --git a/DRAMSys/simulator/src/simulation/Simulation.cpp b/DRAMSys/simulator/src/simulation/Simulation.cpp index e842fa52..186d4b81 100644 --- a/DRAMSys/simulator/src/simulation/Simulation.cpp +++ b/DRAMSys/simulator/src/simulation/Simulation.cpp @@ -148,7 +148,7 @@ void Simulation::instantiateModules(const string &traceName, const string &pathT arbiter = new Arbiter<128>("arbiter"); arbiter->setTlmRecorders(tlmRecorders); - init = new ExampleInitiator<128>("init", this); + init = new ExampleInitiator<>("init"); for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); diff --git a/DRAMSys/simulator/src/simulation/exampleinitiator.h b/DRAMSys/simulator/src/simulation/exampleinitiator.h index c01d4fe0..568cdf81 100644 --- a/DRAMSys/simulator/src/simulation/exampleinitiator.h +++ b/DRAMSys/simulator/src/simulation/exampleinitiator.h @@ -55,14 +55,21 @@ struct ExampleInitiator: sc_module trans->release(); #endif +#if 1 + for (unsigned i = 0; i < 16; i++) { + data[i] = 0xaa55aa55; + } +#endif + // Generate a sequence of random transactions for (int i = 0; i < 1000; i++) { //int adr = rand(); - int adr = 0; + int adr = i % 256; //tlm::tlm_command cmd = static_cast(rand() % 2); - tlm::tlm_command cmd = tlm::TLM_READ_COMMAND; - if (cmd == tlm::TLM_WRITE_COMMAND) data[i % 16] = adr; + //tlm::tlm_command cmd = tlm::TLM_READ_COMMAND; + tlm::tlm_command cmd = tlm::TLM_WRITE_COMMAND; + //if (cmd == tlm::TLM_WRITE_COMMAND) data[i % 16] = adr; // Grab a new transaction from the memory manager trans = m_mm.allocate(); @@ -70,7 +77,7 @@ struct ExampleInitiator: sc_module trans->set_command( cmd ); trans->set_address( adr ); - trans->set_data_ptr( reinterpret_cast(&data[i % 16]) ); + trans->set_data_ptr( reinterpret_cast(&data[0]) ); trans->set_data_length( 4 ); trans->set_streaming_width( 4 ); trans->set_byte_enable_ptr( 0 ); @@ -88,7 +95,7 @@ struct ExampleInitiator: sc_module delay = sc_time(100000, SC_PS); cout << hex << adr << " new, cmd=" << (cmd ? "write" : "read") - << ", data=" << hex << data[i % 16] << " at time " << sc_time_stamp() + << ", data=" << hex << data[0] << " at time " << sc_time_stamp() << " in " << name() << endl; GenerationExtension* genExtension = new GenerationExtension(sc_time_stamp()); @@ -116,11 +123,33 @@ struct ExampleInitiator: sc_module // Allow the memory manager to free the transaction object trans->release(); } + + dump_memories(); + //wait( sc_time(rand_ps(), SC_PS) ); wait( sc_time(50000, SC_PS) ); } } + void dump_memories() + { + for (sc_dt::uint64 addr = 0; addr <= 256; addr += 256) + { + int buffer[64]; + tlm::tlm_generic_payload trans; + trans.set_command( tlm::TLM_READ_COMMAND ); + trans.set_address( addr ); + trans.set_data_ptr( reinterpret_cast(buffer) ); + trans.set_data_length( 16 ); + + socket->transport_dbg( trans ); + + cout << "\nMemory dump\n"; + for (int i = 0; i < 64; i++) + cout << "mem[" << addr + i*4 << "] = " << buffer[i] << endl; + } + } + // TLM-2 backward non-blocking transport method virtual tlm::tlm_sync_enum nb_transport_bw( tlm::tlm_generic_payload& trans, @@ -184,7 +213,7 @@ struct ExampleInitiator: sc_module } MemoryManager m_mm; - int data[16]; + int data[16]; tlm::tlm_generic_payload* request_in_progress; sc_event end_request_event; tlm_utils::peq_with_cb_and_phase m_peq;